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llvm-project
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The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. Note: the repository does not accept github pull requests at this moment. Please submit your patches at…
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GNU toolchain for RISC-V, including GCC
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Documentation of the RISC-V C API
651 contributions in the last year
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Contribution activity
May 2025
Created 2 commits in 1 repository
Reviewed 22 pull requests in 1 repository
llvm/llvm-project
22 pull requests
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[RISCV] Add Zilsd/Zclsd support to RISCVMakeCompressible.
This contribution was made on May 16
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[RISCV] Add Zilsd to RISCVMergeBaseOffset.
This contribution was made on May 16
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[RISCV] Disable combineToVCPOP for illegal scalable vector types.
This contribution was made on May 16
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[RISCV][Scheduler] Split
UnsupportedSchedZfa
by other fp extensionsThis contribution was made on May 16 -
[IR] Add llvm.vector.[de]interleave{4,6,8}
This contribution was made on May 16
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[RISCV][Scheduler] Add scheduling definitions for 128-bit Zfa instructions
This contribution was made on May 15
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[RISCV] Use RISCVRegisterInfo::isRVVRegClass to replace IsScalableVector in storeRegToStackSlot/loadRegFromStackSlot. NFC
This contribution was made on May 15
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[NFC][TableGen][X86] Use StringSwitch to map from string -> enum
This contribution was made on May 15
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[RISCV] Add test for spilling and reloading a GPRPair for Zdinx+RV32. NFC
This contribution was made on May 15
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[RISCV] Add hasSideEffects = true to ReadFRM
This contribution was made on May 14
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[NFC][TableGen] Use StringRef in X86RecognizableInstr
This contribution was made on May 14
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[RISCV] Lower i64 load/stores to ld/sd with Zilsd.
This contribution was made on May 14
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[RISCV] Ignore interleaved accesses with non-default address spaces
This contribution was made on May 13
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[RISCV][MC] Add support for Q extension
This contribution was made on May 13
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[LLVM][TableGen] Code cleanup in FastISelEmitter.cpp
This contribution was made on May 13
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[RISC-V] Allow intrinsics to be used with any pointer type.
This contribution was made on May 13
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[RISCV][Scheduler] Add scheduler definitions for the Q extension
This contribution was made on May 13
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[RISCV] Add
zihintpause
LLVM/Clang intrinsicThis contribution was made on May 13 -
[TableGen][MacroFusion] Predicate if the first inst has the same register
This contribution was made on May 12
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[NFC][TableGen] Code cleanup in Record.h/cpp
This contribution was made on May 12
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[RISCV] Add scheduling model for SiFive P800 processors
This contribution was made on May 12
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[RISCV] Add Andes XAndesVPackFPH (Andes Vector Packed FP16) extension.
This contribution was made on May 12