Ariane SMP support #146
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Ariane SMP support #146
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- invalidate L1 caches with AXI-ACE snoop address channel - flush L1 of Ariane when L2 is flushed - caches: move PUTACK to RSP plane from FWD - hold invalidation in adapter if pending read request - serve forwards from L2 between LR/SC
-pass correct FPGA frequency to openSBI -enable SMP execution through bootloader only when SMP mode is defined
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Support for booting Linux SMP with up to 4 RISC-V Ariane processors:
-Added dcache-inval unit in Ariane processor to receive invalidations from ESP L2 over an ACE bus
-Patch Linux to mitigate RCU stall issue
-Switch from the riscv-pk to openSBI
-Updates to SystemC and SystemVerilog caches to support RISC-V multicore while maintaining backwards compatibility