fence.i test and caches

[algrobman]

Hi,
we see the test failure on CPU with Harvard architecture with D&I caches.
The test writes a new opcode with a store, executes fence.i and expects the new opcode to be executed.
However, the new opcode remains in the D-cache. To make it visible to I-Cache cbo.clean or cbo.flush is needed, which are not in the test code.
We see possible workaround as disable caching, but then we don't check that fence.i invalidates I-chache ...
On other hand, we want to run some other tests with caching ( for ex AMO tests only work on cacheable addresses).
How to select caching selectively per test without patching their sources? (under riscof?)

What's the solution to run fence.i successfully on such CPUs?

[allenjbaum]

The intent of fence.i is to make any prior data writes visible to the fetch. If the fetch unit isn’t seeing a prior write after a fence.i, that sounds like a bug in your fence.i implementation. The fence.i should be flushing dirty lines to the point of convergence- at least that’s my understanding. It’s expensive, but it should work. What does your fence.i do if not that?

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On Thursday, February 13, 2025, algrobman ***@***.***> wrote: Hi, we see the test failure on CPU with Harvard architecture with D&I caches. The test writes a new opcode with a store, executes fence.i and expects the new opcode to be executed. However, the new opcode remains in the D-cache. To make it visible to I-Cache cbo.clean or cbo.flush is needed, which are not in the test code. We see possible workaround as disable caching, but then we don't check that fence.i invalidates I-chache ... On other hand, we want to run some other tests with caching ( for ex AMO tests only work on cacheable addresses). How to select caching selectively per test without patching their sources? (under riscof?) What's the solution to run fence.i successfully on such CPUs? — Reply to this email directly, view it on GitHub <#610>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AHPXVJWHJ23L4L62MHBFAL32PQJZJAVCNFSM6AAAAABXBFQAZ6VHI2DSMVQWIX3LMV43ASLTON2WKOZSHA2DSOBYG4ZTCNQ> . You are receiving this because you are subscribed to this thread.Message ID: ***@***.***>

[algrobman]

fence.i does not effect D-side of CPU, but only I-side - instruction flow and invalidates I-cache. We had long discussions about this instruction spec and this was common agreement ...