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[CIR][Dialect][NFC] Add some helpers to LoadOp #1021

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merged 1,997 commits into from
Nov 5, 2024
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6949a3a
[CIR][CIRGen] Support more complex value casts (#786)
Lancern Aug 13, 2024
a0239aa
[CIR][Dialect] Add verification of address space to `get_global` (#787)
seven-mile Aug 13, 2024
0fb41a1
[CIR][CodeGen] Set address space for OpenCL globals (#788)
seven-mile Aug 14, 2024
1e9382e
[CIR] Fix wrong LLVMIR lowering of fp decrement (#789)
Lancern Aug 14, 2024
354e876
[CIR][CIRGen] Add new CIR visibility to represent Default, Hidden, Pr…
roro47 Aug 15, 2024
4eb034b
[CIR][CIRGen] Complex unary increment and decrement operator (#790)
Lancern Aug 15, 2024
34bc341
[CIR][CodeGen] Set address space for OpenCL static and local-qualifie…
seven-mile Aug 15, 2024
e487b83
[CIR][ABI][NFC] Follow-up to struct unpacking (#791)
sitio-couto Aug 15, 2024
63c6bdf
[CIR][CIRGen] Add CIRGen support for pointer-to-member-functions (#722)
Lancern Aug 20, 2024
970efe9
[CIR][CIRGen] Achieve union's bitfields additionally. (#742)
566hub Aug 20, 2024
2f82a2a
[CIR] Cleanup most recent warnings
bcardosolopes Aug 21, 2024
e6ac8e5
[CIR] More warning fixed by another fresh build
bcardosolopes Aug 21, 2024
253d1e3
[CIR] Add select operation (#796)
Lancern Aug 21, 2024
cb40fcc
[CIR][CIRGen] Inline variables processing (#794)
ivanmurashko Aug 22, 2024
8dc84ff
[CIR] Incorrect global view index and offset when neg index (#795)
HerrCai0907 Aug 22, 2024
2f86e11
[CIR][NFC] Replace ternary ops after lowering prepare to select ops (…
Lancern Aug 22, 2024
403f4dc
[CIR][CirGen][Bugfix] Fixes __sync_fetch_and_add for unsigned integer…
bruteforceboy Aug 23, 2024
d784759
[CIR][CIRGen] Support global initialization with new
bcardosolopes Aug 23, 2024
f13d2ec
[CIR][NFC] Fix sign-compare warning
bcardosolopes Aug 23, 2024
49ceda3
[CIR] Add missing testcase for previous commit
bcardosolopes Aug 23, 2024
307fd34
[CIR][CIRGen] Add minimal support for building invariant globals
bcardosolopes Aug 23, 2024
ddf7003
[CIR][Lowering] Add the concept of simple lowering and use it for una…
Lancern Aug 27, 2024
ec31a4a
[CIR][CIRGen] Exceptions: Use the surrounding scope (if available) fo…
bcardosolopes Aug 28, 2024
e9527a6
[CIR][NFC] Exceptions: introduce cleanup region to cir.try
bcardosolopes Aug 28, 2024
806b457
[CIR][CIRGen] Exceptions: handle cleanups and global initializers
bcardosolopes Aug 26, 2024
14dd633
[CIR][FlattenCFG] Exceptions: propagate cleanups to flat CIR
bcardosolopes Aug 28, 2024
c0c66d7
[CIR] Add new HLSLResource enum value coverage
lanza Aug 30, 2024
1529f0e
[CIR] Exceptions: propagate more cleanup info for LLVM lowering use
bcardosolopes Aug 29, 2024
8ef6fce
[CIR][CIRGen][NFC] Add more skeleton to make crashes fine grained on …
bcardosolopes Aug 29, 2024
672ade9
[CIR][NFC] Exceptions: Move a crash to an assert
bcardosolopes Aug 29, 2024
eefe053
[CIR][CIRGen] Handle paren list init and get dtors right
bcardosolopes Aug 29, 2024
91720d6
[CIR][CIRGen] Handle more cleanup situations and fix bug
bcardosolopes Aug 29, 2024
9682945
[CIR][NFC] Leftover from previous commit
bcardosolopes Aug 30, 2024
b6685a2
[CIR][NFC] Cleanup tests a bit to reflect tested platform
bcardosolopes Aug 30, 2024
5956abb
[CIR] Disable test temporatily
bcardosolopes Aug 30, 2024
f494178
[CIR] Another attempt to disable tests
bcardosolopes Aug 30, 2024
ef771a4
[CIR] Reland failing tests (#811)
bcardosolopes Aug 31, 2024
ecae00b
[CIR][CIRGen] Support pure and deleted virtual functions (#823)
smeenai Sep 5, 2024
cd0ca4c
[CIR][CIRGen][Lowering] Get alignment from frontend and pass it to LL…
ghehg Sep 9, 2024
99aef47
[CIR][CodeGen] Fix address space of result pointer type of array deca…
seven-mile Sep 9, 2024
410d638
[CIR][Transform] Add simplify transformation for select op (#816)
Lancern Sep 9, 2024
f32fe84
[CIR][NFC] Extend simple lowering to unary fp2int ops and binary fp2f…
Lancern Sep 9, 2024
7f528a8
[CIR][CIRGen] Add initial CIRGen support for local temporary material…
Lancern Sep 9, 2024
d6c0ec3
[CIR][CIRGen] Implement delegating constructors (#821)
smeenai Sep 9, 2024
8dc4fb4
[CIR][Dialect] Verify bitcast does not contain address space conversi…
seven-mile Sep 10, 2024
f8d1d9c
[CIR][Dialect] Remove 22 prefix and suffix from type aliases (#826)
smeenai Sep 10, 2024
a4fa59b
[CIR][Lowering] Fix BrCond Lowering (#819)
bruteforceboy Sep 10, 2024
dd9e883
[CIR] Add some extra dumping to help with intermitent bug
bcardosolopes Sep 10, 2024
ed1f9fd
[CIR][driver] Forward -fno-clangir-direct-lowering option to cc1 (#822)
keryell Sep 10, 2024
f2349c4
[CIR][CIRGen] Exceptions: handle synthetic cir.try within functions
bcardosolopes Sep 11, 2024
c1e80e1
[CIR][Transform] Add ternary simplification (#809)
Lancern Sep 11, 2024
127fb54
[CIR][CIRGen] Support a defined pure virtual destructor (#825)
smeenai Sep 11, 2024
a0ea3fb
[CIR][Dialect] Add calling convention attribute to cir.call op (#828)
seven-mile Sep 11, 2024
548a503
[CIR][CIRGen] Exception: get scope order right for try/catch with cle…
bcardosolopes Sep 11, 2024
9f26e4e
[CIR][LowerToLLVM] Exceptions: llvm.zero needed for landingpad should…
bcardosolopes Sep 11, 2024
972ca21
[CIR][CIRGen] Exceptions: support nested scope cleanup
bcardosolopes Sep 11, 2024
5214678
[CIR][CodeGen][NFCI] Unify attribute list handling of func / call by …
seven-mile Sep 12, 2024
dfc1677
[CIR][CodeGen] Refactor `setExtraAttributesForFunc` to better align w…
seven-mile Sep 12, 2024
e6fffd6
[CIR][Asm] Fix parsing of extra(...) attributes in cir.call (#835)
keryell Sep 13, 2024
6d07605
[CIR][CodeGen][LowerToLLVM] Set calling convention for call ops (#836)
seven-mile Sep 13, 2024
bc457d4
[CIR][Lowering] Fix static array lowering (#838)
bruteforceboy Sep 13, 2024
967ae69
[CIR][CIRGen][Lowering] Add support for attribute annotate (#804)
ghehg Sep 13, 2024
bae79ba
[CIR][CIRGen][NFC] Exceptions: add cleanups to cir.call
bcardosolopes Sep 13, 2024
9e13781
[CIR][CIRGen][NFC] Exceptions: refactor invoke checks to better align…
bcardosolopes Sep 13, 2024
8f820ed
[CIR][CIRGen][NFC] Exceptions: sink invoke logic closer to call emission
bcardosolopes Sep 13, 2024
06f96ca
[CIR][CIRGen][NFC] Exceptions: Move the logic to create surrounding t…
bcardosolopes Sep 13, 2024
665798d
[CIR][CIRGen][NFCI] Exceptions: change getEHDispatchBlock to create b…
bcardosolopes Sep 14, 2024
143e2a5
[CIR][NFC] Fix mismatch of argument type in IR tests (#837)
seven-mile Sep 14, 2024
bff487f
[CIR][Dialect] Add `convergent` attribute to functions for SIMT langu…
seven-mile Sep 16, 2024
7b4e3c7
[CIR][FlattenCFG] Fix use after free when flattening terminator (#843)
smeenai Sep 16, 2024
c01b543
[CIR][CodeGen][BugFix] Fixes structures name collisions (#844)
gitoleg Sep 16, 2024
229ebc1
[CIR][Bugfix] renames minor/major parameters of the OpenCLVersionAttr…
gitoleg Sep 16, 2024
3a95d58
[CIR][CodeGen] Support FullExpression storage duration cleanup (#846)
lanza Sep 16, 2024
12f12bf
[CIR][CIRGen] Properly link multiple level of cleanups
bcardosolopes Sep 14, 2024
25bf750
[CIR][CodeGen] Fix packed structures (#839)
bruteforceboy Sep 17, 2024
6eee944
[CIR][CIRGen] add CIRGen support for assume builtins (#841)
Lancern Sep 17, 2024
a64c961
[CIR][NFC] Change default LLVM output file extension (#849)
Lancern Sep 17, 2024
08b2e1e
[CIR][Asm] Parse extra attributes after calling convention (#847)
keryell Sep 17, 2024
efee5c0
[CIR][CIRGen][Lowering] Lower AArch64::BI__builtin_arm_ldrex to llvm …
ghehg Sep 17, 2024
07315cb
[CIR][FlattenCFG][NFC] Exceptions: refactor landing pad code and catches
bcardosolopes Sep 17, 2024
2950f36
[CIR][CIRGen][NFC] Exceptions: refactor more infra for handling multi…
bcardosolopes Sep 18, 2024
4038dff
[CIR][CIRGen][NFCI] Exceptions: generalize landing pad insertion
bcardosolopes Sep 18, 2024
39a2c08
[CIR][FlattenCFG][NFCI] Exceptions: more generalization for dispatch …
bcardosolopes Sep 18, 2024
86d5ca4
[CIR][FlattenCFG][NFCI] Exceptions: generalize catch dispatch emission
bcardosolopes Sep 18, 2024
3729f9f
[CIR][NFC] Move things around in try-catch-dtors.cpp
bcardosolopes Sep 18, 2024
e4eecd2
[CIR][FlattenCFG] Exceptions: enable many calls / many landing pads s…
bcardosolopes Sep 18, 2024
ae75127
[CIR][LowerToLLVM][NFC] Exceptions: use getOrCreateLLVMFuncOp to crea…
bcardosolopes Sep 18, 2024
74066a1
[CIR][Lowering] Erase op through rewriter instead of directly (#853)
smeenai Sep 18, 2024
e95f39b
[CIR] Exceptions: check LLVM output for more complex dtor order
bcardosolopes Sep 18, 2024
b981867
[CIR][ABI] Fix use after free from erasing while iterating (#854)
smeenai Sep 18, 2024
22bd691
Recommit [CIR][Pipeline] Support -fclangir-analysis-only (#832)
ChuanqiXu9 Sep 18, 2024
9980dbb
[CIR][Lowering] Fix lowering for multi dimensional array (#851)
bruteforceboy Sep 18, 2024
d88868e
[CIR][CodeGen] Support global temporaries
lanza Sep 18, 2024
92f3e1e
[CIR][CodeGen][NFC] Move GetUndefRValue to the right file
lanza Sep 18, 2024
789fb87
[CIR][CIRGen] Exceptions: lexical scope issue with global initializers
bcardosolopes Sep 18, 2024
9ec43b0
[CIR][CIRGen][Builtin][Neon] Lower __builtin_neon_vrndns_f32 (#858)
ghehg Sep 19, 2024
bdfa942
[CIR][CodeGen][NFC] Add TBAAAccessInfo stubbed out and many usages of…
lanza Sep 19, 2024
191ea78
[CIR][CodeGen] Stub out an empty CIRGenDebugInfo type
lanza Sep 19, 2024
3bf78fe
[CIR][CIRGen] Initialize more CGF member variables to nullptr (#863)
smeenai Sep 19, 2024
5c3e67b
[CIR][CIRGen] Implement Nullpointer arithmatic extension (#861)
ChuanqiXu9 Sep 19, 2024
48cab65
[CIR][Codegen] supports aarch64_be (#864)
gitoleg Sep 19, 2024
7cf7961
[CIR] Split cir-simplify into two passes (#868)
Lancern Sep 19, 2024
689a762
[CIR][CodeGen] Implement union cast (#867)
bruteforceboy Sep 19, 2024
b924002
[CIR][CIRGen] Exceptions: unlock nested try/catch support
bcardosolopes Sep 20, 2024
16991e3
[CIR][CodeGen] Fix array initialization in CIRGenExprAgg (#852)
bruteforceboy Sep 20, 2024
ab37943
[CIR][CIRGen] Correct isSized predicate for vector type (#869)
ghehg Sep 20, 2024
2e1febe
[CIR][CIRGen][Builtin][Neon] Lower builtin_neon_vrnda_v and builtin_n…
ghehg Sep 20, 2024
8412ead
[CIR][CIRGen] Handle VisitCXXRewrittenBinaryOperator for scalars
bcardosolopes Sep 20, 2024
5a290b6
[CIR][CIRGen][NFC] Cleanups: add skeleton for DominatingValue<RValue>…
bcardosolopes Sep 20, 2024
6ca5f24
[CIR][Infra] Run check-clang-cir against any branch based PR (#873)
lanza Sep 20, 2024
c99f210
[CIR][CIRGen][NFC] Cleanups: add more skeleton to pushFullExprCleanup
bcardosolopes Sep 21, 2024
73aebf4
[CIR][CodeGen][BugFix] don't place alloca before the label (#875)
gitoleg Sep 23, 2024
5334d5a
[CIR][CIRGen] Allow constant evaluation of int annotation (#874)
keryell Sep 23, 2024
831c229
[CIR][CIRGen] Cleanups: handle conditional cleanups
bcardosolopes Sep 21, 2024
ba03052
[CIR][CIRGen][NFC] Cleanups: Prepare for conditional cleanup
bcardosolopes Sep 23, 2024
2b97f7a
[CIR][CIRGen][NFC] Cleanups: more boilerplate work for conditional on…
bcardosolopes Sep 23, 2024
933f775
[CIR][CodeGen] Handling multiple stmt followed after a switch case (#…
ChuanqiXu9 Sep 24, 2024
8f96cfa
[CIR][CIRGen] Generate CIR for empty compound literal (#880)
ghehg Sep 24, 2024
669eaa9
[CIR][CIRGen] Generate CIR for vset_lane and vsetq_lane intrinsics (#…
ghehg Sep 24, 2024
348f18f
[CIR][CI] Remove libcxx tests
lanza Sep 25, 2024
5649a45
[CIR][Dialect][CodeGen] Add a unit attribute for OpenCL kernels (#877)
seven-mile Sep 25, 2024
d0fad9f
[CIR][CodeGen] Handle the case of 'case' after label statement after …
ChuanqiXu9 Sep 25, 2024
98586db
[CIR][CIRGen] Generate CIR for neon_vget and neon_vdup lane intrinsic…
ghehg Sep 25, 2024
64ae660
[CIR][CIRGen] Allow maybeSetTrivialComdat for GlobalOp (#885)
ghehg Sep 25, 2024
6fd7507
[CIR][CIRGen][Builtin][Neon] Lower neon vqadd_v (#890)
ghehg Sep 27, 2024
0a33748
[CIR][CIRGen][NFC] Split cir.scope creation on buildReturnStmt
bcardosolopes Sep 24, 2024
7e3d6e6
[CIR][NFC] Add helpers for cir.try and do some refactoring
bcardosolopes Sep 24, 2024
166af47
[CIR][CIRGen][Builtin] Allow CIRGen for builtin calls with math error…
ghehg Sep 27, 2024
ce7ccce
[CIR][CIRGen] Support __builtin_huge_val for float type (#889)
ghehg Sep 27, 2024
737e91b
[CIR][NFC] Rename test
bcardosolopes Sep 27, 2024
80814d6
[CIR][ABI] Apply CC lowering pass by default (#842)
sitio-couto Sep 28, 2024
d246854
[CIR][CIRGen][Builtin][Neon] Lower vqrshrun_n and add getAArch64SIMDI…
ghehg Sep 30, 2024
881c18a
[CIR][NFC] Silence unused warning
bcardosolopes Sep 28, 2024
41891e8
Revert "[CIR][ABI] Apply CC lowering pass by default (#842)"
bcardosolopes Sep 30, 2024
b59a2e7
[CIR][CIRGen] Add time trace to several CIRGen pieces (#898)
ChuanqiXu9 Sep 30, 2024
14970ad
[CIR][Dialect] Support OpenCL work group uniformity attribute (#896)
seven-mile Sep 30, 2024
ae40465
[CIR][CodeGen][NFC] Rename the confusing `buildGlobal` overload (#897)
seven-mile Sep 30, 2024
ce0aa5c
[CIR][CIRGen][Builtin][Neon] Lower neon vld1_lane and vld1q_lane (#901)
ghehg Sep 30, 2024
3e13daf
[CIR][CodeGen][NFC] Break the missing feature flag for OpenCL into sm…
seven-mile Oct 1, 2024
2322e2a
[CIR][CodeGen] Add `nothrow` for functions in OpenCL languages (#903)
seven-mile Oct 1, 2024
31cc156
[CIR][CodeGen] Set constant properly for global variables (#904)
seven-mile Oct 1, 2024
f9a83c8
[CIR][Test][NFC] Organize CIR CodeGen AArch64 neon tests (#910)
ghehg Oct 2, 2024
3966c67
[CIR][Lowering] Fix Global Attr Lowering (#906)
bruteforceboy Oct 2, 2024
088accd
[CIR][CIRGen][Builtin] Implement builtin __sync_fetch_and_sub (#932)
ghehg Oct 2, 2024
ef57d5f
[CIR][CIRGen] Cleanup: enable conditional cleanup with exceptions
bcardosolopes Sep 24, 2024
6885dd0
[CIR][CIRGen][Builtin][Neon] Lower BI__builtin_neon_vmovn_v (#909)
ghehg Oct 4, 2024
c9e5a9c
[CIR][CIRGen][Builtin][Neon] Lower neon vst1q_lane and vst1_lane (#935)
ghehg Oct 4, 2024
74d032f
[CIR] Derived-to-base conversions (#937)
dkolsen-pgi Oct 5, 2024
2ec2277
[CIR][NFC] Updates against -Wswitch after rebase
bcardosolopes Oct 5, 2024
366b4a3
[CIR][CIRGen] Exceptions: fix agg store for temporaries
bcardosolopes Oct 5, 2024
9cc1faf
[CIR][CIRGen] Lower cir.throw in absence of dtors
bcardosolopes Oct 7, 2024
eaacaf1
[CIR][NFC] Update wrong comments from previous commit
bcardosolopes Oct 7, 2024
cea946a
[CIR][CIRGen] Exceptions: support free'ing allocated exception resources
bcardosolopes Oct 7, 2024
4d2c56f
[Lowering][DirectToLLVM] Fix calling variadic functions (#945)
smeenai Oct 8, 2024
99a4590
[CIR] [CodeGen] Remove NYI in buildPointerWithAlignment (#949)
ChuanqiXu9 Oct 8, 2024
45fe4fd
[CIR][Lowering] Introduce HoistAllocasPass (#887)
ChuanqiXu9 Oct 9, 2024
f9ef59a
[CIR][CodeGen] Enable -fno-PIE (#940)
bruteforceboy Oct 9, 2024
04087b5
[CIR][CIRGen] Add support for __fp16 type (#950)
Lancern Oct 9, 2024
0bc6286
[CIR][CIRGen][Builtin] Support unsigned type for _sync_(bool/val)_com…
ghehg Oct 9, 2024
42f05b5
[CIR][CIRGen][NFC] Improve buildAutoVarAlloca skeleton and add hooks …
bcardosolopes Oct 9, 2024
19c9099
[CIR][CIRGen] Support annotations on local var decl
bcardosolopes Oct 9, 2024
8f61a4c
[CIR][LowerToLLVM][NFC] Move annotation lowering around
bcardosolopes Oct 9, 2024
7dd34cd
[CIR][NFC] Fix post-rebase warning
bcardosolopes Oct 9, 2024
d1b1222
[CIR][LowerToLLVM] Add support for local var annotations
bcardosolopes Oct 10, 2024
6d49e8b
Reapply and patch "[CIR][ABI] Apply CC lowering pass by default (#842…
sitio-couto Oct 11, 2024
a34d6e6
[CIR][CodeGen] kr-style for function arguments (#938)
gitoleg Oct 11, 2024
b2ad574
[CIR][CIRGen] Add const attribute to alloca operations (#892)
Lancern Oct 11, 2024
a6fd0d7
[CIR][Lowering] VecCreateOp and VecSplatOp lowering choose LLVM:Poiso…
ghehg Oct 11, 2024
6976c41
[CIR][NFC][Testing] Fix test failure (#963)
ghehg Oct 11, 2024
43f5b48
fixup! [CIR][LowerToLLVM] Fix crash in PtrStrideOp lowering
smeenai Oct 11, 2024
d8d2464
[CIR][CodeGen] Support static references to temporaries
lanza Sep 19, 2024
077ebe9
[CIR][CIRGen] Support CodeGen for vbase constructors
Laity000 May 21, 2024
c693c34
[CIR][CIRGen][Builtin][Neon] Lower neon_vtrn and neon_vtrnq (#942)
ghehg Oct 11, 2024
ffdbdc3
[CIR][CIRGen][Builtin][Neon] Lower neon_vext_v and neon_vextq_v (#951)
ghehg Oct 11, 2024
666dbcf
[CIR][Lowering] Handling Lowering of multiple dimension array correct…
ChuanqiXu9 Oct 14, 2024
90a9be6
[CIR][CIRGen][Builtin][Neon] Lower vld1_dup and vld1q_dup (#936)
ghehg Oct 14, 2024
244734d
[CIR][CIRGen][Builtin][Neon] Lower neon_vpadd_v and neon_vpaddq_v int…
ghehg Oct 14, 2024
4a8a588
[CIR] [Lowering] Fix handling of multiple array for ZeroAttr (#970)
ChuanqiXu9 Oct 14, 2024
a43cad3
[CIR][Driver] Fix -fclangir-call-conv-lowering behavior
bcardosolopes Oct 14, 2024
2b5947a
[CIR] Add more user facing messages for -fno-clangir-call-conv-lowering
bcardosolopes Oct 15, 2024
5f4a2ae
[CIR] Make the asserts to display suggestion for -fno-clangir-call-co…
bcardosolopes Oct 15, 2024
b4b6fbe
[CIR][NFC] Massively rename workarounds for callconv lowering
bcardosolopes Oct 15, 2024
3ef5e65
[CIR][CIRGen] Implement CIRGenModule::shouldEmitFunction (#984)
smeenai Oct 16, 2024
0c6d78b
[CIR][CIRGen] Port 1d0bd8e51be2627f79bede54735c38b917ea04ee (#983)
smeenai Oct 16, 2024
679b8ea
[CIR][LowerToLLVM] Lower cir.vtt.address_point
bcardosolopes Oct 16, 2024
7f1a689
[CIR][NFC] Rename function in a test
bcardosolopes Oct 16, 2024
4f3b99e
[CIR][CIRGen] Get more vtable and dtor working
bcardosolopes Oct 16, 2024
ffd2935
[CIR][CIRGen][NFC] Consolidate RUN lines for builtin tests (#968)
ghehg Oct 16, 2024
478deb6
[CIR] [Lowering] care trailing zero for lowering constant array (#976)
ChuanqiXu9 Oct 16, 2024
31fd4b7
[CIR] Add support for __int128 type (#980)
Lancern Oct 16, 2024
e865152
[CIR][CIRGen][Builtin][Neon] Lower neon_vrshrn_n to llvm intrinsic ca…
ghehg Oct 16, 2024
35ec8a6
[CIR][CIRGen][Builtin][Neon] Lower vqdmulhq_lane, vqdmulh_lane, vqrdm…
ghehg Oct 16, 2024
0d894e1
[CIR][CIRGen][Builtin][Type] Support for IEEE Quad (long double) adde…
mvvsmk Oct 16, 2024
f0c1120
[CIR][NFC] Fix some consistency issues with missing features
bcardosolopes Oct 16, 2024
ce33590
[CIR] Disable `-fclangir-call-conv-lowering` from default in the LLVM…
bcardosolopes Oct 16, 2024
ae4a7df
[CIR][CIRGen][Builtin] Implement builtin addressof (#987)
ghehg Oct 16, 2024
6e7779a
[CIR][NFC] Improve documentation about goto's
bcardosolopes Oct 16, 2024
da816c5
[CIR][NFC] Move code around to match OG
bcardosolopes Oct 16, 2024
2c3c8ef
[CIR][CIRGen][NFC] Add more skeleton for handling inheritance ctors
bcardosolopes Oct 18, 2024
e3ad862
[CIR][CIRGen] Ensure default visibility for local linkage functions (…
smeenai Oct 18, 2024
bb3b839
[CIR][CIRGen][Builtin][Neon] Lower neon_vshl_n_v and neon_vshlq_n_v (…
ghehg Oct 18, 2024
b24f6f6
[CIR][CIRGen] Use Clang Codegen's skeleton in CIRGenFunction::buildBu…
ghehg Oct 18, 2024
5b81555
[CIR][CIRGen][Builtin][Neon] Lower neon_vqaddq_v, neon_vqsubq and neo…
ghehg Oct 18, 2024
e198f7e
[CIR][CIRGen][Builtin][Neon] Lower neon_vmovl_v (#989)
ghehg Oct 18, 2024
92c7d8f
[CIR][CIRGen] Support initial cases of inheritance ctor/dtor
bcardosolopes Oct 18, 2024
cb0cb34
[CIR][CIRGen] Null init some inheritance components
bcardosolopes Oct 18, 2024
c1731b1
[CIR][CIRGen][NFC] More skeleton for building constants
bcardosolopes Oct 19, 2024
e744086
[CIR][CIRGen] Add missing testcase for null base class
bcardosolopes Oct 19, 2024
f50ca24
[CIR] [CodeGen] Introduce IsFPClassOp to support builtin_isfpclass (#…
ChuanqiXu9 Oct 21, 2024
e2631fb
[CIR][NFC] Move callconv tests around
bcardosolopes Oct 21, 2024
a4cda9b
[CIR][Asm] Implement parser for cir.func annotations (#981)
keryell Oct 21, 2024
663c13a
[CIR][CIRGen][Builtin][Neon] Lower neon_vabd_v and neon_vabdq_v (#996)
ghehg Oct 21, 2024
57e60f6
[CIR][CIRGen][Builtin][Neon] Lower neon_vmull_v (#998)
ghehg Oct 21, 2024
766f0b8
[CIR][CIRGen][Builtin][Neon] Lower neon_vrhadd_v and neon_vrhaddq_v (…
ghehg Oct 21, 2024
cab2b44
[CIR][CIRGen][Builtin][Neon] Lower neon_vmin_v and neon_vminq_v (#1000)
ghehg Oct 21, 2024
33857b4
[CIR][Transforms] Fix CallConv Function Lowering (#979)
bruteforceboy Oct 26, 2024
2170ce7
[CIR][CIRGen][Lowering] Use same set of annotation-related global var…
ghehg Oct 26, 2024
e7982b8
[CIR][CodeGen][NFC] Cleanup CIRGenFunction::StartFunction to match OG…
lanza Oct 26, 2024
74d8fe9
[ClangIR][Lowering] Handle lowered array index (#1008)
ChuanqiXu9 Oct 26, 2024
d7de21f
[CIR][CIRGen] Removed extra space in "cir.shift( right)" (#997) (#1009)
MarcoCalabretta Oct 28, 2024
c76c138
[CIR][CIRGen][Builtin][Neon] Lower neon_vshll_n (#1010)
ghehg Oct 28, 2024
8f54bcd
[ClangIR][CIRGen] Introduce CaseOp and refactor SwitchOp (#1006)
ChuanqiXu9 Oct 29, 2024
e58602d
[𝘀𝗽𝗿] initial version
lanza Oct 29, 2024
5873d88
[CIR][ABI][AArch64][Lowering] Initial support for return of struct ty…
gitoleg Oct 29, 2024
6a79d2b
[CIR][Lowering] Supports varargs in the CallingConvention pass (#1005)
gitoleg Oct 29, 2024
9c2b99e
add todo
lanza Oct 30, 2024
60e4512
rebase
lanza Oct 30, 2024
6a925fd
[CIR][CodeGen][NFC] Add some missing guards for unreachable
lanza Oct 30, 2024
91b172f
[CIR][CodeGen] Store the old CIRGenFunction when popping to a new one
lanza Oct 30, 2024
d50e440
[CIR][CodeGen][NFC] Implement a missing function
lanza Oct 30, 2024
6288572
[CIR][ABI][Lowering] Supports function pointers in the calling conven…
gitoleg Oct 30, 2024
d6db31d
[CIR][CIRGen][Builtin][Neon] Lower neon_vqmovun_v (#1012)
ghehg Oct 30, 2024
29e5998
[CIR][CIRGen] Enable comdat for static variables (#1015)
ghehg Oct 30, 2024
b4d4611
[CIR][CIRGen] Fix "definition with same mangled name" error (#1016)
smeenai Oct 30, 2024
c5124be
[CIR][CIRGen][Builtin][Neon] Lower neon_vrshr_n and vrshrq_n to llvm …
ghehg Oct 30, 2024
fccd337
[CIR][Dialect][NFC] Fix double whitespaces in `cir.func` assembly (#1…
seven-mile Oct 30, 2024
5404e9c
[CIR][CIRGen] Add support for abs (#1011)
PikachuHyA Oct 30, 2024
9ca00c4
[CIR][Lowering] Transform cir.store of const arrays into cir.copy
bcardosolopes Oct 29, 2024
f9c5477
[CIR][CIRGen] Fix typo in test check
smeenai Oct 30, 2024
b53784a
[CIR][CIRGen] Fix swapped parameters in test
smeenai Oct 31, 2024
7e7be0e
[CIR][CIRGen][Builtin][Neon] Lower neon_vtst_v and neon_vtstq_v (#1013)
ghehg Oct 31, 2024
2813bac
[CIR][CIRGen] Add support for memmove (#1019)
PikachuHyA Oct 31, 2024
c8f189b
[CIR][ABI][AArch64] support for return struct types greater than 128 …
gitoleg Oct 31, 2024
ce2469e
[CIR][ABI][Lowering] Supports call by function pointer in the calling…
gitoleg Oct 31, 2024
2eaa500
[CIR][CIRGen][Builtin] Support BI__builtin_operator_new and BI__built…
ghehg Oct 31, 2024
734d344
[CIR][ABI][Lowering] Add CCLower support for int128 on x86_64 (#1036)
Lancern Oct 31, 2024
dae8726
[CIR][CIRGen][Builtin][Neon] Lower neon_vqshlu_n and neon_vqshluq_n (…
ghehg Oct 31, 2024
3d16a0f
[CIR][CIRGen] Support more member init variations
bcardosolopes Oct 31, 2024
37c7e20
storeop and usages
lanza Nov 1, 2024
67264e8
rebase
lanza Nov 5, 2024
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[CIR][ABI][NFC] Follow-up to struct unpacking (#791)
This patch fixes a bunch of pending review comments in #784:

 - Remove data layout attribute from address space testing
 - Remove incoherent comment
 - Rename abi_or_pref to abiOrPref
 - Make comments impersonal
 - Implement feature guard for ARM's CMSE secure call feature
 - Track volatile return times feature in CC lowering
 - Track missing features in the Itanium record builder
 - Remove incoherent fix me
 - Clarify comment regarding CIR record layout getter
 - Track missing cache for record layout getter
 - Remove unnecessary todo's
sitio-couto authored and lanza committed Oct 12, 2024
commit e487b83f164742e084bdd0da3687f48c4d4733dc
4 changes: 1 addition & 3 deletions clang/include/clang/CIR/Dialect/IR/CIRDataLayout.h
Original file line number Diff line number Diff line change
@@ -55,7 +55,7 @@ class CIRDataLayout {
const StructLayout *getStructLayout(mlir::cir::StructType Ty) const;

/// Internal helper method that returns requested alignment for type.
llvm::Align getAlignment(mlir::Type Ty, bool abi_or_pref) const;
llvm::Align getAlignment(mlir::Type Ty, bool abiOrPref) const;

llvm::Align getABITypeAlign(mlir::Type ty) const {
return getAlignment(ty, true);
@@ -93,8 +93,6 @@ class CIRDataLayout {
return layout.getTypeSizeInBits(Ty);
}

// The implementation of this method is provided inline as it is particularly
// well suited to constant folding when called on a specific Type subclass.
llvm::TypeSize getTypeSizeInBits(mlir::Type Ty) const;

mlir::Type getIntPtrType(mlir::Type Ty) const {
7 changes: 7 additions & 0 deletions clang/include/clang/CIR/MissingFeatures.h
Original file line number Diff line number Diff line change
@@ -135,6 +135,7 @@ struct MissingFeatures {
static bool syncScopeID() { return false; }

// Misc
static bool cacheRecordLayouts() { return false; }
static bool capturedByInit() { return false; }
static bool tryEmitAsConstant() { return false; }
static bool incrementProfileCounter() { return false; }
@@ -282,6 +283,9 @@ struct MissingFeatures {
// up argument registers), but we do not yet track such cases.
static bool chainCall() { return false; }

// ARM-specific feature that can be specified as a function attribute in C.
static bool cmseNonSecureCallAttr() { return false; }

// ABI-lowering has special handling for regcall calling convention (tries to
// pass every argument in regs). We don't support it just yet.
static bool regCall() { return false; }
@@ -326,6 +330,9 @@ struct MissingFeatures {
// CIR modules parsed from text form may not carry the triple or data layout
// specs. We should make it always present.
static bool makeTripleAlwaysPresent() { return false; }

// This Itanium bit is currently being skipped in cir.
static bool itaniumRecordLayoutBuilderFinishLayout() { return false; }
};

} // namespace cir
12 changes: 6 additions & 6 deletions clang/lib/CIR/Dialect/IR/CIRDataLayout.cpp
Original file line number Diff line number Diff line change
@@ -157,25 +157,25 @@ CIRDataLayout::getStructLayout(mlir::cir::StructType Ty) const {
}

/*!
\param abi_or_pref Flag that determines which alignment is returned. true
\param abiOrPref Flag that determines which alignment is returned. true
returns the ABI alignment, false returns the preferred alignment.
\param Ty The underlying type for which alignment is determined.

Get the ABI (\a abi_or_pref == true) or preferred alignment (\a abi_or_pref
Get the ABI (\a abiOrPref == true) or preferred alignment (\a abiOrPref
== false) for the requested type \a Ty.
*/
llvm::Align CIRDataLayout::getAlignment(mlir::Type Ty, bool abi_or_pref) const {
llvm::Align CIRDataLayout::getAlignment(mlir::Type Ty, bool abiOrPref) const {

if (llvm::isa<mlir::cir::StructType>(Ty)) {
// Packed structure types always have an ABI alignment of one.
if (::cir::MissingFeatures::recordDeclIsPacked() && abi_or_pref)
if (::cir::MissingFeatures::recordDeclIsPacked() && abiOrPref)
llvm_unreachable("NYI");

// Get the layout annotation... which is lazily created on demand.
const StructLayout *Layout =
getStructLayout(llvm::cast<mlir::cir::StructType>(Ty));
const llvm::Align Align =
abi_or_pref ? StructAlignment.ABIAlign : StructAlignment.PrefAlign;
abiOrPref ? StructAlignment.ABIAlign : StructAlignment.PrefAlign;
return std::max(Align, Layout->getAlignment());
}

@@ -184,7 +184,7 @@ llvm::Align CIRDataLayout::getAlignment(mlir::Type Ty, bool abi_or_pref) const {
assert(!::cir::MissingFeatures::addressSpace());

// Fetch type alignment from MLIR's data layout.
unsigned align = abi_or_pref ? layout.getTypeABIAlignment(Ty)
unsigned align = abiOrPref ? layout.getTypeABIAlignment(Ty)
: layout.getTypePreferredAlignment(Ty);
return llvm::Align(align);
}
Original file line number Diff line number Diff line change
@@ -61,8 +61,8 @@ clang::TypeInfo CIRLowerContext::getTypeInfoImpl(const Type T) const {
// FIXME(cir): Here we fetch the width and alignment of a type considering the
// current target. We can likely improve this using MLIR's data layout, or
// some other interface, to abstract this away (e.g. type.getWidth() &
// type.getAlign()). I'm not sure if data layoot suffices because this would
// involve some other types such as vectors and complex numbers.
// type.getAlign()). Verify if data layout suffices because this would involve
// some other types such as vectors and complex numbers.
// FIXME(cir): In the original codegen, this receives an AST type, meaning it
// differs chars from integers, something that is not possible with the
// current level of CIR.
Original file line number Diff line number Diff line change
@@ -12,6 +12,7 @@
//===----------------------------------------------------------------------===//

#include "CIRRecordLayout.h"
#include "clang/CIR/MissingFeatures.h"

namespace mlir {
namespace cir {
@@ -45,10 +46,8 @@ CIRRecordLayout::CIRRecordLayout(
CXXInfo->NonVirtualAlignment = nonvirtualalignment;
CXXInfo->PreferredNVAlignment = preferrednvalignment;
CXXInfo->SizeOfLargestEmptySubobject = SizeOfLargestEmptySubobject;
// FIXME(cir): I'm assuming that since we are not dealing with inherited
// classes yet, removing the following lines will be ok.
// CXXInfo->BaseOffsets = BaseOffsets;
// CXXInfo->VBaseOffsets = VBaseOffsets;
// FIXME(cir): Initialize base classes offsets.
assert(!::cir::MissingFeatures::getCXXRecordBases());
CXXInfo->HasOwnVFPtr = hasOwnVFPtr;
CXXInfo->VBPtrOffset = vbptroffset;
CXXInfo->HasExtendableVFPtr = hasExtendableVFPtr;
8 changes: 4 additions & 4 deletions clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerCall.cpp
Original file line number Diff line number Diff line change
@@ -42,8 +42,8 @@ arrangeFreeFunctionLikeCall(LowerTypes &LT, LowerModule &LM,
}

// TODO(cir): There's some CC stuff related to no-proto functions here, but
// I'm skipping it since it requires CodeGen info. Maybe we can embbed this
// information in the FuncOp during CIRGen.
// its skipped here since it requires CodeGen info. Maybe this information
// could be embbed in the FuncOp during CIRGen.

assert(!::cir::MissingFeatures::chainCall() && !chainCall && "NYI");
FnInfoOpts opts = chainCall ? FnInfoOpts::IsChainCall : FnInfoOpts::None;
@@ -120,8 +120,8 @@ void LowerModule::constructAttributeList(StringRef Name,
// }

// NOTE(cir): The original code adds default and no-builtin attributes here as
// well. AFAIK, these are ABI/Target-agnostic, so it would be better handled
// in CIRGen. Regardless, I'm leaving this comment here as a heads up.
// well. These are ABI/Target-agnostic, so it would be better handled in
// CIRGen.

// Override some default IR attributes based on declaration-specific
// information.
18 changes: 6 additions & 12 deletions clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerFunction.cpp
Original file line number Diff line number Diff line change
@@ -434,8 +434,7 @@ LogicalResult LowerFunction::buildFunctionEpilog(const LowerFunctionInfo &FI) {

// If there is a dominating store to ReturnValue, we can elide
// the load, zap the store, and usually zap the alloca.
// NOTE(cir): This seems like a premature optimization case, so I'm
// skipping it.
// NOTE(cir): This seems like a premature optimization case. Skipping it.
if (::cir::MissingFeatures::returnValueDominatingStoreOptmiization()) {
llvm_unreachable("NYI");
}
@@ -453,12 +452,6 @@ LogicalResult LowerFunction::buildFunctionEpilog(const LowerFunctionInfo &FI) {
mlir::PatternRewriter::InsertionGuard guard(rewriter);
NewFn->walk([&](ReturnOp returnOp) {
rewriter.setInsertionPoint(returnOp);

// TODO(cir): I'm not sure if we need this offset here or in CIRGen.
// Perhaps both? For now I'm just ignoring it.
// Value V = emitAddressAtOffset(*this, getResultAlloca(returnOp),
// RetAI);

RV = castReturnValue(returnOp->getOperand(0), RetAI.getCoerceToType(),
*this);
rewriter.replaceOpWithNewOp<ReturnOp>(returnOp, RV);
@@ -655,7 +648,7 @@ Value LowerFunction::rewriteCallOp(const LowerFunctionInfo &CallInfo,

FuncType IRFuncTy = LM.getTypes().getFunctionType(CallInfo);

// NOTE(cir): Some target/ABI related checks happen here. I'm skipping them
// NOTE(cir): Some target/ABI related checks happen here. They are skipped
// under the assumption that they are handled in CIRGen.

// 1. Set up the arguments.
@@ -737,7 +730,7 @@ Value LowerFunction::rewriteCallOp(const LowerFunctionInfo &CallInfo,
if (!isa<StructType>(I->getType())) {
llvm_unreachable("NYI");
} else {
// NOTE(cir): I'm leaving L/RValue stuff for CIRGen to handle.
// NOTE(cir): L/RValue stuff are left for CIRGen to handle.
Src = *I;
}

@@ -756,6 +749,7 @@ Value LowerFunction::rewriteCallOp(const LowerFunctionInfo &CallInfo,
Value Load = createCoercedValue(Src, ArgInfo.getCoerceToType(), *this);

// FIXME(cir): We should probably handle CMSE non-secure calls here
assert(!::cir::MissingFeatures::cmseNonSecureCallAttr());

// since they are a ARM-specific feature.
if (::cir::MissingFeatures::undef())
@@ -856,22 +850,22 @@ Value LowerFunction::rewriteCallOp(const LowerFunctionInfo &CallInfo,
// FIXME(cir): Use return value slot here.
Value RetVal = callOp.getResult();
// TODO(cir): Check for volatile return values.
assert(!::cir::MissingFeatures::volatileTypes());

// NOTE(cir): If the function returns, there should always be a valid
// return value present. Instead of setting the return value here, we
// should have the ReturnValueSlot object set it beforehand.
if (!RetVal) {
RetVal = callOp.getResult();
// TODO(cir): Check for volatile return values.
assert(::cir::MissingFeatures::volatileTypes());
}

// An empty record can overlap other data (if declared with
// no_unique_address); omit the store for such types - as there is no
// actual data to store.
if (dyn_cast<StructType>(RetTy) &&
cast<StructType>(RetTy).getNumElements() != 0) {
// NOTE(cir): I'm assuming we don't need to change any offsets here.
// Value StorePtr = emitAddressAtOffset(*this, RetVal, RetAI);
RetVal =
createCoercedValue(newCallOp.getResult(), RetVal.getType(), *this);
}
Original file line number Diff line number Diff line change
@@ -108,8 +108,8 @@ mlir::Type LowerTypes::convertType(Type T) {
/// LLVM IR representation for a given AST type. When a the ABI-specific
/// function info sets a nullptr for a return or argument type, the default
/// type given by this method is used. In CIR's case, its types are already
/// supposed to be ABI-specific, so this method is not really useful here. I'm
/// keeping it here for parity's sake.
/// supposed to be ABI-specific, so this method is not really useful here.
/// It's kept here for codegen parity's sake.

// Certain CIR types are already ABI-specific, so we just return them.
if (isa<BoolType, IntType, SingleType, DoubleType>(T)) {
Original file line number Diff line number Diff line change
@@ -239,18 +239,10 @@ void ItaniumRecordLayoutBuilder::layout(const StructType RT) {

layoutFields(RT);

// NonVirtualSize = Context.toCharUnitsFromBits(
// llvm::alignTo(getSizeInBits(),
// Context.getTargetInfo().getCharAlign()));
// NonVirtualAlignment = Alignment;
// PreferredNVAlignment = PreferredAlignment;

// // Lay out the virtual bases and add the primary virtual base offsets.
// LayoutVirtualBases(RD, RD);

// // Finally, round the size of the total struct up to the alignment
// // of the struct itself.
// FinishLayout(RD);
// FIXME(cir): Handle virtual-related layouts.
assert(!::cir::MissingFeatures::getCXXRecordBases());

assert(!::cir::MissingFeatures::itaniumRecordLayoutBuilderFinishLayout());
}

void ItaniumRecordLayoutBuilder::initializeLayout(const mlir::Type Ty) {
@@ -558,10 +550,6 @@ static bool mustSkipTailPadding(clang::TargetCXXABI ABI, const StructType RD) {
return false;

case clang::TargetCXXABI::UseTailPaddingUnlessPOD03:
// FIXME: To the extent that this is meant to cover the Itanium ABI
// rules, we should implement the restrictions about over-sized
// bitfields:
//
// http://itanium-cxx-abi.github.io/cxx-abi/abi.html#POD :
// In general, a type is considered a POD for the purposes of
// layout if it is a POD type (in the sense of ISO C++
@@ -605,7 +593,8 @@ const CIRRecordLayout &CIRLowerContext::getCIRRecordLayout(const Type D) const {

assert(RT.isComplete() && "Cannot get layout of forward declarations!");

// FIXME(cir): Cache the layout. Also, use a more MLIR-based approach.
// FIXME(cir): Use a more MLIR-based approach by using it's buitin data layout
// features, such as interfaces, cacheing, and the DLTI dialect.

const CIRRecordLayout *NewEntry = nullptr;

@@ -642,8 +631,8 @@ const CIRRecordLayout &CIRLowerContext::getCIRRecordLayout(const Type D) const {
Builder.PrimaryBaseIsVirtual, nullptr, false, false);
}

// TODO(cir): Cache the layout.
// TODO(cir): Add option to dump the layouts.
assert(!::cir::MissingFeatures::cacheRecordLayouts());

return *NewEntry;
}
Original file line number Diff line number Diff line change
@@ -235,9 +235,8 @@ void X86_64ABIInfo::classify(Type Ty, uint64_t OffsetBase, Class &Lo, Class &Hi,
} else if (isa<IntType>(Ty)) {

// FIXME(cir): Clang's BuiltinType::Kind allow comparisons (GT, LT, etc).
// We should implement this in CIR to simplify the conditions below. BTW,
// I'm not sure if the comparisons below are truly equivalent to the ones
// in Clang.
// We should implement this in CIR to simplify the conditions below. Hence,
// Comparisons below might not be truly equivalent to the ones in Clang.
if (isa<IntType>(Ty)) {
Current = Class::Integer;
}
3 changes: 1 addition & 2 deletions clang/test/CIR/Lowering/address-space.cir
Original file line number Diff line number Diff line change
@@ -5,8 +5,7 @@

module attributes {
cir.triple = "spirv64-unknown-unknown",
llvm.data_layout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1",
dlti.dl_spec = #dlti.dl_spec<> // Avoid assert errors.
llvm.data_layout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1"
} {
cir.global external addrspace(offload_global) @addrspace1 = #cir.int<1> : !s32i
// LLVM: @addrspace1 = addrspace(1) global i32