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Added grouping LRAM timings by cell configuration
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Signed-off-by: Maciej Kurc <[email protected]>
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mkurc-ant committed Sep 20, 2022
1 parent 8131499 commit b16d6d8
Showing 1 changed file with 23 additions and 3 deletions.
26 changes: 23 additions & 3 deletions timing/util/extract_cell_timings.py
Original file line number Diff line number Diff line change
Expand Up @@ -75,7 +75,7 @@ def unescape_sdf_name(name):

subtracts = {}

def rewrite_path(modules, modtype, from_pin, to_pin):
def rewrite_path(modules, modtype, from_pin, to_pin, cellconf=None):
# Rewrite a (celltype, from_pin, to_pin) tuple given cell data, or returns None to drop the path
# This looks at the JSON output by Yosys from the Lattice structural Verilog netlist in order
# to determine what the cells in the SDF file are actually doing
Expand Down Expand Up @@ -233,7 +233,17 @@ def strip_prefix_ebr(x, p):
continue
return (ebr_type, strip_prefix_ebr(from_pin, ebr_prefixes), strip_prefix_ebr(to_pin, ebr_prefixes))
if celltype.startswith("LRAM_CORE"):
return ("LRAM_CORE", strip_prefix(from_pin, lram_prefixes), strip_prefix(to_pin, lram_prefixes))
conf_str = ""
if cellconf is not None:
spen = "ENABLE" if cellconf["type"] == "SP512K" else "DISABLE"
if "OUTREG" in cellconf["params"]:
oreg_a = cellconf["params"]["OUTREG"]
oreg_b = cellconf["params"]["OUTREG"]
else:
oreg_a = cellconf["params"]["OUTREG_A"]
oreg_b = cellconf["params"]["OUTREG_B"]
conf_str = ":{},{},{}".format(spen, oreg_a, oreg_b)
return ("LRAM_CORE" + conf_str, strip_prefix(from_pin, lram_prefixes), strip_prefix(to_pin, lram_prefixes))
return None

def main():
Expand All @@ -256,13 +266,23 @@ def main():
with open(sdffile, "rb") as sdff:
sdf = pickle.load(sdff)

# Load cell configuration if any
conffile = netlist.rsplit("_", maxsplit=1)[0] + ".json"
try:
with open(conffile, "r") as fp:
conf = json.load(fp)
except FileNotFoundError:
conf = dict()

speed = sdffile.replace(".sdf.pickle", "").split("_")[-1]
assert speed in speedgrades
for cell in sdf.cells.values():
celltype = unescape_sdf_name(cell.type)
if conf is not None:
cellconf = conf.get(cell.inst.split("\\",maxsplit=1)[0], None)
for entry in cell.entries:
if isinstance(entry, IOPath):
rewritten = rewrite_path(modules, celltype, entry.from_pin, entry.to_pin)
rewritten = rewrite_path(modules, celltype, entry.from_pin, entry.to_pin, cellconf)
if rewritten is None:
continue
if rewritten in iopaths[speed]:
Expand Down

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