Merge remote-tracking branch 'refs/remotes/origin/main' into new_spi_dma

# Conflicts:
#	esp-hal/src/dma/mod.rs
#	esp-hal/src/soc/mod.rs
#	esp-hal/src/spi/master.rs
#	hil-test/tests/spi_full_duplex_dma.rs

esp-hal/CHANGELOG.md

@@ -16,6 +16,10 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 - Peripheral driver constructors don't take `InterruptHandler`s anymore. Use `set_interrupt_handler` to explicitly set the interrupt handler now. (#1819)
 - Migrate SPI driver to use DMA buffer objects (#1856)
+- Use the peripheral ref pattern for `OneShotTimer` and `PeriodicTimer` (#1855)
+
+- Allow DMA to/from psram for esp32s3 (#1827)
+- DMA buffers now don't require a static lifetime. Make sure to never `mem::forget` an in-progress DMA transfer (consider using `#[deny(clippy::mem_forget)]`) (#1837)
 
 ### Fixed
 

esp-hal/src/dma/mod.rs

@@ -155,7 +155,7 @@ pub trait WriteBuffer: crate::private::Sealed {
     ///
     /// Once this method has been called, it is unsafe to call any `&mut self`
     /// methods, except for `write_buffer`, on this object as long as the
-    /// returned value is in use (by DMA).    
+    /// returned value is in use (by DMA).
     unsafe fn write_buffer(&mut self) -> (*mut u8, usize);
 }
 
@@ -1279,6 +1279,25 @@ where
             return Err(DmaError::InvalidAlignment);
         }
 
+        // for esp32s3 we check each descriptor buffer that points to psram for
+        // alignment and invalidate the cache for that buffer
+        // NOTE: for RX the `buffer` and `size` need to be aligned but the `len` does
+        // not. TRM section 3.4.9
+        #[cfg(esp32s3)]
+        for des in chain.descriptors.iter() {
+            // we are forcing the DMA alignment to the cache line size
+            // required when we are using dcache
+            let alignment = crate::soc::cache_get_dcache_line_size() as usize;
+            if crate::soc::is_valid_psram_address(des.buffer as u32) {
+                // both the size and address of the buffer must be aligned
+                if des.buffer as usize % alignment != 0 && des.size() % alignment != 0 {
+                    return Err(DmaError::InvalidAlignment);
+                }
+                // TODO: make this optional?
+                crate::soc::cache_invalidate_addr(des.buffer as u32, des.size() as u32);
+            }
+        }
+
         self.rx_impl
             .prepare_transfer_without_start(chain.first() as _, peri)
     }
@@ -1592,6 +1611,21 @@ where
         peri: DmaPeripheral,
         chain: &DescriptorChain,
     ) -> Result<(), DmaError> {
+        // for esp32s3 we check each descriptor buffer that points to psram for
+        // alignment and writeback the cache for that buffer
+        #[cfg(esp32s3)]
+        for des in chain.descriptors.iter() {
+            // we are forcing the DMA alignment to the cache line size
+            // required when we are using dcache
+            let alignment = crate::soc::cache_get_dcache_line_size() as usize;
+            if crate::soc::is_valid_psram_address(des.buffer as u32) {
+                // both the size and address of the buffer must be aligned
+                if des.buffer as usize % alignment != 0 && des.size() % alignment != 0 {
+                    return Err(DmaError::InvalidAlignment);
+                }
+                crate::soc::cache_writeback_addr(des.buffer as u32, des.size() as u32);
+            }
+        }
         self.tx_impl
             .prepare_transfer_without_start(chain.first() as _, peri)
     }

esp-hal/src/soc/mod.rs

@@ -78,3 +78,20 @@ pub(crate) fn is_slice_in_dram<T>(slice: &[T]) -> bool {
     let end = start + slice.len() as u32;
     self::constants::SOC_DRAM_LOW <= start && end <= self::constants::SOC_DRAM_HIGH
 }
+
+#[allow(unused)]
+pub(crate) fn is_valid_psram_address(address: u32) -> bool {
+    #[cfg(psram)]
+    {
+        let start = crate::psram::psram_vaddr_start() as u32;
+        let end = start + crate::psram::PSRAM_BYTES as u32;
+        (start..=end).contains(&address)
+    }
+    #[cfg(not(psram))]
+    false
+}
+
+#[allow(unused)]
+pub(crate) fn is_valid_memory_address(address: u32) -> bool {
+    is_valid_ram_address(address) || is_valid_psram_address(address)
+}

esp-hal/src/spi/master.rs

@@ -859,7 +859,6 @@ pub mod dma {
             Spi2Peripheral,
             SpiPeripheral,
             TxPrivate,
-            WriteBuffer,
         },
         InterruptConfigurable,
         Mode,
@@ -2096,6 +2095,7 @@ pub trait InstanceDma: Instance {
 
         reset_dma_before_load_dma_dscr(reg_block);
 
+        self.clear_dma_interrupts();
         reset_dma_before_usr_cmd(reg_block);
 
         rx.prepare_transfer(self.dma_peripheral(), desc)?;