| 📸 Photo | 🏷️ Name | 🎯 Role | 🔗 GitHub | |
|---|---|---|---|---|
| Loïc NOGUES | Project Manager |  |
 |
|
| Alexis SANTOS | Program Manager | |
|
|
| Yann-Maël BOUTON | Technical Leader | |
|
|
| Lucas MEGNAN | Software Engineer | |
|
|
| Mathis LEBEL | Quality Assurance | |
|
|
| Gregory PAGNOU | Technical Writer | |
|
This project aims to develop a web-based interface for an FPGA simulator. The interface will allow the user (students) to see an animated FPGA board, where the data and electricity signals are represented.
- 2D Visualization of BELs and signal routing in the FPGA
- Preloaded Verilog Applications for educational use
- Teacher Dashboard to upload Verilog files and testbenches
- Animation On Board To Simulate Signals for the simulation
| Task | Deadline |
|---|---|
| 📄 Functional Specification | 03/13/2025 |
| ⚙️ Technical Specification | 03/25/2025 |
| 🖥️ Test Plan | 03/25/2025 |
| 👨💻 Code Implementation | 04/01/2025 |
| 📘 User Manual | 04/01/2025 |
| 🧪 Test Cases | 04/01/2025 |