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Register bug fixes #363

Merged
merged 3 commits into from
Dec 19, 2023
Merged

Register bug fixes #363

merged 3 commits into from
Dec 19, 2023

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jj16791
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@jj16791 jj16791 commented Dec 16, 2023

Within this PR, various identified bugs in dev are resolved. These include:

  • A fix for the AArch64 ST1W instruction when the first operand is of form za.d. The existing sve_merge_store_data assumed the vector and memory elements were the same width which is false. sve_merge_store_data now takes a secondary typename to describe the width of the memory elements.
  • It was possible for a test to fail as the process memory wasn't being cleared between RUN calls in the regression test suite. The process memory is now zeroed out before populating it.
  • The new Alias NYI exceptions did not consider that their non-renamed operands could be rewound if the instruction was fetched on an incorrectly speculated path and reserved an ROB entry. The Register struct now has an extra boolean attribute to describe whether its been generated as part of a renaming scheme. Only those registers with this attribute set to true will be rewound when the ROB is flushed.

Resolves #360, resolves #361, resolves #362

@jj16791 jj16791 added bug Something isn't working tests Testing and CI 0.9.6 Part of SimEng Release 0.9.6 labels Dec 16, 2023
@jj16791 jj16791 self-assigned this Dec 16, 2023
This was linked to issues Dec 16, 2023
sve_merge_store_data doesn't account for source vector elements and destination memory elements being different widths #360
Closed
Process memory not cleared between tests #361
Closed
Alias NYI exception can cause the incorrect rewinding of unrenamed physical registers #362
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@jj16791 jj16791 mentioned this pull request Dec 18, 2023
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dANW34V3R
dANW34V3R previously approved these changes Dec 18, 2023
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Good find, simple fix and well documented

JosephMoore25
JosephMoore25 previously approved these changes Dec 18, 2023
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Clear fixes, well commented, and looks good to be merged

@jj16791 jj16791 dismissed stale reviews from JosephMoore25 and dANW34V3R via 2c08dea December 19, 2023 10:53
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jj16791 commented Dec 19, 2023

#rerun tests

@jj16791 jj16791 merged commit dbe3952 into dev Dec 19, 2023
@jj16791 jj16791 deleted the register-bug-fixes branch December 19, 2023 16:03
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@dANW34V3R dANW34V3R dANW34V3R approved these changes

@FinnWilkinson FinnWilkinson FinnWilkinson approved these changes

@JosephMoore25 JosephMoore25 JosephMoore25 approved these changes

@rahahahat rahahahat Awaiting requested review from rahahahat

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0.9.6 Part of SimEng Release 0.9.6 bug Something isn't working tests Testing and CI
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@jj16791 @dANW34V3R @FinnWilkinson @JosephMoore25