Add alder lake to processor list

[gbaraldi]

Initial fix for #44691.
Alder lake also has the AVX-VNNI extension, but I haven't seen what are the correct bit masks for that feature in LLVM so that I can add them to features_x86.h.

[oscardssmith]

While we're doing this, would it make sense to say that unknown Intel+AMD CPUs have FMA and AVX2? It seems reasonable to assume that any cpu we don't know about is new.

[yuyichao]

The bitmask is not related to LLVM. It's simply the CPU ID value and should be added here

julia/src/features_x86.h

Line 111 in cf999af

JL_FEATURE_DEF(avx512bf16, 32 * 9 + 5, 0)

with bit 4 instead of bit 5.

The feature is also available in LLVM and it's name is avxvnni https://github.com/llvm/llvm-project/blob/80ec0ebfdc5692a58e0832125f2c6a991df9d63f/llvm/lib/Target/X86/X86.td#L163 and it was added in LLVM 12 as well.

[yuyichao]

While we're doing this, would it make sense to say that unknown Intel+AMD CPUs have FMA and AVX2? It seems reasonable to assume that any cpu we don't know about is new.

This should not be needed. Even without this, avx2 and fma should have been enabled since we do a full feature detection. The only thing missing is scheduling model.

[yuyichao]

LGTM other than the required compilation fix.

It's still good to know the exact feature set the processor supports. I doubt your i5 would have more features than the i7 but maybe the OS can mask these? This won't affect runtime since the correct features will be detected (and I don't think the affected features will change codegen in any way...) but may make a difference if you are compiling the system image for the target...

[yuyichao]

And just for reference, the cldemote claim comes from here https://github.com/JuliaLang/llvm-project/blob/bc5644ee74f4cb42042257ac129d2be1c252e3f2/llvm/lib/Target/X86/X86.td#L967

[gbaraldi]

Bump :)

stale

[KristofferC]

Merging based on #44696 (comment).