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Yi Zhouakiernan
Yi Zhou
authored and
akiernan
committed
hdmitx: fix DEADCODE errors
PD#150471: hdmitx: driver defect clean up: torvalds#168 torvalds#186 torvalds#200 torvalds#211 torvalds#192 Change-Id: Iffafec12c39cd98f8260a99417cb709ccc94935d Signed-off-by: Yi Zhou <[email protected]>
1 parent 6bf2b7e commit e14b754

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+26
-80
lines changed

2 files changed

+26
-80
lines changed

‎drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_main.c

-10
Original file line numberDiff line numberDiff line change
@@ -3060,11 +3060,6 @@ static int amhdmitx_probe(struct platform_device *pdev)
30603060

30613061
r = alloc_chrdev_region(&hdmitx_id, 0, HDMI_TX_COUNT,
30623062
DEVICE_NAME);
3063-
if (r < 0) {
3064-
hdmi_print(INF, SYS
3065-
"Can't register major for amhdmitx device\n");
3066-
return r;
3067-
}
30683063

30693064
hdmitx_class = class_create(THIS_MODULE, DEVICE_NAME);
30703065
if (IS_ERR(hdmitx_class)) {
@@ -3247,11 +3242,6 @@ static int amhdmitx_probe(struct platform_device *pdev)
32473242
pr_info("hdmitx: attr %s\n", fmt_attr);
32483243
hdmitx_device.task = kthread_run(hdmi_task_handle,
32493244
&hdmitx_device, "kthread_hdmi");
3250-
3251-
if (r < 0) {
3252-
hdmi_print(INF, SYS "register switch dev failed\n");
3253-
return r;
3254-
}
32553245
return r;
32563246
}
32573247

‎drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c

+26-70
Original file line numberDiff line numberDiff line change
@@ -887,7 +887,7 @@ static void hdmi_tvenc4k2k_set(struct hdmitx_vidpara *param)
887887
unsigned long TOTAL_PIXELS = 4400, PIXEL_REPEAT_HDMI = 0,
888888
PIXEL_REPEAT_VENC = 0, ACTIVE_PIXELS = 3840;
889889
unsigned int FRONT_PORCH = 1020, HSYNC_PIXELS = 0, ACTIVE_LINES = 2160,
890-
INTERLACE_MODE = 0, TOTAL_LINES = 0, SOF_LINES = 0,
890+
INTERLACE_MODE = 0U, TOTAL_LINES = 0, SOF_LINES = 0,
891891
VSYNC_LINES = 0;
892892
unsigned int LINES_F0 = 2250, LINES_F1 = 2250, BACK_PORCH = 0,
893893
EOF_LINES = 8, TOTAL_FRAMES = 0;
@@ -898,19 +898,17 @@ static void hdmi_tvenc4k2k_set(struct hdmitx_vidpara *param)
898898
unsigned long hsync_pixels_venc = 0;
899899

900900
unsigned long de_h_begin = 0, de_h_end = 0;
901-
unsigned long de_v_begin_even = 0, de_v_end_even = 0,
902-
de_v_begin_odd = 0, de_v_end_odd = 0;
901+
unsigned long de_v_begin_even = 0, de_v_end_even = 0;
903902
unsigned long hs_begin = 0, hs_end = 0;
904903
unsigned long vs_adjust = 0;
905-
unsigned long vs_bline_evn = 0, vs_eline_evn = 0, vs_bline_odd = 0,
906-
vs_eline_odd = 0;
907-
unsigned long vso_begin_evn = 0, vso_begin_odd = 0;
904+
unsigned long vs_bline_evn = 0, vs_eline_evn = 0;
905+
unsigned long vso_begin_evn = 0;
908906

909907
switch (param->VIC) {
910908
case HDMI_4k2k_30:
911909
case HDMI_3840x2160p60_16x9:
912910
case HDMI_3840x2160p60_16x9_Y420:
913-
INTERLACE_MODE = 0;
911+
INTERLACE_MODE = 0U;
914912
PIXEL_REPEAT_VENC = 0;
915913
PIXEL_REPEAT_HDMI = 0;
916914
ACTIVE_PIXELS = (3840*(1+PIXEL_REPEAT_HDMI));
@@ -928,7 +926,7 @@ static void hdmi_tvenc4k2k_set(struct hdmitx_vidpara *param)
928926
case HDMI_4k2k_25:
929927
case HDMI_3840x2160p50_16x9:
930928
case HDMI_3840x2160p50_16x9_Y420:
931-
INTERLACE_MODE = 0;
929+
INTERLACE_MODE = 0U;
932930
PIXEL_REPEAT_VENC = 0;
933931
PIXEL_REPEAT_HDMI = 0;
934932
ACTIVE_PIXELS = (3840*(1+PIXEL_REPEAT_HDMI));
@@ -944,7 +942,7 @@ static void hdmi_tvenc4k2k_set(struct hdmitx_vidpara *param)
944942
TOTAL_FRAMES = 3;
945943
break;
946944
case HDMI_4k2k_24:
947-
INTERLACE_MODE = 0;
945+
INTERLACE_MODE = 0U;
948946
PIXEL_REPEAT_VENC = 0;
949947
PIXEL_REPEAT_HDMI = 0;
950948
ACTIVE_PIXELS = (3840*(1+PIXEL_REPEAT_HDMI));
@@ -960,7 +958,7 @@ static void hdmi_tvenc4k2k_set(struct hdmitx_vidpara *param)
960958
TOTAL_FRAMES = 3;
961959
break;
962960
case HDMI_4k2k_smpte_24:
963-
INTERLACE_MODE = 0;
961+
INTERLACE_MODE = 0U;
964962
PIXEL_REPEAT_VENC = 0;
965963
PIXEL_REPEAT_HDMI = 0;
966964
ACTIVE_PIXELS = (4096*(1+PIXEL_REPEAT_HDMI));
@@ -978,7 +976,7 @@ static void hdmi_tvenc4k2k_set(struct hdmitx_vidpara *param)
978976
case HDMI_4096x2160p25_256x135:
979977
case HDMI_4096x2160p50_256x135:
980978
case HDMI_4096x2160p50_256x135_Y420:
981-
INTERLACE_MODE = 0;
979+
INTERLACE_MODE = 0U;
982980
PIXEL_REPEAT_VENC = 0;
983981
PIXEL_REPEAT_HDMI = 0;
984982
ACTIVE_PIXELS = (4096*(1+PIXEL_REPEAT_HDMI));
@@ -996,7 +994,7 @@ static void hdmi_tvenc4k2k_set(struct hdmitx_vidpara *param)
996994
case HDMI_4096x2160p30_256x135:
997995
case HDMI_4096x2160p60_256x135:
998996
case HDMI_4096x2160p60_256x135_Y420:
999-
INTERLACE_MODE = 0;
997+
INTERLACE_MODE = 0U;
1000998
PIXEL_REPEAT_VENC = 0;
1001999
PIXEL_REPEAT_HDMI = 0;
10021000
ACTIVE_PIXELS = (4096*(1+PIXEL_REPEAT_HDMI));
@@ -1038,16 +1036,6 @@ static void hdmi_tvenc4k2k_set(struct hdmitx_vidpara *param)
10381036
de_v_end_even = modulo(de_v_begin_even + ACTIVE_LINES, TOTAL_LINES);
10391037
hd_write_reg(P_ENCP_DE_V_BEGIN_EVEN, de_v_begin_even);
10401038
hd_write_reg(P_ENCP_DE_V_END_EVEN, de_v_end_even);
1041-
/* Program DE timing for odd field if needed */
1042-
if (INTERLACE_MODE) {
1043-
de_v_begin_odd = to_signed(
1044-
(hd_read_reg(P_ENCP_VIDEO_OFLD_VOAV_OFST) & 0xf0)>>4)
1045-
+ de_v_begin_even + (TOTAL_LINES-1)/2;
1046-
de_v_end_odd = modulo(de_v_begin_odd + ACTIVE_LINES,
1047-
TOTAL_LINES);
1048-
hd_write_reg(P_ENCP_DE_V_BEGIN_ODD, de_v_begin_odd);
1049-
hd_write_reg(P_ENCP_DE_V_END_ODD, de_v_end_odd);
1050-
}
10511039

10521040
/* Program Hsync timing */
10531041
if (de_h_end + front_porch_venc >= total_pixels_venc) {
@@ -1074,17 +1062,6 @@ static void hdmi_tvenc4k2k_set(struct hdmitx_vidpara *param)
10741062
vso_begin_evn = hs_begin;
10751063
hd_write_reg(P_ENCP_DVI_VSO_BEGIN_EVN, vso_begin_evn);
10761064
hd_write_reg(P_ENCP_DVI_VSO_END_EVN, vso_begin_evn);
1077-
/* Program Vsync timing for odd field if needed */
1078-
if (INTERLACE_MODE) {
1079-
vs_bline_odd = de_v_begin_odd-1 - SOF_LINES - VSYNC_LINES;
1080-
vs_eline_odd = de_v_begin_odd-1 - SOF_LINES;
1081-
vso_begin_odd = modulo(hs_begin + (total_pixels_venc>>1),
1082-
total_pixels_venc);
1083-
hd_write_reg(P_ENCP_DVI_VSO_BLINE_ODD, vs_bline_odd);
1084-
hd_write_reg(P_ENCP_DVI_VSO_ELINE_ODD, vs_eline_odd);
1085-
hd_write_reg(P_ENCP_DVI_VSO_BEGIN_ODD, vso_begin_odd);
1086-
hd_write_reg(P_ENCP_DVI_VSO_END_ODD, vso_begin_odd);
1087-
}
10881065
hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) |
10891066
(0 << 1) |
10901067
(HSYNC_POLARITY << 2) |
@@ -1285,7 +1262,7 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param)
12851262
unsigned long TOTAL_PIXELS = 0, PIXEL_REPEAT_HDMI = 0,
12861263
PIXEL_REPEAT_VENC = 0, ACTIVE_PIXELS = 0;
12871264
unsigned int FRONT_PORCH = 0, HSYNC_PIXELS = 0, ACTIVE_LINES = 0,
1288-
INTERLACE_MODE = 0, TOTAL_LINES = 0, SOF_LINES = 0,
1265+
INTERLACE_MODE = 0U, TOTAL_LINES = 0, SOF_LINES = 0,
12891266
VSYNC_LINES = 0;
12901267
unsigned int LINES_F0 = 0, LINES_F1 = 0, BACK_PORCH = 0,
12911268
EOF_LINES = 0, TOTAL_FRAMES = 0;
@@ -1296,17 +1273,15 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param)
12961273
unsigned long hsync_pixels_venc = 0;
12971274

12981275
unsigned long de_h_begin = 0, de_h_end = 0;
1299-
unsigned long de_v_begin_even = 0, de_v_end_even = 0,
1300-
de_v_begin_odd = 0, de_v_end_odd = 0;
1276+
unsigned long de_v_begin_even = 0, de_v_end_even = 0;
13011277
unsigned long hs_begin = 0, hs_end = 0;
13021278
unsigned long vs_adjust = 0;
1303-
unsigned long vs_bline_evn = 0, vs_eline_evn = 0,
1304-
vs_bline_odd = 0, vs_eline_odd = 0;
1305-
unsigned long vso_begin_evn = 0, vso_begin_odd = 0;
1279+
unsigned long vs_bline_evn = 0, vs_eline_evn = 0;
1280+
unsigned long vso_begin_evn = 0;
13061281

13071282
switch (param->VIC) {
13081283
case HDMI_3840x1080p120hz:
1309-
INTERLACE_MODE = 0;
1284+
INTERLACE_MODE = 0U;
13101285
PIXEL_REPEAT_VENC = 0;
13111286
PIXEL_REPEAT_HDMI = 0;
13121287
ACTIVE_PIXELS = 3840;
@@ -1322,7 +1297,7 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param)
13221297
TOTAL_FRAMES = 0;
13231298
break;
13241299
case HDMI_3840x1080p100hz:
1325-
INTERLACE_MODE = 0;
1300+
INTERLACE_MODE = 0U;
13261301
PIXEL_REPEAT_VENC = 0;
13271302
PIXEL_REPEAT_HDMI = 0;
13281303
ACTIVE_PIXELS = 3840;
@@ -1338,7 +1313,7 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param)
13381313
TOTAL_FRAMES = 0;
13391314
break;
13401315
case HDMI_3840x540p240hz:
1341-
INTERLACE_MODE = 0;
1316+
INTERLACE_MODE = 0U;
13421317
PIXEL_REPEAT_VENC = 0;
13431318
PIXEL_REPEAT_HDMI = 0;
13441319
ACTIVE_PIXELS = 3840;
@@ -1354,7 +1329,7 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param)
13541329
TOTAL_FRAMES = 0;
13551330
break;
13561331
case HDMI_3840x540p200hz:
1357-
INTERLACE_MODE = 0;
1332+
INTERLACE_MODE = 0U;
13581333
PIXEL_REPEAT_VENC = 0;
13591334
PIXEL_REPEAT_HDMI = 0;
13601335
ACTIVE_PIXELS = 3840;
@@ -1372,7 +1347,7 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param)
13721347
case HDMI_480p60:
13731348
case HDMI_480p60_16x9:
13741349
case HDMI_480p60_16x9_rpt:
1375-
INTERLACE_MODE = 0;
1350+
INTERLACE_MODE = 0U;
13761351
PIXEL_REPEAT_VENC = 1;
13771352
PIXEL_REPEAT_HDMI = 0;
13781353
ACTIVE_PIXELS = (720*(1+PIXEL_REPEAT_HDMI));
@@ -1390,7 +1365,7 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param)
13901365
case HDMI_576p50:
13911366
case HDMI_576p50_16x9:
13921367
case HDMI_576p50_16x9_rpt:
1393-
INTERLACE_MODE = 0;
1368+
INTERLACE_MODE = 0U;
13941369
PIXEL_REPEAT_VENC = 1;
13951370
PIXEL_REPEAT_HDMI = 0;
13961371
ACTIVE_PIXELS = (720*(1+PIXEL_REPEAT_HDMI));
@@ -1406,7 +1381,7 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param)
14061381
TOTAL_FRAMES = 4;
14071382
break;
14081383
case HDMI_720p60:
1409-
INTERLACE_MODE = 0;
1384+
INTERLACE_MODE = 0U;
14101385
PIXEL_REPEAT_VENC = 1;
14111386
PIXEL_REPEAT_HDMI = 0;
14121387
ACTIVE_PIXELS = (1280*(1+PIXEL_REPEAT_HDMI));
@@ -1422,7 +1397,7 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param)
14221397
TOTAL_FRAMES = 4;
14231398
break;
14241399
case HDMI_720p50:
1425-
INTERLACE_MODE = 0;
1400+
INTERLACE_MODE = 0U;
14261401
PIXEL_REPEAT_VENC = 1;
14271402
PIXEL_REPEAT_HDMI = 0;
14281403
ACTIVE_PIXELS = (1280*(1+PIXEL_REPEAT_HDMI));
@@ -1439,7 +1414,7 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param)
14391414
break;
14401415
case HDMI_1080p50:
14411416
case HDMI_1080p25:
1442-
INTERLACE_MODE = 0;
1417+
INTERLACE_MODE = 0U;
14431418
PIXEL_REPEAT_VENC = 0;
14441419
PIXEL_REPEAT_HDMI = 0;
14451420
ACTIVE_PIXELS = (1920*(1+PIXEL_REPEAT_HDMI));
@@ -1455,7 +1430,7 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param)
14551430
TOTAL_FRAMES = 4;
14561431
break;
14571432
case HDMI_1080p24:
1458-
INTERLACE_MODE = 0;
1433+
INTERLACE_MODE = 0U;
14591434
PIXEL_REPEAT_VENC = 0;
14601435
PIXEL_REPEAT_HDMI = 0;
14611436
ACTIVE_PIXELS = (1920*(1+PIXEL_REPEAT_HDMI));
@@ -1472,7 +1447,7 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param)
14721447
break;
14731448
case HDMI_1080p60:
14741449
case HDMI_1080p30:
1475-
INTERLACE_MODE = 0;
1450+
INTERLACE_MODE = 0U;
14761451
PIXEL_REPEAT_VENC = 0;
14771452
PIXEL_REPEAT_HDMI = 0;
14781453
ACTIVE_PIXELS = (1920*(1+PIXEL_REPEAT_HDMI));
@@ -1515,15 +1490,6 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param)
15151490
de_v_end_even = de_v_begin_even + ACTIVE_LINES;
15161491
hd_write_reg(P_ENCP_DE_V_BEGIN_EVEN, de_v_begin_even);
15171492
hd_write_reg(P_ENCP_DE_V_END_EVEN, de_v_end_even); /* 522 */
1518-
/* Program DE timing for odd field if needed */
1519-
if (INTERLACE_MODE) {
1520-
de_v_begin_odd = to_signed(
1521-
(hd_read_reg(P_ENCP_VIDEO_OFLD_VOAV_OFST)
1522-
& 0xf0)>>4) + de_v_begin_even + (TOTAL_LINES-1)/2;
1523-
de_v_end_odd = de_v_begin_odd + ACTIVE_LINES;
1524-
hd_write_reg(P_ENCP_DE_V_BEGIN_ODD, de_v_begin_odd);
1525-
hd_write_reg(P_ENCP_DE_V_END_ODD, de_v_end_odd);
1526-
}
15271493

15281494
/* Program Hsync timing */
15291495
if (de_h_end + front_porch_venc >= total_pixels_venc) {
@@ -1550,17 +1516,7 @@ static void hdmi_tvenc_set(struct hdmitx_vidpara *param)
15501516
vso_begin_evn = hs_begin; /* 1692 */
15511517
hd_write_reg(P_ENCP_DVI_VSO_BEGIN_EVN, vso_begin_evn); /* 1692 */
15521518
hd_write_reg(P_ENCP_DVI_VSO_END_EVN, vso_begin_evn); /* 1692 */
1553-
/* Program Vsync timing for odd field if needed */
1554-
if (INTERLACE_MODE) {
1555-
vs_bline_odd = de_v_begin_odd-1 - SOF_LINES - VSYNC_LINES;
1556-
vs_eline_odd = de_v_begin_odd-1 - SOF_LINES;
1557-
vso_begin_odd = modulo(hs_begin + (total_pixels_venc>>1),
1558-
total_pixels_venc);
1559-
hd_write_reg(P_ENCP_DVI_VSO_BLINE_ODD, vs_bline_odd);
1560-
hd_write_reg(P_ENCP_DVI_VSO_ELINE_ODD, vs_eline_odd);
1561-
hd_write_reg(P_ENCP_DVI_VSO_BEGIN_ODD, vso_begin_odd);
1562-
hd_write_reg(P_ENCP_DVI_VSO_END_ODD, vso_begin_odd);
1563-
}
1519+
15641520
if ((param->VIC == HDMI_3840x540p240hz) ||
15651521
(param->VIC == HDMI_3840x540p200hz))
15661522
hd_write_reg(P_ENCP_DE_V_END_EVEN, 0x230);

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