Skip to content

Files

Latest commit

 

History

History
143 lines (143 loc) · 32.3 KB

tuning_params_hardware.csv

File metadata and controls

143 lines (143 loc) · 32.3 KB
1
Categoryname (Parameter to be adjusted)desc (Parameter description)get (Command for querying parameter values.)set (Command for setting parameter values)needrestart(Whether require restart or not)type (discrete/continuous)options (For the discrete type, use";"to split different values.)dtype (For discrete, the parameter value type can only be int or string.)scope (Minimum value of the parameter)scope (Maximum Value of the parameter)step (Step of the parameter value)items (Enumerated values out of parameter values. Use ";" to split different values)select (whether to select the parameter)
2
Hardware-relatedprefetcherHardware prefetch policy. The value 0 indicates that the policy is disabled, and the value 15 indicates that the policy is enabled.cat /sys/class/misc/prefetch/policyecho $value > /sys/class/misc/prefetch/policyFALSEdiscrete0; 15int0151yes
3
read_uniqueWhether to allow cross-numa access to cache. 0--allow 1--forbid.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
4
reg_nosnp_atomic_bypass_enWhether to bypass atomic operations of CPUs. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
5
reg_ro_alloc_shut_enWhether to allow allocating readonce operation into L3. 0--allow 1--forbidcat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
6
reg_wrfull_hit_shut_enWhether to send createE to HA when 64wu-full hit spipe M. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
7
req_conflict_enWhether to enable the operation of reversing back one pat when receiving requests from both in and out of CPU. 0--disable 1--enable cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
8
lower_power_enWhether to enable CQ low power method. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
9
dataclean_shut_enWhether to shield the CE bit of Taishan Core's write_no_snoop_full. 0--not shield 1--shieldcat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
10
arb_flush_shut_enWhether to enable the reset of ARBIT scheduling pointer when CQ queue is at idle status. 0--enable 1--disablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
11
pgnt_arb_exat_shut_enWhether to enable pgrant scheduling method in which only one grant tries at one time. 0--enable 1--disablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
12
fast_exter_shut_enWhether to forbid data missed from extern requests to be transferred through fast access. 0--allow 1--forbidcat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
13
fast_data_shut_enWhether to forbid data missed to be transferred through fast access. 0--allow 1--forbidcat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
14
pend_data_shut_enWhether to forbid data missed to be transferred through pend access. 0--allow 1--forbidcat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
15
ramswap_full_shut_enFull or partial when doing ramswap. 1--partial 0--Full.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
16
ramfwd_shut_enEnable ramfwd method. 0--enable 1--disablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
17
reads_upgrade_enEnable read_shared operation status promotion. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
18
rdmerge_pipe_enWhether to allow requests from Sqmerge to be hit in Cpipe5. 0--forbid 1--allowcat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
19
spill_enEnable spill in L3T. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
20
spill_shared_enEnable spill at shared status of L3T. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
21
spill_instr_enEnable instruction spill in L3T. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
22
sqrdmerge_enUse RDMERGE acceleration in SQ merge operations. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
23
prefetch_drop_enEnable the drop of prefetch in L3T. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
24
datapull_enEnable the datapull in L3T. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
25
mkinvld_enEnable the transformation from makelinvalid to cleinvalid. 0--enable 1--disablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
26
ramthr_enAllow CPU to derive data back from thr channel directly in L3D. 0--forbid 1--allowcat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
27
rsperr_enAllow to report rsperr. 0--forbid 1--allowcat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
28
iocapacity_limit_enWhether to limit the io capacity of cache. 0--unlimiet 1--limit.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
29
force_cq_clk_enForce to open Cache queue clock. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
30
sqmerge_enWhether consecutive address access can occupy only one entry in the squeue to accelerate the merge process. 0--limit 1--merge.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
31
rdmerge_upgrade_enWhether to allow the RS to merge with the preceding ReadE. 0--disabl 1--allow.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
32
prefetch_drop_hha_enWhether to merge a non-prefetch operation with the previous prefetch operation. 0--allow 1--limit.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
33
tag_rep_algChoose cache line algorithm. 0--random 1--drrip 2--plru 3--random.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscreteint031yes
34
rdnosnp_nca_shut_enWhether to mark the readnosnp of the bypass sent by the CPU as NCA. 0--yes 1--nocat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
35
wrfull_create_enWhether to enable 128-byte writeunique only to obtain permission but not data from HHA. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
36
cleanunique_data_enWhether to enable the cleanunqunie to return data. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
37
lock_share_req_enWhether to enable the register lock function in share mode and not to deliver operations to the HHA. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
38
ddr_compress_opt_enOptimization switch of support HHA compression access. 0--disable 1--enable.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
39
atomic_monitor_enEnable atomic_monitor. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
40
snpsleep_enWhether to enable snp sleep. 0--disable 1--enable.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
41
prefetchtgt_enWhether to enable the prefetchtgt. 0--disable 1--enable.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
42
sequence_shape_enEnable to push back to the CPU for several cycles when the SQ is about to be full. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
43
mpam_portion_enEnable the function of allocating MPAM based on the way. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
44
mpam_capacity_enEnable the function of allocating MPAM based on capacity statistics. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
45
eccchk_enEnable ECC_CHK. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
46
refill_1024_relax_enWhether to use the 1024-bit size to send requests for access. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
47
lookup_thr_enWhether to enable the through channel during pipeline query. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
48
snpunique_stash_enSupport to receive hydra snpUniquestash. 0--forbid 1--supportcat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
49
prime_timeout_mask_enEnable the count for timeout. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
50
prime_sleep_mask_enEnable the function of releasing a sleep request after a period of time. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
51
prime_extend_mask_enWhether to enable random allocation of a request to extendway. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
52
force_intl_allocate_failEnable the function of forcibly determining that the assign operation of the intleave type fails. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
53
cpu_write_unique_stream_enWhether to forcibly process the writeunique operation delivered by the CPU as the stream type. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
54
cpu_pf_lqos_enWhether to enable the prefetch operation delivered by the CPU to be forcibly processed as the lqos operation. 0--disable 1--enable.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
55
cpu_vic_lqos_enWhether to enable the victim operation delivered by the CPU to be forcibly processed as the lqos operation. 0--disable 1--enable.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
56
prime_excl_mask_enWhether to enable the random exclusive operation. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
57
prime_drop_mask_enEnable prefetch to retry randomly. 0--disable 1--enable.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
58
prime_home_mask_enEnable the forcehome processing on internal requests randomly. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
59
refillsize_com_ada_enWhether to enable the auto-sensing of the size of the request sent to the HHA. If the size of the continuously received requests is 128 bytes or 64 bytes, the size of the prefetched request is automatically adjusted. 0--disable 1--enable adaptive size adjustment.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
60
refillsize_pre_ada_enWhether to enable the adaptation of the size of the request sent to the HHA. If the size of the continuously received request is 128 bytes or 64 bytes, the size of the normal request is automatically adjusted. 0--disable 1--enable adaptive size adjustment.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
61
sequence_opt_enWhether change the L3T processing to serial mode when blocking. 0--limit 1--enable.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
62
prefetch_clr_levelNumber of requests that fail to find the corresponding prefetch buffer and lower the priority of each buffer to make the existing buffer easier to replace. Range from 0~255.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscreteint02551yes
63
prefetch_overide_levelInitial coverage priority for an operation to enter the prefetch buffer. If the value is incorrect, the threshold is decreased by 1. If the value is correct, the threshold is increased by 1. If the value is 0, the prefetch rule needs to be replaced. range 0~15.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscreteint0151yes
64
prefetch_utl_ddrThe utilization of ddr that leads to the halving the threshold of prefetch. 0--less thean 1/2 1--1/2 2--3/4 3--almost full.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscreteint031yes
65
prefetch_utl_ddr_enWhether to allow the automatic threshold reduction according to the utilization of ddr. 0--forbid 1--allow.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
66
prefetch_utl_l3tThe utilization of l3t that leads to the halving the threshold of prefetch. 0--less thean 1/2 1--1/2 2--3/4 3--almost full.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscreteint031yes
67
prefetch_utl_l3t_enWhether to allow the automatic threshold reduction according to the utilization of l3t. 0--forbid 1--allow.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
68
prefetch_vague_enWhether to enable fuzzy match for prefetch. After the function is enabled, the prefetch summarizes the same 16 KB address rule. The four 4 KB address rules are the same and can be used together. 0--disable 1--enable.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
69
prefetch_core_enCore prefetch enable: Bit 1 indicates that the core request needs to be prefetched. range 0~15.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscreteint0151yes
70
prefetch_match_enWhether to enable the prefetch operation after the prefetch hit. 0--disable 1--enable.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
71
prefetch_start_levelThe number of missing addresses that leads to prefetch. 0--32 1--2 n-1--n, can be 0-31.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscreteint0311yes
72
pime_timeout_numThe maximum count of timeout. Range from 0 to 65535.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscreteint0655351yes
73
reg_ctrl_spillprefetchSnoop type configuration of the spill. 0--type of request 1--prefetchcat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
74
reg_ctrl_mpamenEnable HHA MPAM scheduling. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
75
reg_ctrl_mpamqosEnable QoS for modifying the DDR read/write command based on the MPAM monitoring and control bandwidth. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
76
reg_ctrl_poisonEnable HHA to return poison. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
77
reg_ctrl_compress_specEnable the random read of 128-byte data in HHA memory data compression. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
78
reg_ctrl_writeevict_dropEnable the discard of WriteEvictI. 0--disable 1--enable.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
79
reg_ctrl_prefetch_dropPrefetch operation discard enable. 0--disable 1--enable.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
80
reg_ctrl_dmcassignDDR access address alignment enable. 0--The DDR read operation uses the wrap mode, and the address is 32-byte-aligned. The DDR write operation is always in INCR mode, and the address is aligned with the access boundary. 1--The DDR read operation is always in INCR mode, and the address is aligned with the access boundary. The DDR write operation is always in INCR mode, and the address is aligned with the access boundary.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
81
reg_ctrl_rdatabypDDR read data bypass memory enable in the HHA. 0--disable 1--The internal data of the HHA is bypassed, and the DDR read data can be transmitted quickly.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
82
reg_ctrl_excl_clear_disWhether to disable the function of periodically clearing HHA non-cacheable exclusive monitor. 0--enable 1--disablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
83
reg_ctrl_excl_eventenEnable HHA non-cacheable exclusive monitor event. An event can be sent to wake up the CPU when an address is successfully written or corrupted. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
84
reg_ctrl_eccenEnable the memory ECC error correction in the HHA. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
85
reg_readoncesnp_disDisable NCA Readonce fixed snoop. 0--enable 1--disablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
86
reg_cc_exter_stashL3T configuration of extern snoop stash. 0--forbid 1--allowcat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
87
reg_cc_writebacki_spill_fullEnable fixed 128-byte data spill of the WritebackI operation. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
88
reg_cc_writeevicti_spill_fullEnable fixed 128-byte data spill of the WriteEvictI operation. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
89
reg_cc_stashonce_fullEnable fixed 128-byte data stash of the StashOnce operation. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
90
reg_cc_atomicstashl2Enable L2 stash of atomic operations. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
91
reg_cc_atomicstashl3Enable L3 stash of atomic operations. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
92
reg_cc_atomicstashclrClear L3 stash monitor of atomic operations. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
93
reg_cc_cmo_snpmeEnable snoop me for CMO operations. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
94
reg_cc_makee_changeEnable HHA MakeE conversion to readE when the HHA MakeE is not self-hit. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
95
reg_cc_ioc_hitsca_disDisable the function of recording CAIDs when the HHA I/O cache hits the exact directory. 0--enable 1--disablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
96
reg_cc_passdirtyEnable HHA pass dirty. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
97
reg_cc_snpdropEnable Snoop Drop. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
98
reg_cc_spillEnable local multi-partition sharing. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
99
reg_precisionsnp_disDisable HHA precise snoop based on shared directories. 0--enable 1--disablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
100
reg_notonly_exclWhether to create new entries for exclusive operations in the HHA share directory buffer. 0--only for exclusive operations 1--for all of operationscat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
101
reg_buffer_share_disDisable HHA share directory buffer. 0--enable 1--disablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
102
reg_miss_allindexEnable that HHA miss queues are related based on index. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
103
reg_miss_cbackthEnable HHA miss queue copyback request to use second threshold. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
104
reg_miss_normalthEnable HHA miss queue common request to use second threshold. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
105
reg_miss_tosdirEnable HHA only to allow miss alloc to be sent to sdir. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
106
reg_entry_exceptExclude the same entry address in HHA. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
107
reg_dir_precisionConfiguration of HHA precise directory. 0--disable to allow vague directory recording 1--enable to forbid vague directory recordingcat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
108
reg_dir_replace_algDirectory replacement algorithm configuration. 0--EDIR random+SDIR random 1--EDIR random+SDIR polling 2--EDIR PLRU+SDIR random 3--EDIR PLRU+SDIR pollingcat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscreteint031yes
109
strict_orderKeep the order of HHA operation queue strictly. 0--enable 1--unablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
110
prefetch_combRead operation and prefetchtgt merge enable. 0--The read operation can be merged with the fetchtgt operation. 1--The read operation and the fetchtgt merge operation are not allowed.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
111
evict_greenUnblocking configuration of the evict in PQ. 0--evict can't be blocked 1--evict can be blockedcat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
112
block_retryWhether to perform retry configuration directly when the MPAM hardlim flow bandwidth exceeds the configured one such that enters CMD. 0--retry directly 1--don't retry directly and be scheduled with other flowscat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
113
buffer_prioPriority configuration for the ingress queue of the CMD buffer request and PGNT application. 0--CMD buffer priors to pgnt 1--CMD buffer and pgnt have equivalent prioritycat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
114
half_wr_rdddr_delayEnables the DDR read delay during 64-byte full write operations after compression. 0--enable 1--disablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
115
wback_cnfl_rdhalfDDR size configuration that is reread when the writeback conflict occurs. 0--depend on Writeback address and size 1--size=128Bcat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
116
reg_funcdis_pendprecisionEnable precise pend. 0--pend is precisely depend on flit 1--pend=1cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
117
reg_funcdis_combrdddrReread DDR after multiple adjacent narrow write operations are merged.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
118
reg_funcdis_scrambleIngress queue scrambling. 0--enable 1--disablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
119
reg_funcdis_stashidpgWhether to enable the partial good conversion of the Stash TGTID. cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
120
reg_funcdis_rdatatimeHHA receives DMC read data anti-starvation threshold configuration. 0--threshold=8 1--threshold=4cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
121
reg_funcdis_dmcutlDMC usage source selection. 0--from DDRC 1--from queue processing utilization ratio inside HHAcat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
122
reg_funcdis_cancelexceptThe pipeline index check excludes requests that are not actually queried (for example, prefetchtgt). 0--enable exclusion 1--disable exclusioncat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
123
reg_funcdis_ccixcbupdateWhether to update the directory in the CCIX copyback of the multi-CA. 0--allow 1--forbidcat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
124
reg_funcdis_updateopenBlock the update dir command in the processing queue based on index. 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
125
reg_funcdis_combWhether to merge write operations whose size is less than 128 bytes. 0--enable 1--disables the merge function of the write operation.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
126
reg_prefetchtgt_outstandingOutstanding configuration for the HHA to read data from the DDR prefetch. When the read/write operation sent by the HHA to the DDR exceeds the threshold, the prefetchtgt operation is forbidden to read the DDR data and the operation is directly discarded. This configuration and reg_prefetch_outstanding control the prefetch threshold at the same time. Threshold ranges from 0 to 127.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscreteint01271yes
127
reg_prefetchtgt_levelThreshold for the HHA to read data from the DDR prefetch. When the DDR read/write operations in the HHA processing queue exceed the threshold, the prefetchtgt operation is forbidden to read the DDR data and the operation is directly discarded. This configuration and reg_prefetch_outstanding control the prefetch threshold at the same time. Threshold ranges from 0 to 127.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscreteint01271yes
128
reg_spec_rd_levelDDR threshold configuration for speculation read. When the DDR read and write commands in the HHA processing queue exceed the threshold, speculative reading of the DDR is prohibited. After the directory is queried, the system determines whether to read the DDR based on the directory query result. Note: The value 0x08 or 0x10 is recommended. Range from 0 to 127cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscreteint01271yes
129
reg_drop_levelPrefetch drop threshold configuration. When the number of DDR read and write commands in the HHA processing queue exceeds the threshold, some prefetch read commands can be discarded. Range from 0 to 127.cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscreteint01271yes
130
dvmsnp_outstandingOutstanding value of the DVMSNP of the MN. Note 1: If dvmsnp_perf_en is enabled, the configured value is valid. The maximum value of outstanding can be 5 when the TaiShan core is used. Otherwise, overflow errors occur. Note 2: The SMMU cannot match the Dvmsnp outstanding value 5. Therefore, you need to set the switch to 3 for Totem and Infinite of 1383. Totem and Nimbus of 1620: Set DVM outstanding to 5. However, do not configure POE for the DVMSNP broadcast node. The POE uses a private page table and does not require DVMSNP. Range from 0 to 15.(Note: 0 represents that outstanding level is 1)cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscreteint0151yes
131
dvmreq_outstandingOutstanding value of the DVMREQ of the MN. Note 1: If dvmreq_perf_en is enabled, the configured value is valid. The maximum value of outstanding can be 9 when there are four chips. Otherwise, an overflow error occurs. Note 2: In the case of two chips, the maximum outstanding value of totem can be 10, and the maximum outstanding value of nimbus or infinite is 24. This ensures the best performance. Note 3: In the case of a single chip, there is no restriction on the outstanding configuration of the totem. Range from 0 to 31.(Note: 0 represents that outstanding level is 1)cat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscreteint0311yes
132
dvmsnp_perf_enWhether to enable the outstanding level for the dvmsnp.(Note: After the function is enabled, the dvmsnp outstanding value of the MN is equal to the value of dvmsnp_outstanding.) 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes
133
dvmreq_perf_enWhether to enable the outstanding level for the dvmreq.(Note: After the function is enabled, the dvmreq outstanding value of the MN is equal to the value of dvmreq_outstanding.) 0--disable 1--enablecat /sys/class/misc/prefetch/@nameecho $value > /sys/class/misc/prefetch/@nameFALSEdiscrete0; 1stringyes