Skip to content

Commit f4cd522

Browse files
luyahantargos
luyahan
authored and
targos
committed
deps: V8: cherry-pick 77d515484864
Original commit message: [riscv64] Move explicit specialization into .cc file Building with Gcc-10 causes error "explicit specialization in non-namespace scope". This change fixes it. Bug: v8:12649 Change-Id: I36b2b042b336c2dfd32ba5541fdbbdb8dc8b4fd7 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3473997 Reviewed-by: ji qiu <[email protected]> Commit-Queue: ji qiu <[email protected]> Cr-Commit-Position: refs/heads/main@{#79185} Refs: v8/v8@77d5154 PR-URL: nodejs#42067 Refs: v8/v8@b663343 Reviewed-By: Michaël Zasso <[email protected]> Reviewed-By: Jiawen Geng <[email protected]> Reviewed-By: Richard Lau <[email protected]> Reviewed-By: Colin Ihrig <[email protected]> Reviewed-By: Mary Marchini <[email protected]> Reviewed-By: Juan José Arboleda <[email protected]> Reviewed-By: James M Snell <[email protected]> Reviewed-By: Stewart X Addison <[email protected]>
1 parent 67f1b77 commit f4cd522

File tree

3 files changed

+159
-159
lines changed

3 files changed

+159
-159
lines changed

‎common.gypi

+1-1
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@
3636

3737
# Reset this number to 0 on major V8 upgrades.
3838
# Increment by one for each non-official patch applied to deps/v8.
39-
'v8_embedder_string': '-node.10',
39+
'v8_embedder_string': '-node.11',
4040

4141
##### V8 defaults for Node.js #####
4242

‎deps/v8/src/execution/riscv64/simulator-riscv64.cc

+158
Original file line numberDiff line numberDiff line change
@@ -128,6 +128,164 @@ static inline bool is_overlapped_widen(const int astart, int asize,
128128
#define require_align(val, pos) CHECK_EQ(is_aligned(val, pos), true)
129129
#endif
130130

131+
// RVV
132+
// The following code about RVV was based from:
133+
// https://github.com/riscv/riscv-isa-sim
134+
// Copyright (c) 2010-2017, The Regents of the University of California
135+
// (Regents). All Rights Reserved.
136+
137+
// Redistribution and use in source and binary forms, with or without
138+
// modification, are permitted provided that the following conditions are met:
139+
// 1. Redistributions of source code must retain the above copyright
140+
// notice, this list of conditions and the following disclaimer.
141+
// 2. Redistributions in binary form must reproduce the above copyright
142+
// notice, this list of conditions and the following disclaimer in the
143+
// documentation and/or other materials provided with the distribution.
144+
// 3. Neither the name of the Regents nor the
145+
// names of its contributors may be used to endorse or promote products
146+
// derived from this software without specific prior written permission.
147+
148+
// IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
149+
// SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS,
150+
// ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
151+
// REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
152+
153+
// REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED
154+
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
155+
// PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
156+
// HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
157+
// MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
158+
template <uint64_t N>
159+
struct type_usew_t;
160+
template <>
161+
struct type_usew_t<8> {
162+
using type = uint8_t;
163+
};
164+
165+
template <>
166+
struct type_usew_t<16> {
167+
using type = uint16_t;
168+
};
169+
170+
template <>
171+
struct type_usew_t<32> {
172+
using type = uint32_t;
173+
};
174+
175+
template <>
176+
struct type_usew_t<64> {
177+
using type = uint64_t;
178+
};
179+
180+
template <>
181+
struct type_usew_t<128> {
182+
using type = __uint128_t;
183+
};
184+
template <uint64_t N>
185+
struct type_sew_t;
186+
187+
template <>
188+
struct type_sew_t<8> {
189+
using type = int8_t;
190+
};
191+
192+
template <>
193+
struct type_sew_t<16> {
194+
using type = int16_t;
195+
};
196+
197+
template <>
198+
struct type_sew_t<32> {
199+
using type = int32_t;
200+
};
201+
202+
template <>
203+
struct type_sew_t<64> {
204+
using type = int64_t;
205+
};
206+
207+
template <>
208+
struct type_sew_t<128> {
209+
using type = __int128_t;
210+
};
211+
212+
#define VV_PARAMS(x) \
213+
type_sew_t<x>::type& vd = \
214+
Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
215+
type_sew_t<x>::type vs1 = Rvvelt<type_sew_t<x>::type>(rvv_vs1_reg(), i); \
216+
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
217+
218+
#define VV_UPARAMS(x) \
219+
type_usew_t<x>::type& vd = \
220+
Rvvelt<type_usew_t<x>::type>(rvv_vd_reg(), i, true); \
221+
type_usew_t<x>::type vs1 = Rvvelt<type_usew_t<x>::type>(rvv_vs1_reg(), i); \
222+
type_usew_t<x>::type vs2 = Rvvelt<type_usew_t<x>::type>(rvv_vs2_reg(), i);
223+
224+
#define VX_PARAMS(x) \
225+
type_sew_t<x>::type& vd = \
226+
Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
227+
type_sew_t<x>::type rs1 = (type_sew_t<x>::type)(get_register(rs1_reg())); \
228+
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
229+
230+
#define VX_UPARAMS(x) \
231+
type_usew_t<x>::type& vd = \
232+
Rvvelt<type_usew_t<x>::type>(rvv_vd_reg(), i, true); \
233+
type_usew_t<x>::type rs1 = (type_usew_t<x>::type)(get_register(rs1_reg())); \
234+
type_usew_t<x>::type vs2 = Rvvelt<type_usew_t<x>::type>(rvv_vs2_reg(), i);
235+
236+
#define VI_PARAMS(x) \
237+
type_sew_t<x>::type& vd = \
238+
Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
239+
type_sew_t<x>::type simm5 = (type_sew_t<x>::type)(instr_.RvvSimm5()); \
240+
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
241+
242+
#define VI_UPARAMS(x) \
243+
type_usew_t<x>::type& vd = \
244+
Rvvelt<type_usew_t<x>::type>(rvv_vd_reg(), i, true); \
245+
type_usew_t<x>::type uimm5 = (type_usew_t<x>::type)(instr_.RvvUimm5()); \
246+
type_usew_t<x>::type vs2 = Rvvelt<type_usew_t<x>::type>(rvv_vs2_reg(), i);
247+
248+
#define VN_PARAMS(x) \
249+
constexpr int half_x = x >> 1; \
250+
type_sew_t<half_x>::type& vd = \
251+
Rvvelt<type_sew_t<half_x>::type>(rvv_vd_reg(), i, true); \
252+
type_sew_t<x>::type uimm5 = (type_sew_t<x>::type)(instr_.RvvUimm5()); \
253+
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
254+
255+
#define VN_UPARAMS(x) \
256+
constexpr int half_x = x >> 1; \
257+
type_usew_t<half_x>::type& vd = \
258+
Rvvelt<type_usew_t<half_x>::type>(rvv_vd_reg(), i, true); \
259+
type_usew_t<x>::type uimm5 = (type_usew_t<x>::type)(instr_.RvvUimm5()); \
260+
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
261+
262+
#define VXI_PARAMS(x) \
263+
type_sew_t<x>::type& vd = \
264+
Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
265+
type_sew_t<x>::type vs1 = Rvvelt<type_sew_t<x>::type>(rvv_vs1_reg(), i); \
266+
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i); \
267+
type_sew_t<x>::type rs1 = (type_sew_t<x>::type)(get_register(rs1_reg())); \
268+
type_sew_t<x>::type simm5 = (type_sew_t<x>::type)(instr_.RvvSimm5());
269+
270+
#define VI_XI_SLIDEDOWN_PARAMS(x, off) \
271+
auto& vd = Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
272+
auto vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i + off);
273+
274+
#define VI_XI_SLIDEUP_PARAMS(x, offset) \
275+
auto& vd = Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
276+
auto vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i - offset);
277+
278+
/* Vector Integer Extension */
279+
#define VI_VIE_PARAMS(x, scale) \
280+
if ((x / scale) < 8) UNREACHABLE(); \
281+
auto& vd = Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
282+
auto vs2 = Rvvelt<type_sew_t<x / scale>::type>(rvv_vs2_reg(), i);
283+
284+
#define VI_VIE_UPARAMS(x, scale) \
285+
if ((x / scale) < 8) UNREACHABLE(); \
286+
auto& vd = Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
287+
auto vs2 = Rvvelt<type_usew_t<x / scale>::type>(rvv_vs2_reg(), i);
288+
131289
#define require_noover(astart, asize, bstart, bsize) \
132290
CHECK_EQ(!is_overlapped(astart, asize, bstart, bsize), true)
133291
#define require_noover_widen(astart, asize, bstart, bsize) \

‎deps/v8/src/execution/riscv64/simulator-riscv64.h

-158
Original file line numberDiff line numberDiff line change
@@ -652,164 +652,6 @@ class Simulator : public SimulatorBase {
652652
}
653653
}
654654

655-
// RVV
656-
// The following code about RVV was based from:
657-
// https://github.com/riscv/riscv-isa-sim
658-
// Copyright (c) 2010-2017, The Regents of the University of California
659-
// (Regents). All Rights Reserved.
660-
661-
// Redistribution and use in source and binary forms, with or without
662-
// modification, are permitted provided that the following conditions are met:
663-
// 1. Redistributions of source code must retain the above copyright
664-
// notice, this list of conditions and the following disclaimer.
665-
// 2. Redistributions in binary form must reproduce the above copyright
666-
// notice, this list of conditions and the following disclaimer in the
667-
// documentation and/or other materials provided with the distribution.
668-
// 3. Neither the name of the Regents nor the
669-
// names of its contributors may be used to endorse or promote products
670-
// derived from this software without specific prior written permission.
671-
672-
// IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
673-
// SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS,
674-
// ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
675-
// REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
676-
677-
// REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED
678-
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
679-
// PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
680-
// HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
681-
// MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
682-
template <uint64_t N>
683-
struct type_usew_t;
684-
template <>
685-
struct type_usew_t<8> {
686-
using type = uint8_t;
687-
};
688-
689-
template <>
690-
struct type_usew_t<16> {
691-
using type = uint16_t;
692-
};
693-
694-
template <>
695-
struct type_usew_t<32> {
696-
using type = uint32_t;
697-
};
698-
699-
template <>
700-
struct type_usew_t<64> {
701-
using type = uint64_t;
702-
};
703-
704-
template <>
705-
struct type_usew_t<128> {
706-
using type = __uint128_t;
707-
};
708-
template <uint64_t N>
709-
struct type_sew_t;
710-
711-
template <>
712-
struct type_sew_t<8> {
713-
using type = int8_t;
714-
};
715-
716-
template <>
717-
struct type_sew_t<16> {
718-
using type = int16_t;
719-
};
720-
721-
template <>
722-
struct type_sew_t<32> {
723-
using type = int32_t;
724-
};
725-
726-
template <>
727-
struct type_sew_t<64> {
728-
using type = int64_t;
729-
};
730-
731-
template <>
732-
struct type_sew_t<128> {
733-
using type = __int128_t;
734-
};
735-
736-
#define VV_PARAMS(x) \
737-
type_sew_t<x>::type& vd = \
738-
Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
739-
type_sew_t<x>::type vs1 = Rvvelt<type_sew_t<x>::type>(rvv_vs1_reg(), i); \
740-
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
741-
742-
#define VV_UPARAMS(x) \
743-
type_usew_t<x>::type& vd = \
744-
Rvvelt<type_usew_t<x>::type>(rvv_vd_reg(), i, true); \
745-
type_usew_t<x>::type vs1 = Rvvelt<type_usew_t<x>::type>(rvv_vs1_reg(), i); \
746-
type_usew_t<x>::type vs2 = Rvvelt<type_usew_t<x>::type>(rvv_vs2_reg(), i);
747-
748-
#define VX_PARAMS(x) \
749-
type_sew_t<x>::type& vd = \
750-
Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
751-
type_sew_t<x>::type rs1 = (type_sew_t<x>::type)(get_register(rs1_reg())); \
752-
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
753-
754-
#define VX_UPARAMS(x) \
755-
type_usew_t<x>::type& vd = \
756-
Rvvelt<type_usew_t<x>::type>(rvv_vd_reg(), i, true); \
757-
type_usew_t<x>::type rs1 = (type_usew_t<x>::type)(get_register(rs1_reg())); \
758-
type_usew_t<x>::type vs2 = Rvvelt<type_usew_t<x>::type>(rvv_vs2_reg(), i);
759-
760-
#define VI_PARAMS(x) \
761-
type_sew_t<x>::type& vd = \
762-
Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
763-
type_sew_t<x>::type simm5 = (type_sew_t<x>::type)(instr_.RvvSimm5()); \
764-
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
765-
766-
#define VI_UPARAMS(x) \
767-
type_usew_t<x>::type& vd = \
768-
Rvvelt<type_usew_t<x>::type>(rvv_vd_reg(), i, true); \
769-
type_usew_t<x>::type uimm5 = (type_usew_t<x>::type)(instr_.RvvUimm5()); \
770-
type_usew_t<x>::type vs2 = Rvvelt<type_usew_t<x>::type>(rvv_vs2_reg(), i);
771-
772-
#define VN_PARAMS(x) \
773-
constexpr int half_x = x >> 1; \
774-
type_sew_t<half_x>::type& vd = \
775-
Rvvelt<type_sew_t<half_x>::type>(rvv_vd_reg(), i, true); \
776-
type_sew_t<x>::type uimm5 = (type_sew_t<x>::type)(instr_.RvvUimm5()); \
777-
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
778-
779-
#define VN_UPARAMS(x) \
780-
constexpr int half_x = x >> 1; \
781-
type_usew_t<half_x>::type& vd = \
782-
Rvvelt<type_usew_t<half_x>::type>(rvv_vd_reg(), i, true); \
783-
type_usew_t<x>::type uimm5 = (type_usew_t<x>::type)(instr_.RvvUimm5()); \
784-
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
785-
786-
#define VXI_PARAMS(x) \
787-
type_sew_t<x>::type& vd = \
788-
Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
789-
type_sew_t<x>::type vs1 = Rvvelt<type_sew_t<x>::type>(rvv_vs1_reg(), i); \
790-
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i); \
791-
type_sew_t<x>::type rs1 = (type_sew_t<x>::type)(get_register(rs1_reg())); \
792-
type_sew_t<x>::type simm5 = (type_sew_t<x>::type)(instr_.RvvSimm5());
793-
794-
#define VI_XI_SLIDEDOWN_PARAMS(x, off) \
795-
auto& vd = Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
796-
auto vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i + off);
797-
798-
#define VI_XI_SLIDEUP_PARAMS(x, offset) \
799-
auto& vd = Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
800-
auto vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i - offset);
801-
802-
/* Vector Integer Extension */
803-
#define VI_VIE_PARAMS(x, scale) \
804-
if ((x / scale) < 8) UNREACHABLE(); \
805-
auto& vd = Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
806-
auto vs2 = Rvvelt<type_sew_t<x / scale>::type>(rvv_vs2_reg(), i);
807-
808-
#define VI_VIE_UPARAMS(x, scale) \
809-
if ((x / scale) < 8) UNREACHABLE(); \
810-
auto& vd = Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
811-
auto vs2 = Rvvelt<type_usew_t<x / scale>::type>(rvv_vs2_reg(), i);
812-
813655
inline void rvv_trace_vd() {
814656
if (::v8::internal::FLAG_trace_sim) {
815657
__int128_t value = Vregister_[rvv_vd_reg()];

0 commit comments

Comments
 (0)