Update History
-V1.4.0
+V1.5.0
+/ 23-June-2017Main changes - Maintenance release to fix known defects and
+enhancements implementation
Generic drivers changes - MISRA C 2004 rule 11.4 (A cast should not be performed between a pointer to object type and a different pointer to object type).
- MISRA C 2004 rule 12.4 (The right-hand operand of a logical or I I operator shall not
contain side effects). - MISRA C 2004 rule 17.4 (Array indexing shall be the only allowed form of pointer arithmetic).
- Remove uselesss cast (uint32_t ) cast in case of 'U' suffix.
- Fix Code Sonar warnings (useless assignment, cast alters value, empty while statement ...).
- Minor improvement of
+ Doxygen Tags for CHM UM generation.
- Replace POSITION_VAL(xxx) macro by corresponding CMSIS_Pos definitions.
HAL Drivers changes - The following changes done on the HAL drivers require an update on the application code based on HAL V1.3.0
- HAL NAND driver: Overall driver rework with compatibility break versus previous HAL version (see below).
- HAL
- Correct RTC_PREDIV values (for LSI clock) in hal_timebase_rtc_alam_template.c and hal_timebase_rtc_wakeup_template.c
- Add definition of USE_SPI_CRC in hal_conf_template.h
- Modify HAL_Delay() function to garantee minimum delay.
- New API : HAL_GetUIDwx() read the unique device identifier word x.
- HAL ADC
- Remove unused litteral ADC_EOC_SINGLE_SEQ_CONV.
- Correct name of one ADC1 external trigger of regular group : ADC_EXTERNALTRIGCONV_T4_CC4.
- HAL CAN
- Add transmission abort when timeout is reached in HAL_CAN_Transmit().
- Add managment of overrun error.
- Store missing FIFO number in received message.
- Extend SET_BIT, CLEAR_BIT macro usage.
- Allow possibility to receive messages from the 2 RX FIFOs in parallel via interrupt.
- Fix message lost issue with specific sequence of transmit requests.
- HAL COMP
- COMP_WINDOWMODE litterals clean-up according to family diversity.
- HAL NAND
- Overall driver rework in order to support NAND flash memories with higher capacities.
- Add support of 16 bits adressing mode
- API changes :
- Add HAL_NAND_ConfigDevice() function
- Split HAL_NAND_Read_Page(),
+HAL_NAND_Write_Page(), HAL_NAND_Read_SpareArea(),
+HAL_NAND_Write_SpareArea() in _8b and _ 16b functions to select
+the proper adressing mode.
- HAL HRTIM
- Modify __HAL_HRTIM_SETCLOCKPRESCALER macro to clear CKPSC and CKPSCx bits before setting new prescaler value.
- Correct HRTIM_EVENTFASTMODE_DISABLE and HRTIM_EVENTFASTMODE_ENABLE defines.
- HAL I2C
- Editorial modification : astyle clean-up
- HAL SMBUS
- New API : Digital/Analog filter configuration with HAL_SMBUS_ConfigAnalogFilter() and HAL_SMBUS_ConfigDigitalFilter().
- HAL
+ PCD
- Fix and Improve PCD_ReadPMA() API to prevent corrupting user buffer.
- Minor changes in HAL_PCD_CLEAR_FLAG, PCD_CLEAR_TX/RX_EP_CTR macros.
- Fix USB device remote wakeup issue.
- USB PCD interrupt handler: remove useless usb device interrupts enable, already set during the pcd init.
- Remove lock/unlock from USB receive and transmit endpoints.
- HAL RTC
- Correct RTC Time register initialization.
- HAL SPI
- Empty RXFIFO in case of end of MASTER transmission 2 lines.
- HAL I2S
- Fix full duplex I2S with circular DMA issues :
- Don't stop DMA at end of transfert
- Solve synchroniszation issues between RX and TX.
- HAL TIM
- Fix typo in __HAL_TIM_SET_PRESCALER macro.
- Improvment of TIM DMA burst mode. Add 2 new API :
- HAL_TIM_DMABurst_MultiWriteStart()
- HAL_TIM_DMABurst_MultiReadStart()
- Add BRK2 (Break input 2 event) interrupt handler.
- Update IRQ handler to use correct defines (TIM_FLAG_xxxx instead of TIM_IT_xxxx) to clear flag.
+
LL Drivers changes - LL ADC
- Set TEMPSENSOR_CAL1_TEMP value to 30°C as specified in datasheet.
- LL DMA
- Replace SET_BIT macro by WRITE_REG in LL_DMA_ClearFlag_xxx() as DMA IFCR register is read only.
- For better performances, CPAR and CMAR regsiters are updated by WRITE_REG macro instead of MODIFY_REG.
- LL I2C
- OA1EN bit of OAR1 register should be set only when own address different from 0 (0 reserved for General Call address).
- LL RTC
- Update LL_RTC_DATE_Get() function for better performances.
- LL SPI
- Remove LL_SPI_SR_UDR (available only for I2S feature).
- LL_TIM
- Add AutomaticOutput field initialization in LL_TIM_BDTR_StructInit().
- Fix typo in __HAL_TIM_SET_PRESCALER macro.
- Ensure
+write operation of BKE and BKP bits is effective by adding fake read
+operation to garantee 1 APB clock cycle before function exit.
- Exchange behavior between LL_TIM_EnableUpdateEvent() and LL_TIM_DisableUpdateEvent().
- LL UTILS
- Update function UTILS_EnablePLLAndSwitchSystem() to use current AHB prescaler for sysclk frequency calculation.
V1.4.0
/ 16-December-2016Main changes
- Maintenance release to fix known defects and
enhancements implementation
HAL Drivers changes -
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c
index a5bc2e40a5..5be17ad4b1 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@@ -70,10 +68,10 @@
* @{
*/
/**
- * @brief STM32F3xx HAL Driver version number V1.4.0
+ * @brief STM32F3xx HAL Driver version number V1.5.0
*/
#define __STM32F3xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
-#define __STM32F3xx_HAL_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */
+#define __STM32F3xx_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */
#define __STM32F3xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32F3xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F3xx_HAL_VERSION ((__STM32F3xx_HAL_VERSION_MAIN << 24U)\
@@ -231,7 +229,7 @@ __weak void HAL_MspDeInit(void)
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
* The function is declared as __Weak to be overwritten in case of other
* implementation in user file.
- * @param TickPriority: Tick interrupt priority.
+ * @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
@@ -306,13 +304,21 @@ __weak uint32_t HAL_GetTick(void)
* is incremented.
* The function is declared as __Weak to be overwritten in case of other
* implementations in user file.
- * @param Delay: specifies the delay time length, in milliseconds.
+ * @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(__IO uint32_t Delay)
{
uint32_t tickstart = HAL_GetTick();
- while((HAL_GetTick() - tickstart) < Delay)
+ uint32_t wait = Delay;
+
+ /* Add a period to guarantee minimum wait */
+ if (wait < HAL_MAX_DELAY)
+ {
+ wait++;
+ }
+
+ while((HAL_GetTick() - tickstart) < wait)
{
}
}
@@ -379,6 +385,33 @@ uint32_t HAL_GetDEVID(void)
return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
}
+/**
+ * @brief Returns first word of the unique device identifier (UID based on 96 bits)
+ * @retval Device identifier
+ */
+uint32_t HAL_GetUIDw0(void)
+{
+ return(READ_REG(*((uint32_t *)UID_BASE)));
+}
+
+/**
+ * @brief Returns second word of the unique device identifier (UID based on 96 bits)
+ * @retval Device identifier
+ */
+uint32_t HAL_GetUIDw1(void)
+{
+ return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
+}
+
+/**
+ * @brief Returns third word of the unique device identifier (UID based on 96 bits)
+ * @retval Device identifier
+ */
+uint32_t HAL_GetUIDw2(void)
+{
+ return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
+}
+
/**
* @brief Enable the Debug Module during SLEEP mode
* @retval None
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c
index cbf7d0a5b4..a16d430f8f 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_adc.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC)
* peripheral:
@@ -416,7 +414,7 @@
* bypassed without error reporting: it can be the intended behaviour in
* case of update of a parameter of ADC_InitTypeDef on the fly,
* without disabling the other ADCs sharing the same common group.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
@@ -447,7 +445,7 @@ __weak HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
* let commented below.
* If needed, the example code can be copied and uncommented into
* function HAL_ADC_MspDeInit().
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
@@ -464,7 +462,7 @@ __weak HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
/**
* @brief Initializes the ADC MSP.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
@@ -479,7 +477,7 @@ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
/**
* @brief DeInitializes the ADC MSP.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
@@ -525,7 +523,7 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
* function must be called for ADC slave first, then ADC master.
* For ADC slave, ADC is enabled only (conversion is not started).
* For ADC master, ADC is enabled and multimode conversion is started.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
@@ -548,7 +546,7 @@ __weak HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
* For ADC master, converson is stopped and ADC is disabled.
* For ADC slave, ADC is disabled only (conversion stop of ADC master
* has already stopped conversion of ADC slave).
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval HAL status.
*/
__weak HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
@@ -565,8 +563,8 @@ __weak HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
/**
* @brief Wait for regular group conversion to be completed.
- * @param hadc: ADC handle
- * @param Timeout: Timeout value in millisecond.
+ * @param hadc ADC handle
+ * @param Timeout Timeout value in millisecond.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
@@ -584,15 +582,15 @@ __weak HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint
/**
* @brief Poll for conversion event.
- * @param hadc: ADC handle
- * @param EventType: the ADC event type.
+ * @param hadc ADC handle
+ * @param EventType the ADC event type.
* This parameter can be one of the following values:
* @arg ADC_AWD_EVENT: ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
* @arg ADC_AWD2_EVENT: ADC Analog watchdog 2 event (additional analog watchdog, present only on STM32F3 devices)
* @arg ADC_AWD3_EVENT: ADC Analog watchdog 3 event (additional analog watchdog, present only on STM32F3 devices)
* @arg ADC_OVR_EVENT: ADC Overrun event
* @arg ADC_JQOVF_EVENT: ADC Injected context queue overflow event
- * @param Timeout: Timeout value in millisecond.
+ * @param Timeout Timeout value in millisecond.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
@@ -621,7 +619,7 @@ __weak HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t
* function must be called for ADC slave first, then ADC master.
* For ADC slave, ADC is enabled only (conversion is not started).
* For ADC master, ADC is enabled and multimode conversion is started.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
@@ -648,7 +646,7 @@ __weak HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
* For ADC master, conversion is stopped and ADC is disabled.
* For ADC slave, ADC is disabled only (conversion stop of ADC master
* has already stopped conversion of ADC slave).
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval HAL status.
*/
__weak HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
@@ -674,9 +672,9 @@ __weak HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
* @note: Case of multimode enabled (for devices with several ADCs): This
* function is for single-ADC mode only. For multimode, use the
* dedicated MultimodeStart function.
- * @param hadc: ADC handle
- * @param pData: The destination Buffer address.
- * @param Length: The length of data to be transferred from ADC peripheral to memory.
+ * @param hadc ADC handle
+ * @param pData The destination Buffer address.
+ * @param Length The length of data to be transferred from ADC peripheral to memory.
* @retval None
*/
__weak HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
@@ -703,7 +701,7 @@ __weak HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pD
* @note: Case of multimode enabled (for devices with several ADCs): This
* function is for single-ADC mode only. For multimode, use the
* dedicated MultimodeStop function.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval HAL status.
*/
__weak HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
@@ -724,7 +722,7 @@ __weak HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
* regular group) flag.
* Additionally, this functions clears EOS (end of sequence of
* regular group) flag, in case of the end of the sequence is reached.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval Converted value
*/
__weak uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
@@ -738,7 +736,7 @@ __weak uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
/**
* @brief Handles ADC interrupt request.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
@@ -752,7 +750,7 @@ __weak void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
/**
* @brief Conversion complete callback in non blocking mode
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
@@ -767,7 +765,7 @@ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
/**
* @brief Conversion DMA half-transfer callback in non blocking mode
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
@@ -782,7 +780,7 @@ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
/**
* @brief Analog watchdog callback in non blocking mode.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
@@ -798,7 +796,7 @@ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
/**
* @brief ADC error callback in non blocking mode
* (ADC conversion with interruption or transfer by DMA)
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
@@ -849,8 +847,8 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
* The setting of these parameters is conditioned to ADC state.
* For parameters constraints, see comments of structure
* "ADC_ChannelConfTypeDef".
- * @param hadc: ADC handle
- * @param sConfig: Structure of ADC channel for regular group.
+ * @param hadc ADC handle
+ * @param sConfig Structure of ADC channel for regular group.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
@@ -876,8 +874,8 @@ __weak HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_Chan
* The setting of these parameters is conditioned to ADC state.
* For parameters constraints, see comments of structure
* "ADC_AnalogWDGConfTypeDef".
- * @param hadc: ADC handle
- * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
+ * @param hadc ADC handle
+ * @param AnalogWDGConfig Structure of ADC analog watchdog configuration
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
@@ -921,7 +919,7 @@ __weak HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_An
* For example:
* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) "
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval HAL state
*/
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
@@ -935,7 +933,7 @@ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
/**
* @brief Return the ADC error code
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval ADC Error Code
*/
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c
index 5ec840a1bb..69d398e7fb 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_adc_ex.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_adc_ex.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC)
* peripheral:
@@ -246,7 +244,7 @@ static void ADC_DMAError(DMA_HandleTypeDef *hdma);
* bypassed without error reporting: it can be the intended behaviour in
* case of update of a parameter of ADC_InitTypeDef on the fly,
* without disabling the other ADCs sharing the same common group.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
@@ -567,7 +565,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
* @note This function configures the ADC within 2 scopes: scope of entire
* ADC and scope of regular group. For parameters details, see comments
* of structure "ADC_InitTypeDef".
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
@@ -785,7 +783,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
* let commented below.
* If needed, the example code can be copied and uncommented into
* function HAL_ADC_MspDeInit().
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
@@ -1010,7 +1008,7 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
#if defined(STM32F373xC) || defined(STM32F378xx)
/**
* @brief Deinitialize the ADC peripheral registers to its default reset values.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
@@ -1200,7 +1198,7 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
* @note Case of multimode enabled (for devices with several ADCs):
* if ADC is slave, ADC is enabled only (conversion is not started).
* if ADC is master, ADC is enabled and multimode conversion is started.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
@@ -1314,7 +1312,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
/**
* @brief Enables ADC, starts conversion of regular group.
* Interruptions enabled in this function: None.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
@@ -1406,7 +1404,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
* To stop ADC conversion only on ADC group regular
* while letting ADC group injected conversions running,
* use function @ref HAL_ADCEx_RegularStop().
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
@@ -1456,7 +1454,7 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
* @note ADC peripheral disable is forcing interruption of potential
* conversion on injected group. If injected group is under use, it
* should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
@@ -1508,8 +1506,8 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
* performed on each conversion. Nevertheless, polling can still
* be performed on the complete sequence (ADC init
* parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
- * @param hadc: ADC handle
- * @param Timeout: Timeout value in millisecond.
+ * @param hadc ADC handle
+ * @param Timeout Timeout value in millisecond.
* @note Depending on init parameter "EOCSelection", flags EOS or EOC is
* checked and cleared depending on autodelay status (bit AUTDLY).
* @retval HAL status
@@ -1674,8 +1672,8 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti
* (several ranks selected): polling cannot be done on each
* conversion inside the sequence. In this case, polling is replaced by
* wait for maximum conversion time.
- * @param hadc: ADC handle
- * @param Timeout: Timeout value in millisecond.
+ * @param hadc ADC handle
+ * @param Timeout Timeout value in millisecond.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
@@ -1806,15 +1804,15 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
/**
* @brief Poll for conversion event.
- * @param hadc: ADC handle
- * @param EventType: the ADC event type.
+ * @param hadc ADC handle
+ * @param EventType the ADC event type.
* This parameter can be one of the following values:
* @arg ADC_AWD1_EVENT: ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
* @arg ADC_AWD2_EVENT: ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
* @arg ADC_AWD3_EVENT: ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
* @arg ADC_OVR_EVENT: ADC Overrun event
* @arg ADC_JQOVF_EVENT: ADC Injected context queue overflow event
- * @param Timeout: Timeout value in millisecond.
+ * @param Timeout Timeout value in millisecond.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
@@ -1928,11 +1926,11 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy
#if defined(STM32F373xC) || defined(STM32F378xx)
/**
* @brief Poll for conversion event.
- * @param hadc: ADC handle
- * @param EventType: the ADC event type.
+ * @param hadc ADC handle
+ * @param EventType the ADC event type.
* This parameter can be one of the following values:
* @arg ADC_AWD_EVENT: ADC Analog watchdog event.
- * @param Timeout: Timeout value in millisecond.
+ * @param Timeout Timeout value in millisecond.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
@@ -1992,7 +1990,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy
* function must be called for ADC slave first, then ADC master.
* For ADC slave, ADC is enabled only (conversion is not started).
* For ADC master, ADC is enabled and multimode conversion is started.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
@@ -2132,7 +2130,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
* Interruptions enabled in this function:
* - EOC (end of conversion of regular group)
* Each of these interruptions has its dedicated callback function.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
@@ -2229,7 +2227,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
* To stop ADC conversion only on ADC group regular
* while letting ADC group injected conversions running,
* use function @ref HAL_ADCEx_RegularStop_IT().
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
@@ -2281,7 +2279,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
* @brief Stop ADC conversion of regular group (and injected group in
* case of auto_injection mode), disable interrution of
* end-of-conversion, disable ADC peripheral.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval None
*/
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
@@ -2333,9 +2331,9 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
* @note Case of multimode enabled (for devices with several ADCs): This
* function is for single-ADC mode only. For multimode, use the
* dedicated MultimodeStart function.
- * @param hadc: ADC handle
- * @param pData: The destination Buffer address.
- * @param Length: The length of data to be transferred from ADC peripheral to memory.
+ * @param hadc ADC handle
+ * @param pData The destination Buffer address.
+ * @param Length The length of data to be transferred from ADC peripheral to memory.
* @retval None
*/
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
@@ -2486,9 +2484,9 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
* Each of these interruptions has its dedicated callback function.
* @note For devices with several ADCs: This function is for single-ADC mode
* only. For multimode, use the dedicated MultimodeStart function.
- * @param hadc: ADC handle
- * @param pData: The destination Buffer address.
- * @param Length: The length of data to be transferred from ADC peripheral to memory.
+ * @param hadc ADC handle
+ * @param pData The destination Buffer address.
+ * @param Length The length of data to be transferred from ADC peripheral to memory.
* @retval None
*/
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
@@ -2606,7 +2604,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
* @note Case of multimode enabled (for devices with several ADCs): This
* function is for single-ADC mode only. For multimode, use the
* dedicated MultimodeStop function.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
@@ -2686,7 +2684,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
* should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
* @note For devices with several ADCs: This function is for single-ADC mode
* only. For multimode, use the dedicated MultimodeStop function.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
@@ -2756,7 +2754,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
* in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
* model polling: @ref HAL_ADC_PollForConversion()
* or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval ADC group regular conversion data
*/
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
@@ -2792,7 +2790,7 @@ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
* in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
* model polling: @ref HAL_ADC_PollForConversion()
* or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval ADC group regular conversion data
*/
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
@@ -2814,7 +2812,7 @@ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
/**
* @brief Handles ADC interrupt request.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval None
*/
void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
@@ -3114,7 +3112,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
#if defined(STM32F373xC) || defined(STM32F378xx)
/**
* @brief Handles ADC interrupt request
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval None
*/
void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
@@ -3237,8 +3235,8 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
* @brief Perform an ADC automatic self-calibration
* Calibration prerequisite: ADC must be disabled (execute this
* function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
- * @param hadc: ADC handle
- * @param SingleDiff: Selection of single-ended or differential input
+ * @param hadc ADC handle
+ * @param SingleDiff Selection of single-ended or differential input
* This parameter can be one of the following values:
* @arg ADC_SINGLE_ENDED: Channel in mode input single ended
* @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended
@@ -3301,11 +3299,6 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_READY);
}
- else
- {
- /* Update ADC state machine to error */
- tmp_hal_status = HAL_ERROR;
- }
/* Process unlocked */
__HAL_UNLOCK(hadc);
@@ -3325,7 +3318,7 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t
* function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
* During calibration process, ADC is enabled. ADC is let enabled at
* the completion of this function.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
@@ -3431,8 +3424,8 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
/**
* @brief Get the calibration factor from automatic conversion result
- * @param hadc: ADC handle
- * @param SingleDiff: Selection of single-ended or differential input
+ * @param hadc ADC handle
+ * @param SingleDiff Selection of single-ended or differential input
* This parameter can be one of the following values:
* @arg ADC_SINGLE_ENDED: Channel in mode input single ended
* @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended
@@ -3465,12 +3458,12 @@ uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t Single
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
/**
* @brief Set the calibration factor to overwrite automatic conversion result. ADC must be enabled and no conversion on going.
- * @param hadc: ADC handle
- * @param SingleDiff: Selection of single-ended or differential input
+ * @param hadc ADC handle
+ * @param SingleDiff Selection of single-ended or differential input
* This parameter can be one of the following values:
* @arg ADC_SINGLE_ENDED: Channel in mode input single ended
* @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended
- * @param CalibrationFactor: Calibration factor (coded on 7 bits maximum)
+ * @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
* @retval HAL state
*/
HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
@@ -3535,7 +3528,7 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32
* function must be called for ADC slave first, then ADC master.
* For ADC slave, ADC is enabled only (conversion is not started).
* For ADC master, ADC is enabled and multimode conversion is started.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
@@ -3632,7 +3625,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
/**
* @brief Enables ADC, starts conversion of injected group.
* Interruptions enabled in this function: None.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
@@ -3723,7 +3716,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
* For ADC slave, ADC is disabled only (conversion stop of ADC master
* has already stopped conversion of ADC slave).
* @note In case of auto-injection mode, HAL_ADC_Stop must be used.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval None
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
@@ -3808,7 +3801,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
* regular group, function HAL_ADC_Stop must be used to stop both
* injected and regular groups, and disable the ADC.
* @note In case of auto-injection mode, HAL_ADC_Stop must be used.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval None
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
@@ -3865,8 +3858,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
/**
* @brief Wait for injected group conversion to be completed.
- * @param hadc: ADC handle
- * @param Timeout: Timeout value in millisecond.
+ * @param hadc ADC handle
+ * @param Timeout Timeout value in millisecond.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
@@ -3964,8 +3957,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u
#if defined(STM32F373xC) || defined(STM32F378xx)
/**
* @brief Wait for injected group conversion to be completed.
- * @param hadc: ADC handle
- * @param Timeout: Timeout value in millisecond.
+ * @param hadc ADC handle
+ * @param Timeout Timeout value in millisecond.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
@@ -4093,7 +4086,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u
* function must be called for ADC slave first, then ADC master.
* For ADC slave, ADC is enabled only (conversion is not started).
* For ADC master, ADC is enabled and multimode conversion is started.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
@@ -4213,7 +4206,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
* Interruptions enabled in this function:
* - JEOC (end of conversion of injected group)
* Each of these interruptions has its dedicated callback function.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
@@ -4313,7 +4306,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
* For ADC slave, ADC is disabled only (conversion stop of ADC master
* has already stopped conversion of ADC slave).
* @note In case of auto-injection mode, HAL_ADC_Stop must be used.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval None
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
@@ -4401,7 +4394,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
* @note If ADC must be disabled and if conversion is on going on
* regular group, function HAL_ADC_Stop must be used to stop both
* injected and regular groups, and disable the ADC.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval None
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
@@ -4471,9 +4464,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
* Each of these interruptions has its dedicated callback function.
* @note ADC slave must be preliminarily enabled using single-mode
* HAL_ADC_Start() function.
- * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
- * @param pData: The destination Buffer address.
- * @param Length: The length of data to be transferred from ADC peripheral to memory.
+ * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
+ * @param pData The destination Buffer address.
+ * @param Length The length of data to be transferred from ADC peripheral to memory.
* @retval None
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
@@ -4613,7 +4606,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
* @note In case of DMA configured in circular mode, function
* HAL_ADC_Stop_DMA must be called after this function with handle of
* ADC slave, to properly disable the DMA channel of ADC slave.
- * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
+ * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
* @retval None
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
@@ -4733,7 +4726,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
* @note Reading register CDR does not clear flag ADC flag EOC
* (ADC group regular end of unitary conversion),
* as it is the case for independent mode data register.
- * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
+ * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
* @retval The converted data value.
*/
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
@@ -4778,8 +4771,8 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
* in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
* model polling: @ref HAL_ADCEx_InjectedPollForConversion()
* or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
- * @param hadc: ADC handle
- * @param InjectedRank: the converted ADC injected rank.
+ * @param hadc ADC handle
+ * @param InjectedRank the converted ADC injected rank.
* This parameter can be one of the following values:
* @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
* @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
@@ -4844,8 +4837,8 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa
* in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
* model polling: @ref HAL_ADCEx_InjectedPollForConversion()
* or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
- * @param hadc: ADC handle
- * @param InjectedRank: the converted ADC injected rank.
+ * @param hadc ADC handle
+ * @param InjectedRank the converted ADC injected rank.
* This parameter can be one of the following values:
* @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
* @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
@@ -4898,7 +4891,7 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa
* use function @ref HAL_ADC_Stop().
* @note In case of auto-injection mode, this function also stop conversion
* on ADC group injected.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc)
@@ -4972,7 +4965,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc)
* use function @ref HAL_ADC_Stop().
* @note In case of auto-injection mode, this function also stop conversion
* on ADC group injected.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc)
@@ -5052,7 +5045,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc)
* @note Case of multimode enabled (for devices with several ADCs): This
* function is for single-ADC mode only. For multimode, use the
* dedicated MultimodeStop function.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc)
@@ -5164,7 +5157,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc)
* @note In case of DMA configured in circular mode, function
* HAL_ADC_Stop_DMA must be called after this function with handle of
* ADC slave, to properly disable the DMA channel of ADC slave.
- * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
+ * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
* @retval None
*/
HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc)
@@ -5309,7 +5302,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc)
/**
* @brief Injected conversion complete callback in non blocking mode
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
@@ -5332,7 +5325,7 @@ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
(parameter "QueueInjectedContext" in injected channel configuration)
and if a new injected context is set when queue is full (maximum 2
contexts).
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc)
@@ -5348,7 +5341,7 @@ __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc)
/**
* @brief Analog watchdog 2 callback in non blocking mode.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc)
@@ -5363,7 +5356,7 @@ __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc)
/**
* @brief Analog watchdog 3 callback in non blocking mode.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc)
@@ -5425,8 +5418,8 @@ __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc)
* The setting of these parameters is conditioned to ADC state.
* For parameters constraints, see comments of structure
* "ADC_ChannelConfTypeDef".
- * @param hadc: ADC handle
- * @param sConfig: Structure ADC channel for regular group.
+ * @param hadc ADC handle
+ * @param sConfig Structure ADC channel for regular group.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
@@ -5759,8 +5752,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
* The setting of these parameters is conditioned to ADC state.
* For parameters constraints, see comments of structure
* "ADC_ChannelConfTypeDef".
- * @param hadc: ADC handle
- * @param sConfig: Structure of ADC channel for regular group.
+ * @param hadc ADC handle
+ * @param sConfig Structure of ADC channel for regular group.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
@@ -5890,8 +5883,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
* HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and
* for each context (3 channels x 2 contexts = 6 calls). Conversion can
* start once the 1st context is set. The 2nd context can be set on the fly.
- * @param hadc: ADC handle
- * @param sConfigInjected: Structure of ADC injected group and ADC channel for
+ * @param hadc ADC handle
+ * @param sConfigInjected Structure of ADC injected group and ADC channel for
* injected group.
* @retval None
*/
@@ -6396,8 +6389,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
* Vbat/VrefInt/TempSensor.
* These internal paths can be be disabled using function
* HAL_ADC_DeInit().
- * @param hadc: ADC handle
- * @param sConfigInjected: Structure of ADC injected group and ADC channel for
+ * @param hadc ADC handle
+ * @param sConfigInjected Structure of ADC injected group and ADC channel for
* injected group.
* @retval None
*/
@@ -6643,8 +6636,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
* The setting of these parameters is conditioned to ADC state.
* For parameters constraints, see comments of structure
* "ADC_AnalogWDGConfTypeDef".
- * @param hadc: ADC handle
- * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
+ * @param hadc ADC handle
+ * @param AnalogWDGConfig Structure of ADC analog watchdog configuration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
@@ -6848,8 +6841,8 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG
* Considering that registers write delay may happen due to
* bus activity, this might cause an uncertainty on the
* effective timing of the new programmed threshold values.
- * @param hadc: ADC handle
- * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
+ * @param hadc ADC handle
+ * @param AnalogWDGConfig Structure of ADC analog watchdog configuration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
@@ -6928,8 +6921,8 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG
* "ADC_MultiModeTypeDef".
* @note To change back configuration from multimode to single mode, ADC must
* be reset (using function HAL_ADC_Init() ).
- * @param hadc: ADC handle
- * @param multimode : Structure of ADC multimode configuration
+ * @param hadc ADC handle
+ * @param multimode Structure of ADC multimode configuration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
@@ -6947,12 +6940,16 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
}
- /* Process locked */
- __HAL_LOCK(hadc);
-
-
/* Set handle of the other ADC sharing the same common register */
ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
+ if (tmphadcSharingSameCommonRegister.Instance == NULL)
+ {
+ /* Return function status */
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hadc);
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
@@ -7055,7 +7052,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
*/
/**
* @brief DMA transfer complete callback.
- * @param hdma: pointer to DMA handle.
+ * @param hdma pointer to DMA handle.
* @retval None
*/
static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
@@ -7098,7 +7095,7 @@ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA half transfer complete callback.
- * @param hdma: pointer to DMA handle.
+ * @param hdma pointer to DMA handle.
* @retval None
*/
static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
@@ -7112,7 +7109,7 @@ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA error callback
- * @param hdma: pointer to DMA handle.
+ * @param hdma pointer to DMA handle.
* @retval None
*/
static void ADC_DMAError(DMA_HandleTypeDef *hdma)
@@ -7138,7 +7135,7 @@ static void ADC_DMAError(DMA_HandleTypeDef *hdma)
* @brief Enable the selected ADC.
* @note Prerequisite condition to use this function: ADC must be disabled
* and voltage regulator must be enabled (done into HAL_ADC_Init()).
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval HAL status.
*/
static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
@@ -7192,7 +7189,7 @@ static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
* @brief Disable the selected ADC.
* @note Prerequisite condition to use this function: ADC conversions must be
* stopped.
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval HAL status.
*/
static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
@@ -7246,8 +7243,8 @@ static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
/**
* @brief Stop ADC conversion.
- * @param hadc: ADC handle
- * @param ConversionGroup: ADC group regular and/or injected.
+ * @param hadc ADC handle
+ * @param ConversionGroup ADC group regular and/or injected.
* This parameter can be one of the following values:
* @arg ADC_REGULAR_GROUP: ADC regular conversion type.
* @arg ADC_INJECTED_GROUP: ADC injected conversion type.
@@ -7372,7 +7369,7 @@ static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t Co
* @brief Enable the selected ADC.
* @note Prerequisite condition to use this function: ADC must be disabled
* and voltage regulator must be enabled (done into HAL_ADC_Init()).
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval HAL status.
*/
static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
@@ -7425,7 +7422,7 @@ static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
/**
* @brief Stop ADC conversion and disable the selected ADC
- * @param hadc: ADC handle
+ * @param hadc ADC handle
* @retval HAL status.
*/
static HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c
index 78eb05704a..99f2bf704c 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_can.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief CAN HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Controller Area Network (CAN) peripheral:
@@ -28,9 +26,13 @@
(#) Initialise and configure the CAN using HAL_CAN_Init() function.
(#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
-
+
+ (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function.
+
(#) Receive a CAN frame using HAL_CAN_Receive() function.
+ (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function.
+
*** Polling mode IO operation ***
=================================
[..]
@@ -123,7 +125,7 @@
/** @defgroup CAN_Private_Constants CAN Private Constants
* @{
*/
-#define CAN_TIMEOUT_VALUE 10
+#define CAN_TIMEOUT_VALUE 10U
/**
* @}
*/
@@ -163,7 +165,7 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
/**
* @brief Initializes the CAN peripheral according to the specified
* parameters in the CAN_InitStruct.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL status
*/
@@ -204,16 +206,16 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
hcan->State = HAL_CAN_STATE_BUSY;
/* Exit from sleep mode */
- hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
/* Request initialisation */
- hcan->Instance->MCR |= CAN_MCR_INRQ ;
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait the acknowledge */
- while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
+ while(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
{
if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
{
@@ -225,95 +227,97 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
}
/* Check acknowledge */
- if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
+ if (HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
{
/* Set the time triggered communication mode */
if (hcan->Init.TTCM == ENABLE)
{
- hcan->Instance->MCR |= CAN_MCR_TTCM;
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
}
else
{
- hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM;
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
}
/* Set the automatic bus-off management */
if (hcan->Init.ABOM == ENABLE)
{
- hcan->Instance->MCR |= CAN_MCR_ABOM;
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
}
else
{
- hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM;
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
}
/* Set the automatic wake-up mode */
if (hcan->Init.AWUM == ENABLE)
{
- hcan->Instance->MCR |= CAN_MCR_AWUM;
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
}
else
{
- hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM;
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
}
/* Set the no automatic retransmission */
if (hcan->Init.NART == ENABLE)
{
- hcan->Instance->MCR |= CAN_MCR_NART;
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_NART);
}
else
{
- hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART;
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART);
}
/* Set the receive FIFO locked mode */
if (hcan->Init.RFLM == ENABLE)
{
- hcan->Instance->MCR |= CAN_MCR_RFLM;
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
}
else
{
- hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM;
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
}
/* Set the transmit FIFO priority */
if (hcan->Init.TXFP == ENABLE)
{
- hcan->Instance->MCR |= CAN_MCR_TXFP;
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
}
else
{
- hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP;
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
}
/* Set the bit timing register */
- hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \
- ((uint32_t)hcan->Init.SJW) | \
- ((uint32_t)hcan->Init.BS1) | \
- ((uint32_t)hcan->Init.BS2) | \
- ((uint32_t)hcan->Init.Prescaler - 1U);
+ WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode |
+ hcan->Init.SJW |
+ hcan->Init.BS1 |
+ hcan->Init.BS2 |
+ (hcan->Init.Prescaler - 1U) ));
/* Request leave initialisation */
- hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait the acknowledge */
- while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
+ while(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
{
if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
{
hcan->State= HAL_CAN_STATE_TIMEOUT;
+
/* Process unlocked */
__HAL_UNLOCK(hcan);
- return HAL_TIMEOUT;
+
+ return HAL_TIMEOUT;
}
}
/* Check acknowledged */
- if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
+ if(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
{
status = CAN_INITSTATUS_SUCCESS;
}
@@ -343,9 +347,9 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
/**
* @brief Configures the CAN reception filter according to the specified
* parameters in the CAN_FilterInitStruct.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
- * @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that
+ * @param sFilterConfig pointer to a CAN_FilterConfTypeDef structure that
* contains the filter configuration information.
* @retval None
*/
@@ -359,20 +363,20 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTy
assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
-
+
filternbrbitpos = (1U) << sFilterConfig->FilterNumber;
/* Initialisation mode for the filter */
- hcan->Instance->FMR |= (uint32_t)CAN_FMR_FINIT;
-
+ SET_BIT(hcan->Instance->FMR, CAN_FMR_FINIT);
+
/* Filter Deactivation */
- hcan->Instance->FA1R &= ~(uint32_t)filternbrbitpos;
+ CLEAR_BIT(hcan->Instance->FA1R, filternbrbitpos);
/* Filter Scale */
if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
{
/* 16-bit scale for the filter */
- hcan->Instance->FS1R &= ~(uint32_t)filternbrbitpos;
+ CLEAR_BIT(hcan->Instance->FS1R, filternbrbitpos);
/* First 16-bit identifier and First 16-bit mask */
/* Or First 16-bit identifier and Second 16-bit identifier */
@@ -390,11 +394,13 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTy
if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
{
/* 32-bit scale for the filter */
- hcan->Instance->FS1R |= filternbrbitpos;
+ SET_BIT(hcan->Instance->FS1R, filternbrbitpos);
+
/* 32-bit identifier or First 32-bit identifier */
hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
(0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
+
/* 32-bit mask or Second 32-bit identifier */
hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
@@ -405,35 +411,34 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTy
if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
{
/*Id/Mask mode for the filter*/
- hcan->Instance->FM1R &= ~(uint32_t)filternbrbitpos;
+ CLEAR_BIT(hcan->Instance->FM1R, filternbrbitpos);
}
else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
{
/*Identifier list mode for the filter*/
- hcan->Instance->FM1R |= (uint32_t)filternbrbitpos;
+ SET_BIT(hcan->Instance->FM1R, filternbrbitpos);
}
/* Filter FIFO assignment */
if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
{
/* FIFO 0 assignation for the filter */
- hcan->Instance->FFA1R &= ~(uint32_t)filternbrbitpos;
+ CLEAR_BIT(hcan->Instance->FFA1R, filternbrbitpos);
}
-
- if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1)
+ else
{
/* FIFO 1 assignation for the filter */
- hcan->Instance->FFA1R |= (uint32_t)filternbrbitpos;
+ SET_BIT(hcan->Instance->FFA1R, filternbrbitpos);
}
/* Filter activation */
if (sFilterConfig->FilterActivation == ENABLE)
{
- hcan->Instance->FA1R |= filternbrbitpos;
+ SET_BIT(hcan->Instance->FA1R, filternbrbitpos);
}
/* Leave the initialisation mode for the filter */
- hcan->Instance->FMR &= ~((uint32_t)CAN_FMR_FINIT);
+ CLEAR_BIT(hcan->Instance->FMR, ((uint32_t)CAN_FMR_FINIT));
/* Return function status */
return HAL_OK;
@@ -441,7 +446,7 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTy
/**
* @brief Deinitializes the CANx peripheral registers to their default reset values.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL status
*/
@@ -474,7 +479,7 @@ HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
/**
* @brief Initializes the CAN MSP.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
@@ -490,7 +495,7 @@ __weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
/**
* @brief DeInitializes the CAN MSP.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
@@ -527,9 +532,9 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
/**
* @brief Initiates and transmits a CAN frame message.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
- * @param Timeout: Timeout duration.
+ * @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
@@ -549,29 +554,35 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
/* Process locked */
__HAL_LOCK(hcan);
- if(hcan->State == HAL_CAN_STATE_BUSY_RX)
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
- }
- else
+ /* Change CAN state */
+ switch(hcan->State)
{
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_TX;
+ case(HAL_CAN_STATE_BUSY_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
}
/* Select one empty transmit mailbox */
if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
{
- transmitmailbox = 0U;
+ transmitmailbox = CAN_TXMAILBOX_0;
}
else if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
{
- transmitmailbox = 1U;
+ transmitmailbox = CAN_TXMAILBOX_1;
}
else
{
- transmitmailbox = 2U;
+ transmitmailbox = CAN_TXMAILBOX_2;
}
/* Set up the Id */
@@ -579,15 +590,15 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
if (hcan->pTxMsg->IDE == CAN_ID_STD)
{
assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \
- hcan->pTxMsg->RTR);
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) | \
+ hcan->pTxMsg->RTR);
}
else
{
assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \
- hcan->pTxMsg->IDE | \
- hcan->pTxMsg->RTR);
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) | \
+ hcan->pTxMsg->IDE | \
+ hcan->pTxMsg->RTR);
}
/* Set up the DLC */
@@ -596,14 +607,14 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
/* Set up the data field */
- WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << 24U) |
- ((uint32_t)hcan->pTxMsg->Data[2] << 16U) |
- ((uint32_t)hcan->pTxMsg->Data[1] << 8U) |
- ((uint32_t)hcan->pTxMsg->Data[0] ) );
- WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << 24U) |
- ((uint32_t)hcan->pTxMsg->Data[6] << 16U) |
- ((uint32_t)hcan->pTxMsg->Data[5] << 8U) |
- ((uint32_t)hcan->pTxMsg->Data[4] ) );
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_Pos));
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_Pos));
/* Request transmission */
SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
@@ -630,17 +641,24 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
}
}
}
- if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_RX;
- }
- else
+
+ /* Change CAN state */
+ switch(hcan->State)
{
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_READY;
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_TX */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
}
-
+
/* Process unlocked */
__HAL_UNLOCK(hcan);
@@ -659,7 +677,7 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
/**
* @brief Initiates and transmits a CAN frame message.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL status
*/
@@ -682,15 +700,15 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
/* Select one empty transmit mailbox */
if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
{
- transmitmailbox = 0U;
+ transmitmailbox = CAN_TXMAILBOX_0;
}
else if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
{
- transmitmailbox = 1U;
+ transmitmailbox = CAN_TXMAILBOX_1;
}
else
{
- transmitmailbox = 2U;
+ transmitmailbox = CAN_TXMAILBOX_2;
}
/* Set up the Id */
@@ -698,14 +716,14 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
if(hcan->pTxMsg->IDE == CAN_ID_STD)
{
assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) | \
hcan->pTxMsg->RTR);
}
else
{
assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \
- hcan->pTxMsg->IDE | \
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) | \
+ hcan->pTxMsg->IDE | \
hcan->pTxMsg->RTR);
}
@@ -715,24 +733,30 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
/* Set up the data field */
- WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << 24U) |
- ((uint32_t)hcan->pTxMsg->Data[2] << 16U) |
- ((uint32_t)hcan->pTxMsg->Data[1] << 8U) |
- ((uint32_t)hcan->pTxMsg->Data[0] ) );
- WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << 24U) |
- ((uint32_t)hcan->pTxMsg->Data[6] << 16U) |
- ((uint32_t)hcan->pTxMsg->Data[5] << 8U) |
- ((uint32_t)hcan->pTxMsg->Data[4] ) );
-
- if(hcan->State == HAL_CAN_STATE_BUSY_RX)
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
- }
- else
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_Pos));
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_Pos));
+
+ /* Change CAN state */
+ switch(hcan->State)
{
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_TX;
+ case(HAL_CAN_STATE_BUSY_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
}
/* Set CAN error code to none */
@@ -741,6 +765,9 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
/* Process Unlocked */
__HAL_UNLOCK(hcan);
+ /* Request transmission */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
+
/* Enable interrupts: */
/* - Enable Error warning Interrupt */
/* - Enable Error passive Interrupt */
@@ -754,9 +781,6 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
CAN_IT_LEC |
CAN_IT_ERR |
CAN_IT_TME );
-
- /* Request transmission */
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
}
else
{
@@ -772,34 +796,85 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
/**
* @brief Receives a correct CAN frame.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
- * @param FIFONumber: FIFO number.
- * @param Timeout: Timeout duration.
+ * @param FIFONumber FIFO number.
+ * @param Timeout Timeout duration.
* @retval HAL status
- * @retval None
*/
HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
{
uint32_t tickstart = 0U;
-
+ CanRxMsgTypeDef* pRxMsg = NULL;
+
/* Check the parameters */
assert_param(IS_CAN_FIFO(FIFONumber));
-
+
/* Process locked */
__HAL_LOCK(hcan);
-
- if(hcan->State == HAL_CAN_STATE_BUSY_TX)
+
+ /* Check if CAN state is not busy for RX FIFO0 */
+ if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
{
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ return HAL_BUSY;
}
- else
+
+ /* Check if CAN state is not busy for RX FIFO1 */
+ if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
{
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_RX;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ return HAL_BUSY;
}
-
+
+ /* Change CAN state */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ }
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ }
+ }
+
/* Get tick */
tickstart = HAL_GetTick();
@@ -812,38 +887,51 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u
if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
{
hcan->State = HAL_CAN_STATE_TIMEOUT;
+
/* Process unlocked */
__HAL_UNLOCK(hcan);
+
return HAL_TIMEOUT;
}
}
}
-
+
+ /* Set RxMsg pointer */
+ if(FIFONumber == CAN_FIFO0)
+ {
+ pRxMsg = hcan->pRxMsg;
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ pRxMsg = hcan->pRx1Msg;
+ }
+
/* Get the Id */
- hcan->pRxMsg->IDE = (uint8_t)0x04U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
- if (hcan->pRxMsg->IDE == CAN_ID_STD)
+ pRxMsg->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ if (pRxMsg->IDE == CAN_ID_STD)
{
- hcan->pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
+ pRxMsg->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_TI0R_STID_Pos;
}
else
{
- hcan->pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
+ pRxMsg->ExtId = (0xFFFFFFF8U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_EXID_Pos;
}
-
- hcan->pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ pRxMsg->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_RTR_Pos;
/* Get the DLC */
- hcan->pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
+ pRxMsg->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_DLC_Pos;
/* Get the FMI */
- hcan->pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
+ pRxMsg->FMI = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_FMI_Pos;
+ /* Get the FIFONumber */
+ pRxMsg->FIFONumber = FIFONumber;
/* Get the data field */
- hcan->pRxMsg->Data[0] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
- hcan->pRxMsg->Data[1] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
- hcan->pRxMsg->Data[2] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
- hcan->pRxMsg->Data[3] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
- hcan->pRxMsg->Data[4] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
- hcan->pRxMsg->Data[5] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
- hcan->pRxMsg->Data[6] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
- hcan->pRxMsg->Data[7] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
+ pRxMsg->Data[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA0_Pos;
+ pRxMsg->Data[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA1_Pos;
+ pRxMsg->Data[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA2_Pos;
+ pRxMsg->Data[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA3_Pos;
+ pRxMsg->Data[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA4_Pos;
+ pRxMsg->Data[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA5_Pos;
+ pRxMsg->Data[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA6_Pos;
+ pRxMsg->Data[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA7_Pos;
/* Release the FIFO */
if(FIFONumber == CAN_FIFO0)
@@ -856,16 +944,43 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u
/* Release FIFO1 */
__HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
}
-
- if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
+
+ /* Change CAN state */
+ if (FIFONumber == CAN_FIFO0)
{
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_TX;
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_RX0 */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
}
- else
+ else /* FIFONumber == CAN_FIFO1 */
{
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_READY;
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_RX1 */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
}
/* Process unlocked */
@@ -877,69 +992,108 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u
/**
* @brief Receives a correct CAN frame.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
- * @param FIFONumber: FIFO number.
+ * @param FIFONumber FIFO number.
* @retval HAL status
- * @retval None
*/
HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
{
/* Check the parameters */
assert_param(IS_CAN_FIFO(FIFONumber));
-
- if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_TX))
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Check if CAN state is not busy for RX FIFO0 */
+ if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
{
- /* Process locked */
- __HAL_LOCK(hcan);
-
- if(hcan->State == HAL_CAN_STATE_BUSY_TX)
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
- }
- else
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_RX;
- }
-
- /* Set CAN error code to none */
- hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-
- /* Enable Error warning Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);
-
- /* Enable Error passive Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);
-
- /* Enable Bus-off Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);
-
- /* Enable Last error code Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);
-
- /* Enable Error Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_BUSY;
+ }
+
+ /* Check if CAN state is not busy for RX FIFO1 */
+ if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ {
/* Process unlocked */
__HAL_UNLOCK(hcan);
- if(FIFONumber == CAN_FIFO0)
+ return HAL_BUSY;
+ }
+
+ /* Change CAN state */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ switch(hcan->State)
{
- /* Enable FIFO 0 message pending Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0);
+ case(HAL_CAN_STATE_BUSY_TX):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
}
- else
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ switch(hcan->State)
{
- /* Enable FIFO 1 message pending Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1);
+ case(HAL_CAN_STATE_BUSY_TX):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
}
-
+ }
+
+ /* Set CAN error code to none */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Enable interrupts: */
+ /* - Enable Error warning Interrupt */
+ /* - Enable Error passive Interrupt */
+ /* - Enable Bus-off Interrupt */
+ /* - Enable Last error code Interrupt */
+ /* - Enable Error Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ if(FIFONumber == CAN_FIFO0)
+ {
+ /* Enable FIFO 0 overrun and message pending Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
}
else
{
- return HAL_BUSY;
+ /* Enable FIFO 1 overrun and message pending Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
}
/* Return function status */
@@ -948,7 +1102,7 @@ HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber
/**
* @brief Enters the Sleep (low power) mode.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL status.
*/
@@ -963,10 +1117,13 @@ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
hcan->State = HAL_CAN_STATE_BUSY;
/* Request Sleep mode */
- hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
+ MODIFY_REG(hcan->Instance->MCR,
+ CAN_MCR_INRQ ,
+ CAN_MCR_SLEEP );
/* Sleep mode status */
- if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
+ if (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) ||
+ HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK) )
{
/* Process unlocked */
__HAL_UNLOCK(hcan);
@@ -979,7 +1136,8 @@ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
tickstart = HAL_GetTick();
/* Wait the acknowledge */
- while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
+ while (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) ||
+ HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK) )
{
if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
{
@@ -1003,7 +1161,7 @@ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
/**
* @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral
* is in the normal mode.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL status.
*/
@@ -1018,23 +1176,26 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
hcan->State = HAL_CAN_STATE_BUSY;
/* Wake up request */
- hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
/* Get tick */
tickstart = HAL_GetTick();
/* Sleep mode status */
- while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
+ while(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_SLAK))
{
if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
{
hcan->State= HAL_CAN_STATE_TIMEOUT;
+
/* Process unlocked */
__HAL_UNLOCK(hcan);
+
return HAL_TIMEOUT;
}
}
- if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
+
+ if(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_SLAK))
{
/* Process unlocked */
__HAL_UNLOCK(hcan);
@@ -1055,21 +1216,61 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
/**
* @brief Handles CAN interrupt request
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
{
+ uint32_t errorcode = HAL_CAN_ERROR_NONE;
+
+ /* Check Overrun flag for FIFO0 */
+ if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0)))
+ {
+ /* Set CAN error code to FOV0 error */
+ errorcode |= HAL_CAN_ERROR_FOV0;
+
+ /* Clear FIFO0 Overrun Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
+ }
+
+ /* Check Overrun flag for FIFO1 */
+ if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1)))
+ {
+ /* Set CAN error code to FOV1 error */
+ errorcode |= HAL_CAN_ERROR_FOV1;
+
+ /* Clear FIFO1 Overrun Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
+ }
+
/* Check End of transmission flag */
if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
{
+ /* Check Transmit request completion status */
if((__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0)) ||
(__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1)) ||
(__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2)))
{
- /* Call transmit function */
- CAN_Transmit_IT(hcan);
+ /* Check Transmit success */
+ if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0)) ||
+ (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1)) ||
+ (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2)))
+ {
+ /* Call transmit function */
+ CAN_Transmit_IT(hcan);
+ }
+ else /* Transmit failure */
+ {
+ /* Set CAN error code to TXFAIL error */
+ errorcode |= HAL_CAN_ERROR_TXFAIL;
+ }
+
+ /* Clear transmission status flags (RQCPx and TXOKx) */
+ SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2 | \
+ CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2);
}
}
@@ -1089,6 +1290,9 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
CAN_Receive_IT(hcan, CAN_FIFO1);
}
+ /* Set error code in handle */
+ hcan->ErrorCode |= errorcode;
+
/* Check Error Warning Flag */
if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG)) &&
(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG)) &&
@@ -1155,16 +1359,40 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
}
/* Clear Last error code Flag */
- hcan->Instance->ESR &= ~(CAN_ESR_LEC);
+ CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
}
/* Call the Error call Back in case of Errors */
if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
{
/* Clear ERRI Flag */
- hcan->Instance->MSR |= CAN_MSR_ERRI;
+ SET_BIT(hcan->Instance->MSR, CAN_MSR_ERRI);
+
/* Set the CAN state ready to be able to start again the process */
hcan->State = HAL_CAN_STATE_READY;
+
+ /* Disable interrupts: */
+ /* - Disable Error warning Interrupt */
+ /* - Disable Error passive Interrupt */
+ /* - Disable Bus-off Interrupt */
+ /* - Disable Last error code Interrupt */
+ /* - Disable Error Interrupt */
+ /* - Disable FIFO 0 message pending Interrupt */
+ /* - Disable FIFO 0 Overrun Interrupt */
+ /* - Disable FIFO 1 message pending Interrupt */
+ /* - Disable FIFO 1 Overrun Interrupt */
+ /* - Disable Transmit mailbox empty Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR |
+ CAN_IT_FMP0|
+ CAN_IT_FOV0|
+ CAN_IT_FMP1|
+ CAN_IT_FOV1|
+ CAN_IT_TME );
+
/* Call Error callback function */
HAL_CAN_ErrorCallback(hcan);
}
@@ -1172,7 +1400,7 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
/**
* @brief Transmission complete callback in non blocking mode
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
@@ -1188,7 +1416,7 @@ __weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
/**
* @brief Transmission complete callback in non blocking mode
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
@@ -1204,7 +1432,7 @@ __weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
/**
* @brief Error CAN callback.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
@@ -1240,7 +1468,7 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
/**
* @brief return the CAN state
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL state
*/
@@ -1252,7 +1480,7 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
/**
* @brief Return the CAN error code
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval CAN Error Code
*/
@@ -1277,7 +1505,7 @@ uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
/**
* @brief Initiates and transmits a CAN frame message.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL status
*/
@@ -1288,33 +1516,36 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
if(hcan->State == HAL_CAN_STATE_BUSY_TX)
{
- /* Disable Error warning Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);
-
- /* Disable Error passive Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);
-
- /* Disable Bus-off Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);
-
- /* Disable Last error code Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);
-
- /* Disable Error Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);
- }
-
- if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_RX;
+ /* Disable interrupts: */
+ /* - Disable Error warning Interrupt */
+ /* - Disable Error passive Interrupt */
+ /* - Disable Bus-off Interrupt */
+ /* - Disable Last error code Interrupt */
+ /* - Disable Error Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR );
}
- else
+
+ /* Change CAN state */
+ switch(hcan->State)
{
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_READY;
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_TX */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
}
-
+
/* Transmission complete callback */
HAL_CAN_TxCpltCallback(hcan);
@@ -1323,84 +1554,122 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
/**
* @brief Receives a correct CAN frame.
- * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains
+ * @param hcan Pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
- * @param FIFONumber: Specify the FIFO number
+ * @param FIFONumber Specify the FIFO number
* @retval HAL status
* @retval None
*/
static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
{
+ CanRxMsgTypeDef* pRxMsg = NULL;
+
+ /* Set RxMsg pointer */
+ if(FIFONumber == CAN_FIFO0)
+ {
+ pRxMsg = hcan->pRxMsg;
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ pRxMsg = hcan->pRx1Msg;
+ }
+
/* Get the Id */
- hcan->pRxMsg->IDE = (uint8_t)0x04U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
- if (hcan->pRxMsg->IDE == CAN_ID_STD)
+ pRxMsg->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ if (pRxMsg->IDE == CAN_ID_STD)
{
- hcan->pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
+ pRxMsg->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_TI0R_STID_Pos;
}
else
{
- hcan->pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
+ pRxMsg->ExtId = (0xFFFFFFF8U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_EXID_Pos;
}
-
- hcan->pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ pRxMsg->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[FIFONumber].RIR) >> CAN_RI0R_RTR_Pos;
/* Get the DLC */
- hcan->pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
+ pRxMsg->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_DLC_Pos;
/* Get the FMI */
- hcan->pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
+ pRxMsg->FMI = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR) >> CAN_RDT0R_FMI_Pos;
+ /* Get the FIFONumber */
+ pRxMsg->FIFONumber = FIFONumber;
/* Get the data field */
- hcan->pRxMsg->Data[0] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
- hcan->pRxMsg->Data[1] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
- hcan->pRxMsg->Data[2] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
- hcan->pRxMsg->Data[3] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
- hcan->pRxMsg->Data[4] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
- hcan->pRxMsg->Data[5] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
- hcan->pRxMsg->Data[6] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
- hcan->pRxMsg->Data[7] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
+ pRxMsg->Data[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA0_Pos;
+ pRxMsg->Data[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA1_Pos;
+ pRxMsg->Data[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA2_Pos;
+ pRxMsg->Data[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR) >> CAN_RDL0R_DATA3_Pos;
+ pRxMsg->Data[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA4_Pos;
+ pRxMsg->Data[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA5_Pos;
+ pRxMsg->Data[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA6_Pos;
+ pRxMsg->Data[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR) >> CAN_RDH0R_DATA7_Pos;
+
/* Release the FIFO */
/* Release FIFO0 */
if (FIFONumber == CAN_FIFO0)
{
__HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
- /* Disable FIFO 0 message pending Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0);
+ /* Disable FIFO 0 overrun and message pending Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
}
/* Release FIFO1 */
else /* FIFONumber == CAN_FIFO1 */
{
__HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
- /* Disable FIFO 1 message pending Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1);
+ /* Disable FIFO 1 overrun and message pending Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
}
- if(hcan->State == HAL_CAN_STATE_BUSY_RX)
+ if((hcan->State == HAL_CAN_STATE_BUSY_RX0) || (hcan->State == HAL_CAN_STATE_BUSY_RX1))
{
- /* Disable Error warning Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);
-
- /* Disable Error passive Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);
-
- /* Disable Bus-off Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);
-
- /* Disable Last error code Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);
-
- /* Disable Error Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);
+ /* Disable interrupts: */
+ /* - Disable Error warning Interrupt */
+ /* - Disable Error passive Interrupt */
+ /* - Disable Bus-off Interrupt */
+ /* - Disable Last error code Interrupt */
+ /* - Disable Error Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR );
}
-
- if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
+
+ /* Change CAN state */
+ if (FIFONumber == CAN_FIFO0)
{
- /* Disable CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_TX;
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_RX0 */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
}
- else
+ else /* FIFONumber == CAN_FIFO1 */
{
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_READY;
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_RX1 */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
}
/* Receive complete callback */
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cec.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cec.c
index 4efb0b652f..df7b243e03 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cec.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cec.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_cec.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief CEC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the High Definition Multimedia Interface
@@ -142,7 +140,7 @@
/**
* @brief Initializes the CEC mode according to the specified
* parameters in the CEC_InitTypeDef and creates the associated handle .
- * @param hcec: CEC handle
+ * @param hcec CEC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
@@ -212,7 +210,7 @@ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
/**
* @brief DeInitializes the CEC peripheral
- * @param hcec: CEC handle
+ * @param hcec CEC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
@@ -265,8 +263,8 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
/**
* @brief Initializes the Own Address of the CEC device
- * @param hcec: CEC handle
- * @param CEC_OwnAddress: The CEC own address.
+ * @param hcec CEC handle
+ * @param CEC_OwnAddress The CEC own address.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
@@ -312,7 +310,7 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC
/**
* @brief CEC MSP Init
- * @param hcec: CEC handle
+ * @param hcec CEC handle
* @retval None
*/
__weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
@@ -326,7 +324,7 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC
/**
* @brief CEC MSP DeInit
- * @param hcec: CEC handle
+ * @param hcec CEC handle
* @retval None
*/
__weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
@@ -378,11 +376,11 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC
/**
* @brief Send data in interrupt mode
- * @param hcec: CEC handle
- * @param InitiatorAddress: Initiator address
- * @param DestinationAddress: destination logical address
- * @param pData: pointer to input byte data buffer
- * @param Size: amount of data to be sent in bytes (without counting the header).
+ * @param hcec CEC handle
+ * @param InitiatorAddress Initiator address
+ * @param DestinationAddress destination logical address
+ * @param pData pointer to input byte data buffer
+ * @param Size amount of data to be sent in bytes (without counting the header).
* 0 means only the header is sent (ping operation).
* Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
* @retval HAL status
@@ -438,7 +436,7 @@ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t Initiator
/**
* @brief Get size of the received frame.
- * @param hcec: CEC handle
+ * @param hcec CEC handle
* @retval Frame size
*/
uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec)
@@ -448,8 +446,8 @@ uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec)
/**
* @brief Change Rx Buffer.
- * @param hcec: CEC handle
- * @param Rxbuffer: Rx Buffer
+ * @param hcec CEC handle
+ * @param Rxbuffer Rx Buffer
* @note This function can be called only inside the HAL_CEC_RxCpltCallback()
* @retval Frame size
*/
@@ -460,7 +458,7 @@ void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer)
/**
* @brief This function handles CEC interrupt requests.
- * @param hcec: CEC handle
+ * @param hcec CEC handle
* @retval None
*/
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
@@ -565,7 +563,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
/**
* @brief Tx Transfer completed callback
- * @param hcec: CEC handle
+ * @param hcec CEC handle
* @retval None
*/
__weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
@@ -579,8 +577,8 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
/**
* @brief Rx Transfer completed callback
- * @param hcec: CEC handle
- * @param RxFrameSize: Size of frame
+ * @param hcec CEC handle
+ * @param RxFrameSize Size of frame
* @retval None
*/
__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
@@ -595,7 +593,7 @@ __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize
/**
* @brief CEC error callbacks
- * @param hcec: CEC handle
+ * @param hcec CEC handle
* @retval None
*/
__weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
@@ -626,7 +624,7 @@ __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize
*/
/**
* @brief return the CEC state
- * @param hcec: pointer to a CEC_HandleTypeDef structure that contains
+ * @param hcec pointer to a CEC_HandleTypeDef structure that contains
* the configuration information for the specified CEC module.
* @retval HAL state
*/
@@ -641,7 +639,7 @@ HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
/**
* @brief Return the CEC error code
- * @param hcec : pointer to a CEC_HandleTypeDef structure that contains
+ * @param hcec pointer to a CEC_HandleTypeDef structure that contains
* the configuration information for the specified CEC.
* @retval CEC Error Code
*/
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_comp.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_comp.c
index 32c44ce16d..4727519150 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_comp.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_comp.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_comp.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief COMP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the COMP peripheral:
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c
index dafafd53ff..38080d5302 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_cortex.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:
@@ -168,7 +166,7 @@
/**
* @brief Sets the priority grouping field (pre-emption priority and subpriority)
* using the required unlock sequence.
- * @param PriorityGroup: The priority grouping bits length.
+ * @param PriorityGroup The priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
* 4 bits for subpriority
@@ -195,13 +193,13 @@ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
/**
* @brief Sets the priority of an interrupt.
- * @param IRQn: External interrupt number
+ * @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
- * @param PreemptPriority: The pre-emption priority for the IRQn channel.
+ * @param PreemptPriority The pre-emption priority for the IRQn channel.
* This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table
* A lower priority value indicates a higher priority
- * @param SubPriority: the subpriority level for the IRQ channel.
+ * @param SubPriority the subpriority level for the IRQ channel.
* This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table
* A lower priority value indicates a higher priority.
* @retval None
@@ -266,7 +264,7 @@ void HAL_NVIC_SystemReset(void)
/**
* @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
* Counter is in free running mode to generate periodic interrupts.
- * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
+ * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
@@ -311,7 +309,7 @@ void HAL_MPU_Disable(void)
/**
* @brief Enables the MPU
- * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
+ * @param MPU_Control Specifies the control mode of the MPU during hard fault,
* NMI, FAULTMASK and privileged access to the default memory
* This parameter can be one of the following values:
* @arg MPU_HFNMI_PRIVDEF_NONE
@@ -331,7 +329,7 @@ void HAL_MPU_Enable(uint32_t MPU_Control)
/**
* @brief Initializes and configures the Region and the memory to be protected.
- * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
+ * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
* the initialization and configuration information.
* @retval None
*/
@@ -387,7 +385,7 @@ uint32_t HAL_NVIC_GetPriorityGrouping(void)
/**
* @brief Gets the priority of an interrupt.
- * @param IRQn: External interrupt number
+ * @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
* @param PriorityGroup: the priority grouping bits length.
@@ -402,8 +400,8 @@ uint32_t HAL_NVIC_GetPriorityGrouping(void)
* 1 bits for subpriority
* @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
* 0 bits for subpriority
- * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
- * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
+ * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
+ * @param pSubPriority Pointer on the Subpriority value (starting from 0).
* @retval None
*/
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
@@ -471,7 +469,7 @@ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
/**
* @brief Configures the SysTick clock source.
- * @param CLKSource: specifies the SysTick clock source.
+ * @param CLKSource specifies the SysTick clock source.
* This parameter can be one of the following values:
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_crc.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_crc.c
index d0755e5604..061a9d5080 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_crc.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_crc.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_crc.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief CRC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:
@@ -115,7 +113,7 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3
/**
* @brief Initialize the CRC according to the specified
* parameters in the CRC_InitTypeDef and initialize the associated handle.
- * @param hcrc: CRC handle
+ * @param hcrc CRC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
@@ -192,7 +190,7 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
/**
* @brief DeInitialize the CRC peripheral.
- * @param hcrc: CRC handle
+ * @param hcrc CRC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
@@ -236,7 +234,7 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
/**
* @brief Initializes the CRC MSP.
- * @param hcrc: CRC handle
+ * @param hcrc CRC handle
* @retval None
*/
__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
@@ -251,7 +249,7 @@ __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
/**
* @brief DeInitialize the CRC MSP.
- * @param hcrc: CRC handle
+ * @param hcrc CRC handle
* @retval None
*/
__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
@@ -291,10 +289,10 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
/**
* @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
* starting with the previously computed CRC as initialization value.
- * @param hcrc: CRC handle
- * @param pBuffer: pointer to the input data buffer, exact input data format is
+ * @param hcrc CRC handle
+ * @param pBuffer pointer to the input data buffer, exact input data format is
* provided by hcrc->InputDataFormat.
- * @param BufferLength: input data buffer length (number of bytes if pBuffer
+ * @param BufferLength input data buffer length (number of bytes if pBuffer
* type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
* number of words if pBuffer type is * uint32_t).
* @note By default, the API expects a uint32_t pointer as input buffer parameter.
@@ -351,10 +349,10 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_
/**
* @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
* starting with hcrc->Instance->INIT as initialization value.
- * @param hcrc: CRC handle
- * @param pBuffer: pointer to the input data buffer, exact input data format is
+ * @param hcrc CRC handle
+ * @param pBuffer pointer to the input data buffer, exact input data format is
* provided by hcrc->InputDataFormat.
- * @param BufferLength: input data buffer length (number of bytes if pBuffer
+ * @param BufferLength input data buffer length (number of bytes if pBuffer
* type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
* number of words if pBuffer type is * uint32_t).
* @note By default, the API expects a uint32_t pointer as input buffer parameter.
@@ -433,7 +431,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
/**
* @brief Return the CRC handle state.
- * @param hcrc: CRC handle
+ * @param hcrc CRC handle
* @retval HAL state
*/
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
@@ -457,9 +455,9 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
/**
* @brief Enter 8-bit input data to the CRC calculator.
* Specific data handling to optimize processing time.
- * @param hcrc: CRC handle
- * @param pBuffer: pointer to the input data buffer
- * @param BufferLength: input data buffer length
+ * @param hcrc CRC handle
+ * @param pBuffer pointer to the input data buffer
+ * @param BufferLength input data buffer length
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
@@ -500,9 +498,9 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_
/**
* @brief Enter 16-bit input data to the CRC calculator.
* Specific data handling to optimize processing time.
- * @param hcrc: CRC handle
- * @param pBuffer: pointer to the input data buffer
- * @param BufferLength: input data buffer length
+ * @param hcrc CRC handle
+ * @param pBuffer pointer to the input data buffer
+ * @param BufferLength input data buffer length
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_crc_ex.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_crc_ex.c
index 9998c80bd8..29fbeac01f 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_crc_ex.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_crc_ex.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_crc_ex.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief Extended CRC HAL module driver.
* This file provides firmware functions to manage the extended
* functionalities of the CRC peripheral.
@@ -91,12 +89,12 @@
/**
* @brief Initialize the CRC polynomial if different from default one.
- * @param hcrc: CRC handle
- * @param Pol: CRC generating polynomial (7, 8, 16 or 32-bit long).
+ * @param hcrc CRC handle
+ * @param Pol CRC generating polynomial (7, 8, 16 or 32-bit long).
* This parameter is written in normal representation, e.g.
* @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
* @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
- * @param PolyLength: CRC polynomial length.
+ * @param PolyLength CRC polynomial length.
* This parameter can be one of the following values:
* @arg CRC_POLYLENGTH_7B: 7-bit long CRC (generating polynomial of degree 7)
* @arg CRC_POLYLENGTH_8B: 8-bit long CRC (generating polynomial of degree 8)
@@ -159,8 +157,8 @@ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol
/**
* @brief Set the Reverse Input data mode.
- * @param hcrc: CRC handle
- * @param InputReverseMode: Input Data inversion mode.
+ * @param hcrc CRC handle
+ * @param InputReverseMode Input Data inversion mode.
* This parameter can be one of the following values:
* @arg CRC_INPUTDATA_NOINVERSION: no change in bit order (default value)
* @arg CRC_INPUTDATA_INVERSION_BYTE: Byte-wise bit reversal
@@ -187,8 +185,8 @@ HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t
/**
* @brief Set the Reverse Output data mode.
- * @param hcrc: CRC handle
- * @param OutputReverseMode: Output Data inversion mode.
+ * @param hcrc CRC handle
+ * @param OutputReverseMode Output Data inversion mode.
* This parameter can be one of the following values:
* @arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion (default value)
* @arg CRC_OUTPUTDATA_INVERSION_ENABLE: bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dac.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dac.c
index aa5e22feaa..a98fee31e2 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dac.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dac.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_dac.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Digital to Analog Converter (DAC) peripheral:
@@ -274,7 +272,7 @@
/**
* @brief Initialize the DAC peripheral according to the specified parameters
* in the DAC_InitStruct and initialize the associated handle.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval HAL status
*/
@@ -312,7 +310,7 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
/**
* @brief Deinitialize the DAC peripheral registers to their default reset values.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval HAL status
*/
@@ -348,7 +346,7 @@ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
/**
* @brief Initialize the DAC MSP.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
@@ -364,7 +362,7 @@ __weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
/**
* @brief DeInitialize the DAC MSP.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
@@ -403,9 +401,9 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
/**
* @brief Enables DAC and starts conversion of channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
- * @param Channel: The selected DAC channel.
+ * @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC1 Channel1 selected
* @arg DAC_CHANNEL_2: DAC1 Channel2 selected
@@ -427,9 +425,9 @@ __weak HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel
/**
* @brief Disables DAC and stop conversion of channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
- * @param Channel: The selected DAC channel.
+ * @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC1 Channel1 selected
* @arg DAC_CHANNEL_2: DAC1 Channel2 selected
@@ -453,9 +451,9 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
/**
* @brief Disables DAC and stop conversion of channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
- * @param Channel: The selected DAC channel.
+ * @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC1 Channel1 selected
* @arg DAC_CHANNEL_2: DAC1 Channel2 selected
@@ -520,9 +518,9 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
/**
* @brief Returns the last data output value of the selected DAC channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
- * @param Channel: The selected DAC channel.
+ * @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC1 Channel1 selected
* @arg DAC_CHANNEL_2: DAC1 Channel2 selected
@@ -544,7 +542,7 @@ __weak uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
/**
* @brief Returns the last data output value of the selected DAC channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval The selected DAC channel data output value.
*/
@@ -584,10 +582,10 @@ __weak uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
/**
* @brief Configures the selected DAC channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
- * @param sConfig: DAC configuration structure.
- * @param Channel: The selected DAC channel.
+ * @param sConfig DAC configuration structure.
+ * @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC1 Channel1 selected
* @arg DAC_CHANNEL_2: DAC1 Channel2 selected
@@ -659,7 +657,7 @@ __weak HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_
/**
* @brief return the DAC handle state
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval HAL state
*/
@@ -671,7 +669,7 @@ HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
/**
* @brief Return the DAC error code
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval DAC Error Code
*/
@@ -690,7 +688,7 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
/**
* @brief Conversion complete callback in non blocking mode for Channel1
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
@@ -706,7 +704,7 @@ __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
/**
* @brief Conversion half DMA transfer callback in non blocking mode for Channel1
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
@@ -722,7 +720,7 @@ __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
/**
* @brief Error DAC callback for Channel1.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
@@ -739,7 +737,7 @@ __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
/**
* @brief DMA underrun DAC callback for Channel1.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dac_ex.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dac_ex.c
index a7f4787fcc..6efa4006c7 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dac_ex.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dac_ex.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_dac_ex.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief DACEx HAL module driver.
* This file provides firmware functions to manage the extended
* functionalities of the DAC peripheral.
@@ -116,15 +114,15 @@ static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
/**
* @brief Set the specified data holding register value for DAC channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
- * @param Channel: The selected DAC channel.
- * @param Alignment: Specifies the data alignment for DAC channel.
+ * @param Channel The selected DAC channel.
+ * @param Alignment Specifies the data alignment for DAC channel.
* This parameter can be one of the following values:
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
- * @param Data: Data to be loaded in the selected data holding register.
+ * @param Data Data to be loaded in the selected data holding register.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
@@ -172,9 +170,9 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, ui
/* DAC channel 2 is present in DAC 1U */
/**
* @brief Set the specified data holding register value for dual DAC channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
- * @param Alignment: Specifies the data alignment for dual channel DAC.
+ * @param Alignment Specifies the data alignment for dual channel DAC.
* This parameter can be one of the following values:
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
@@ -249,9 +247,9 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Align
/* DAC 1 has 2 channels 1U & 2U - DAC 2 has one channel 1U */
/**
* @brief Enables DAC and starts conversion of channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
- * @param Channel: The selected DAC channel.
+ * @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC1 Channel1 or DAC2 Channel1 selected
* @arg DAC_CHANNEL_2: DAC1 Channel2 selected
@@ -310,9 +308,9 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
/* DAC 1 has 1 channels 1U */
/**
* @brief Enables DAC and starts conversion of channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
- * @param Channel: The selected DAC channel.
+ * @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC1 Channel1 selected
* @retval HAL status
@@ -360,15 +358,15 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
/* DAC 1 has 2 channels 1U & 2U */
/**
* @brief Enables DAC and starts conversion of channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
- * @param Channel: The selected DAC channel.
+ * @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC1 Channel1 selected
* @arg DAC_CHANNEL_2: DAC1 Channel2 selected
- * @param pData: The destination peripheral Buffer address.
- * @param Length: The length of data to be transferred from memory to DAC peripheral
- * @param Alignment: Specifies the data alignment for DAC channel.
+ * @param pData The destination peripheral Buffer address.
+ * @param Length The length of data to be transferred from memory to DAC peripheral
+ * @param Alignment Specifies the data alignment for DAC channel.
* This parameter can be one of the following values:
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
@@ -494,14 +492,14 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u
/* DAC 1 has 1 channel (channel 1U) */
/**
* @brief Enables DAC and starts conversion of channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
- * @param Channel: The selected DAC channel.
+ * @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC1 Channel1 selected
- * @param pData: The destination peripheral Buffer address.
- * @param Length: The length of data to be transferred from memory to DAC peripheral
- * @param Alignment: Specifies the data alignment for DAC channel.
+ * @param pData The destination peripheral Buffer address.
+ * @param Length The length of data to be transferred from memory to DAC peripheral
+ * @param Alignment Specifies the data alignment for DAC channel.
* This parameter can be one of the following values:
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
@@ -581,9 +579,9 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u
/* DAC 1 has 2 channels 1U & 2U */
/**
* @brief Returns the last data output value of the selected DAC channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
- * @param Channel: The selected DAC channel.
+ * @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC1 Channel1 selected
* @arg DAC_CHANNEL_2: DAC1 Channel2 selected
@@ -615,9 +613,9 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
/* DAC 1 has 1 channel (channel 1U) */
/**
* @brief Returns the last data output value of the selected DAC channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
- * @param channel: The selected DAC channel.
+ * @param channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC1 Channel1 selected
* @retval The selected DAC channel data output value.
@@ -636,7 +634,7 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
/**
* @brief Return the last data output value of the selected DAC channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval The selected DAC channel data output value.
*/
@@ -670,7 +668,7 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
* @brief Handles DAC interrupt request
* This function uses the interruption of DMA
* underrun.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
@@ -733,7 +731,7 @@ void HAL_DAC_IRQHandler(struct __DAC_HandleTypeDef* hdac)
* @brief Handles DAC interrupt request
* This function uses the interruption of DMA
* underrun.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
@@ -767,10 +765,10 @@ void HAL_DAC_IRQHandler(struct __DAC_HandleTypeDef* hdac)
/**
* @brief Configures the selected DAC channel.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
- * @param sConfig: DAC configuration structure.
- * @param Channel: The selected DAC channel.
+ * @param sConfig DAC configuration structure.
+ * @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC1 Channel1 selected
* @arg DAC_CHANNEL_2: DAC1 Channel2 selected
@@ -854,13 +852,13 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf
/**
* @brief Enables or disables the selected DAC channel wave generation.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
- * @param Channel: The selected DAC channel.
+ * @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC1 Channel1 selected
* @arg DAC_CHANNEL_2: DAC1 Channel2 selected
- * @param Amplitude: Select max triangle amplitude.
+ * @param Amplitude Select max triangle amplitude.
* This parameter can be one of the following values:
* @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
* @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
@@ -904,13 +902,13 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32
/**
* @brief Enables or disables the selected DAC channel wave generation.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
- * @param Channel: The selected DAC channel.
+ * @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC1 Channel1 selected
* @arg DAC_CHANNEL_2: DAC1 Channel2 selected
- * @param Amplitude: Unmask DAC channel LFSR for noise wave generation.
+ * @param Amplitude Unmask DAC channel LFSR for noise wave generation.
* This parameter can be one of the following values:
* @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
* @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
@@ -958,7 +956,7 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t
/* DAC channel 2 is available on top of DAC channel 1U */
/**
* @brief Conversion complete callback in non blocking mode for Channel2
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
@@ -974,7 +972,7 @@ __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
/**
* @brief Conversion half DMA transfer callback in non blocking mode for Channel2
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
@@ -990,7 +988,7 @@ __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
/**
* @brief Error DAC callback for Channel2.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
@@ -1006,7 +1004,7 @@ __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
/**
* @brief DMA underrun DAC callback for channel2.
- * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
+ * @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
@@ -1041,7 +1039,7 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
/**
* @brief DMA conversion complete callback.
- * @param hdma: pointer to DMA handle.
+ * @param hdma pointer to DMA handle.
* @retval None
*/
static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
@@ -1055,7 +1053,7 @@ static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
/**
* @brief DMA half transfer complete callback.
- * @param hdma: pointer to DMA handle.
+ * @param hdma pointer to DMA handle.
* @retval None
*/
static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
@@ -1067,7 +1065,7 @@ static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
/**
* @brief DMA error callback
- * @param hdma: pointer to DMA handle.
+ * @param hdma pointer to DMA handle.
* @retval None
*/
static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
@@ -1089,7 +1087,7 @@ static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
/* DAC channel 2 is available on top of DAC channel 1U */
/**
* @brief DMA conversion complete callback.
- * @param hdma: pointer to DMA handle.
+ * @param hdma pointer to DMA handle.
* @retval None
*/
static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
@@ -1103,7 +1101,7 @@ static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
/**
* @brief DMA half transfer complete callback.
- * @param hdma: pointer to DMA handle.
+ * @param hdma pointer to DMA handle.
* @retval None
*/
static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
@@ -1115,7 +1113,7 @@ static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
/**
* @brief DMA error callback
- * @param hdma: pointer to DMA handle.
+ * @param hdma pointer to DMA handle.
* @retval None
*/
static void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c
index d3186af82d..69e42aa981 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_dma.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief DMA HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -148,7 +146,7 @@ static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
/**
* @brief Initialize the DMA according to the specified
* parameters in the DMA_InitTypeDef and initialize the associated handle.
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
@@ -216,7 +214,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
/**
* @brief DeInitialize the DMA peripheral
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
@@ -291,9 +289,9 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
* @brief Start the DMA Transfer.
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
- * @param SrcAddress: The source memory Buffer address
- * @param DstAddress: The destination memory Buffer address
- * @param DataLength: The length of data to be transferred from source to destination
+ * @param SrcAddress The source memory Buffer address
+ * @param DstAddress The destination memory Buffer address
+ * @param DataLength The length of data to be transferred from source to destination
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
@@ -336,11 +334,11 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui
/**
* @brief Start the DMA Transfer with interrupt enabled.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
- * @param SrcAddress: The source memory Buffer address
- * @param DstAddress: The destination memory Buffer address
- * @param DataLength: The length of data to be transferred from source to destination
+ * @param SrcAddress The source memory Buffer address
+ * @param DstAddress The destination memory Buffer address
+ * @param DataLength The length of data to be transferred from source to destination
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
@@ -465,10 +463,10 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
/**
* @brief Polling for transfer complete.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
- * @param CompleteLevel: Specifies the DMA level complete.
- * @param Timeout: Timeout duration.
+ * @param CompleteLevel Specifies the DMA level complete.
+ * @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
@@ -568,7 +566,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
/**
* @brief Handle DMA interrupt request.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval None
*/
@@ -656,11 +654,11 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
/**
* @brief Register callbacks
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
- * @param CallbackID: User Callback identifer
+ * @param CallbackID User Callback identifer
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
- * @param pCallback: pointer to private callback function which has pointer to
+ * @param pCallback pointer to private callback function which has pointer to
* a DMA_HandleTypeDef structure as parameter.
* @retval HAL status
*/
@@ -709,9 +707,9 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call
/**
* @brief UnRegister callbacks
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
- * @param CallbackID: User Callback identifer
+ * @param CallbackID User Callback identifer
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
* @retval HAL status
*/
@@ -787,7 +785,7 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca
/**
* @brief Returns the DMA state.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL state
*/
@@ -798,7 +796,7 @@ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
/**
* @brief Return the DMA error code
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval DMA Error Code
*/
@@ -821,11 +819,11 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
/**
* @brief Set the DMA Transfer parameters.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
- * @param SrcAddress: The source memory Buffer address
- * @param DstAddress: The destination memory Buffer address
- * @param DataLength: The length of data to be transferred from source to destination
+ * @param SrcAddress The source memory Buffer address
+ * @param DstAddress The destination memory Buffer address
+ * @param DataLength The length of data to be transferred from source to destination
* @retval HAL status
*/
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
@@ -858,7 +856,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
/**
* @brief Set the DMA base address and channel index depending on DMA instance
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval None
*/
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c
index f7c40cb79d..5762694e32 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_flash.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
@@ -437,7 +435,7 @@ void HAL_FLASH_IRQHandler(void)
/**
* @brief FLASH end of operation interrupt callback
- * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
+ * @param ReturnValue The value saved in this parameter depends on the ongoing procedure
* - Mass Erase: No return value expected
* - Pages Erase: Address of the page which has been erased
* (if 0xFFFFFFFF, it means that all the selected pages have been erased)
@@ -456,7 +454,7 @@ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
/**
* @brief FLASH operation error interrupt callback
- * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
+ * @param ReturnValue The value saved in this parameter depends on the ongoing procedure
* - Mass Erase: No return value expected
* - Pages Erase: Address of the page which returned an error
* - Program: Address which was selected for data program
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c
index 8484bc40dd..211ec0cc04 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_flash_ex.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief Extended FLASH HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -912,7 +910,6 @@ static uint32_t FLASH_OB_GetWRP(void)
*/
static uint32_t FLASH_OB_GetRDP(void)
{
- uint32_t readstatus = OB_RDP_LEVEL_0;
uint32_t tmp_reg = 0U;
/* Read RDP level bits */
@@ -930,7 +927,7 @@ static uint32_t FLASH_OB_GetRDP(void)
if (tmp_reg == FLASH_OBR_LEVEL1_PROT)
#endif /* FLASH_OBR_LEVEL1_PROT */
{
- readstatus = OB_RDP_LEVEL_1;
+ return OB_RDP_LEVEL_1;
}
#if defined(FLASH_OBR_RDPRT)
else if (tmp_reg == FLASH_OBR_RDPRT_2)
@@ -938,14 +935,12 @@ static uint32_t FLASH_OB_GetRDP(void)
else if (tmp_reg == FLASH_OBR_LEVEL2_PROT)
#endif
{
- readstatus = OB_RDP_LEVEL_2;
+ return OB_RDP_LEVEL_2;
}
else
{
- readstatus = OB_RDP_LEVEL_0;
+ return OB_RDP_LEVEL_0;
}
-
- return readstatus;
}
/**
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c
index 575493d448..d935fcd7cc 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_gpio.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
@@ -182,8 +180,8 @@
/**
* @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
- * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family devices
- * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
+ * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family devices
+ * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
@@ -307,8 +305,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
/**
* @brief De-initialize the GPIOx peripheral registers to their default reset values.
- * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F30X device or STM32F37X device
- * @param GPIO_Pin: specifies the port bit to be written.
+ * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F30X device or STM32F37X device
+ * @param GPIO_Pin specifies the port bit to be written.
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
* @retval None
*/
@@ -389,8 +387,8 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
/**
* @brief Read the specified input port pin.
- * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family
- * @param GPIO_Pin: specifies the port bit to read.
+ * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family
+ * @param GPIO_Pin specifies the port bit to read.
* This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
@@ -419,10 +417,10 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
* accesses. In this way, there is no risk of an IRQ occurring between
* the read and the modify access.
*
- * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family
- * @param GPIO_Pin: specifies the port bit to be written.
+ * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family
+ * @param GPIO_Pin specifies the port bit to be written.
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
- * @param PinState: specifies the value to be written to the selected bit.
+ * @param PinState specifies the value to be written to the selected bit.
* This parameter can be one of the GPIO_PinState enum values:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
@@ -446,8 +444,8 @@ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin
/**
* @brief Toggle the specified GPIO pin.
- * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family
- * @param GPIO_Pin: specifies the pin to be toggled.
+ * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family
+ * @param GPIO_Pin specifies the pin to be toggled.
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
@@ -464,8 +462,8 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
* @note The configuration of the locked GPIO pins can no longer be modified
* until the next reset.
- * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family
- * @param GPIO_Pin: specifies the port bits to be locked.
+ * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family
+ * @param GPIO_Pin specifies the port bits to be locked.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
*/
@@ -500,7 +498,7 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
/**
* @brief Handle EXTI interrupt request.
- * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
+ * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
@@ -515,7 +513,7 @@ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
/**
* @brief EXTI line detection callback.
- * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
+ * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
* @retval None
*/
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_hrtim.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_hrtim.c
index ed53f9e58f..6292c3097a 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_hrtim.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_hrtim.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_hrtim.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the High Resolution Timer (HRTIM) peripheral:
@@ -472,7 +470,7 @@ static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma);
/**
* @brief Initializes a HRTIM instance
- * @param hhrtim: pointer to HAL HRTIM handle
+ * @param hhrtim pointer to HAL HRTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim)
@@ -574,7 +572,7 @@ HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim)
/**
* @brief De-initializes a HRTIM instance
- * @param hhrtim: pointer to HAL HRTIM handle
+ * @param hhrtim pointer to HAL HRTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef * hhrtim)
@@ -601,7 +599,7 @@ HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef * hhrtim)
/**
* @brief MSP initialization for a HRTIM instance
- * @param hhrtim: pointer to HAL HRTIM handle
+ * @param hhrtim pointer to HAL HRTIM handle
* @retval None
*/
__weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim)
@@ -616,7 +614,7 @@ __weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim)
/**
* @brief MSP de-initialization for a for a HRTIM instance
- * @param hhrtim: pointer to HAL HRTIM handle
+ * @param hhrtim pointer to HAL HRTIM handle
* @retval None
*/
__weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim)
@@ -631,8 +629,8 @@ __weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim)
/**
* @brief Starts the DLL calibration
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param CalibrationRate: DLL calibration period
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param CalibrationRate DLL calibration period
* This parameter can be one of the following values:
* @arg HRTIM_SINGLE_CALIBRATION: One shot DLL calibration
* @arg HRTIM_CALIBRATIONRATE_7300: Periodic DLL calibration. T=7.3 ms
@@ -682,8 +680,8 @@ HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Starts the DLL calibration.
* DLL ready interrupt is enabled
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param CalibrationRate: DLL calibration period
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param CalibrationRate DLL calibration period
* This parameter can be one of the following values:
* @arg HRTIM_SINGLE_CALIBRATION: One shot DLL calibration
* @arg HRTIM_CALIBRATIONRATE_7300: Periodic DLL calibration. T=7.3 ms
@@ -739,8 +737,8 @@ HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Polls the DLL calibration ready flag and returns when the flag is
* set (DLL calibration completed) or upon timeout expiration
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Timeout: Timeout duration in millisecond
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Timeout Timeout duration in millisecond
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef * hhrtim,
@@ -774,8 +772,8 @@ HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Configures the time base unit of a timer
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_MASTER for master timer
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
@@ -783,7 +781,7 @@ HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef * hhrtim,
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param pTimeBaseCfg: pointer to the time base configuration structure
+ * @param pTimeBaseCfg pointer to the time base configuration structure
* @note This function must be called prior starting the timer
* @note The time-base unit initialization parameters specify:
* The timer counter operating mode (continuous, one shot),
@@ -852,8 +850,8 @@ HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
/**
* @brief Starts the counter of a timer operating in simple time base mode.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index.
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index.
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_MASTER for master timer
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
@@ -887,8 +885,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Stops the counter of a timer operating in simple time base mode.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index.
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index.
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_MASTER for master timer
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
@@ -923,8 +921,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Starts the counter of a timer operating in simple time base mode
* (Timer repetition interrupt is enabled).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index.
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index.
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_MASTER for master timer
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
@@ -969,8 +967,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Stops the counter of a timer operating in simple time base mode
* (Timer repetition interrupt is disabled).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index.
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index.
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_MASTER for master timer
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
@@ -1015,8 +1013,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Starts the counter of a timer operating in simple time base mode
* (Timer repetition DMA request is enabled).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index.
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index.
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_MASTER for master timer
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
@@ -1024,9 +1022,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim,
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param SrcAddr: DMA transfer source address
- * @param DestAddr: DMA transfer destination address
- * @param Length: The length of data items (data size) to be transferred
+ * @param SrcAddr DMA transfer source address
+ * @param DestAddr DMA transfer destination address
+ * @param Length The length of data items (data size) to be transferred
* from source to destination
*/
HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim,
@@ -1061,7 +1059,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim,
/* Get the timer DMA handler */
hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
-
+ if (hdma == NULL)
+ {
+ hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_ERROR;
+ }
/* Set the DMA transfer completed callback */
if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
{
@@ -1096,14 +1102,14 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim,
/* Process Unlocked */
__HAL_UNLOCK(hhrtim);
- return HAL_OK;
+ return HAL_OK;
}
/**
* @brief Stops the counter of a timer operating in simple time base mode
* (Timer repetition DMA request is disabled).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index.
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index.
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_MASTER for master timer
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
@@ -1136,12 +1142,30 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim,
{
/* Get the timer DMA handler */
hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
+
+ if (hdma == NULL)
+ {
+ /* Disable the timer repetition DMA request */
+ __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
+
+ /* Disable the timer counter */
+ __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+ hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Disable the DMA */
+ HAL_DMA_Abort(hdma);
- /* Disable the DMA */
- HAL_DMA_Abort(hdma);
-
- /* Disable the timer repetition DMA request */
- __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
+ /* Disable the timer repetition DMA request */
+ __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
+ }
}
/* Disable the timer counter */
@@ -1184,15 +1208,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Configures an output in simple output compare mode
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OCChannel: Timer output
+ * @param OCChannel Timer output
* This parameter can be one of the following values:
* @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
* @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
@@ -1204,7 +1228,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim,
* @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
* @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
* @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @param pSimpleOCChannelCfg: pointer to the simple output compare output configuration structure
+ * @param pSimpleOCChannelCfg pointer to the simple output compare output configuration structure
* @note When the timer operates in simple output compare mode:
* Output 1 is implicitly controlled by the compare unit 1
* Output 2 is implicitly controlled by the compare unit 2
@@ -1337,15 +1361,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Starts the output compare signal generation on the designed timer output
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OCChannel: Timer output
+ * @param OCChannel Timer output
* This parameter can be one of the following values:
* @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
* @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
@@ -1387,15 +1411,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Stops the output compare signal generation on the designed timer output
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OCChannel: Timer output
+ * @param OCChannel Timer output
* This parameter can be one of the following values:
* @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
* @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
@@ -1438,15 +1462,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Starts the output compare signal generation on the designed timer output
* (Interrupt is enabled (see note note below)).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OCChannel: Timer output
+ * @param OCChannel Timer output
* This parameter can be one of the following values:
* @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
* @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
@@ -1501,15 +1525,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Stops the output compare signal generation on the designed timer output
* (Interrupt is disabled).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OCChannel: Timer output
+ * @param OCChannel Timer output
* This parameter can be one of the following values:
* @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
* @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
@@ -1560,15 +1584,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Starts the output compare signal generation on the designed timer output
* (DMA request is enabled (see note below)).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OCChannel: Timer output
+ * @param OCChannel Timer output
* This parameter can be one of the following values:
* @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
* @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
@@ -1580,9 +1604,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim,
* @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
* @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
* @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @param SrcAddr: DMA transfer source address
- * @param DestAddr: DMA transfer destination address
- * @param Length: The length of data items (data size) to be transferred
+ * @param SrcAddr DMA transfer source address
+ * @param DestAddr DMA transfer destination address
+ * @param Length The length of data items (data size) to be transferred
* from source to destination
* @note DMA request enabling depends on the chosen output compare mode
* Output toggle: compare match DMA request is enabled
@@ -1629,8 +1653,17 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim,
dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
/* Get the timer DMA handler */
- hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
-
+ hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
+ if (hdma == NULL)
+ {
+ hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_ERROR;
+ }
+
/* Set the DMA error callback */
hdma->XferErrorCallback = HRTIM_DMAError ;
@@ -1657,15 +1690,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Stops the output compare signal generation on the designed timer output
* (DMA request is disabled).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OCChannel: Timer output
+ * @param OCChannel Timer output
* This parameter can be one of the following values:
* @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
* @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
@@ -1699,7 +1732,16 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim,
/* Get the timer DMA handler */
hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
-
+ if (hdma == NULL)
+ {
+ hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_ERROR;
+ }
+
/* Disable the DMA */
HAL_DMA_Abort(hdma);
@@ -1751,15 +1793,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Configures an output in simple PWM mode
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param PWMChannel: Timer output
+ * @param PWMChannel Timer output
* This parameter can be one of the following values:
* @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
* @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
@@ -1771,7 +1813,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim,
* @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
* @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
* @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @param pSimplePWMChannelCfg: pointer to the simple PWM output configuration structure
+ * @param pSimplePWMChannelCfg pointer to the simple PWM output configuration structure
* @note When the timer operates in simple PWM output mode:
* Output 1 is implicitly controlled by the compare unit 1
* Output 2 is implicitly controlled by the compare unit 2
@@ -1877,15 +1919,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Starts the PWM output signal generation on the designed timer output
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param PWMChannel: Timer output
+ * @param PWMChannel Timer output
* This parameter can be one of the following values:
* @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
* @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
@@ -1927,15 +1969,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Stops the PWM output signal generation on the designed timer output
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param PWMChannel: Timer output
+ * @param PWMChannel Timer output
* This parameter can be one of the following values:
* @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
* @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
@@ -1978,15 +2020,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Starts the PWM output signal generation on the designed timer output
* (The compare interrupt is enabled).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param PWMChannel: Timer output
+ * @param PWMChannel Timer output
* This parameter can be one of the following values:
* @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
* @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
@@ -2054,15 +2096,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Stops the PWM output signal generation on the designed timer output
* (The compare interrupt is disabled).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param PWMChannel: Timer output
+ * @param PWMChannel Timer output
* This parameter can be one of the following values:
* @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
* @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
@@ -2130,15 +2172,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Starts the PWM output signal generation on the designed timer output
* (The compare DMA request is enabled).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param PWMChannel: Timer output
+ * @param PWMChannel Timer output
* This parameter can be one of the following values:
* @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
* @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
@@ -2150,9 +2192,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim,
* @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
* @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
* @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @param SrcAddr: DMA transfer source address
- * @param DestAddr: DMA transfer destination address
- * @param Length: The length of data items (data size) to be transferred
+ * @param SrcAddr DMA transfer source address
+ * @param DestAddr DMA transfer destination address
+ * @param Length The length of data items (data size) to be transferred
* from source to destination
* @retval HAL status
*/
@@ -2192,6 +2234,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim,
/* Get the timer DMA handler */
hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
+ if (hdma == NULL)
+ {
+ hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_ERROR;
+ }
/* Set the DMA error callback */
hdma->XferErrorCallback = HRTIM_DMAError ;
@@ -2241,15 +2292,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Stops the PWM output signal generation on the designed timer output
* (The compare DMA request is disabled).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param PWMChannel: Timer output
+ * @param PWMChannel Timer output
* This parameter can be one of the following values:
* @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
* @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
@@ -2282,7 +2333,16 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim,
/* Get the timer DMA handler */
hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
-
+ if (hdma == NULL)
+ {
+ hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_ERROR;
+ }
+
/* Disable the DMA */
HAL_DMA_Abort(hdma);
@@ -2350,19 +2410,19 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Configures a simple capture
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param CaptureChannel: Capture unit
+ * @param CaptureChannel Capture unit
* This parameter can be one of the following values:
* @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
* @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
- * @param pSimpleCaptureChannelCfg: pointer to the simple capture configuration structure
+ * @param pSimpleCaptureChannelCfg pointer to the simple capture configuration structure
* @note When the timer operates in simple capture mode the capture is trigerred
* by the designated external event and GPIO input is implicitly used as event source.
* The cature can be triggered by a rising edge, a falling edge or both
@@ -2423,15 +2483,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhr
/**
* @brief Enables a simple capture on the designed capture unit
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param CaptureChannel: Timer output
+ * @param CaptureChannel Timer output
* This parameter can be one of the following values:
* @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
* @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
@@ -2483,15 +2543,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Disables a simple capture on the designed capture unit
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param CaptureChannel: Timer output
+ * @param CaptureChannel Timer output
* This parameter can be one of the following values:
* @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
* @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
@@ -2545,15 +2605,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Enables a simple capture on the designed capture unit
* (Capture interrupt is enabled).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param CaptureChannel: Timer output
+ * @param CaptureChannel Timer output
* This parameter can be one of the following values:
* @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
* @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
@@ -2609,15 +2669,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Disables a simple capture on the designed capture unit
* (Capture interrupt is disabled).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param CaptureChannel: Timer output
+ * @param CaptureChannel Timer output
* This parameter can be one of the following values:
* @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
* @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
@@ -2677,21 +2737,21 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Enables a simple capture on the designed capture unit
* (Capture DMA request is enabled).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param CaptureChannel: Timer output
+ * @param CaptureChannel Timer output
* This parameter can be one of the following values:
* @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
* @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
- * @param SrcAddr: DMA transfer source address
- * @param DestAddr: DMA transfer destination address
- * @param Length: The length of data items (data size) to be transferred
+ * @param SrcAddr DMA transfer source address
+ * @param DestAddr DMA transfer destination address
+ * @param Length The length of data items (data size) to be transferred
* from source to destination
* @retval HAL status
*/
@@ -2715,7 +2775,16 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim,
/* Get the timer DMA handler */
hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
-
+ if (hdma == NULL)
+ {
+ hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_ERROR;
+ }
+
/* Set the DMA error callback */
hdma->XferErrorCallback = HRTIM_DMAError ;
@@ -2762,15 +2831,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Disables a simple capture on the designed capture unit
* (Capture DMA request is disabled).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param CaptureChannel: Timer output
+ * @param CaptureChannel Timer output
* This parameter can be one of the following values:
* @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
* @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
@@ -2793,7 +2862,16 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim,
/* Get the timer DMA handler */
hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
-
+ if (hdma == NULL)
+ {
+ hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_ERROR;
+ }
+
/* Disable the DMA */
HAL_DMA_Abort(hdma);
@@ -2862,15 +2940,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Configures an output simple one pulse mode
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OnePulseChannel: Timer output
+ * @param OnePulseChannel Timer output
* This parameter can be one of the following values:
* @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
* @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
@@ -2882,7 +2960,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim,
* @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
* @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
* @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @param pSimpleOnePulseChannelCfg: pointer to the simple one pulse output configuration structure
+ * @param pSimpleOnePulseChannelCfg pointer to the simple one pulse output configuration structure
* @note When the timer operates in simple one pulse mode:
* the timer counter is implicitly started by the reset event,
* the reset of the timer counter is triggered by the designated external event
@@ -3012,15 +3090,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hh
/**
* @brief Enables the simple one pulse signal generation on the designed output
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OnePulseChannel: Timer output
+ * @param OnePulseChannel Timer output
* This parameter can be one of the following values:
* @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
* @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
@@ -3062,15 +3140,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Disables the simple one pulse signal generation on the designed output
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OnePulseChannel: Timer output
+ * @param OnePulseChannel Timer output
* This parameter can be one of the following values:
* @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
* @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
@@ -3113,15 +3191,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Enables the simple one pulse signal generation on the designed output
* (The compare interrupt is enabled (pulse start)).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OnePulseChannel: Timer output
+ * @param OnePulseChannel Timer output
* This parameter can be one of the following values:
* @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
* @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
@@ -3189,15 +3267,15 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Disables the simple one pulse signal generation on the designed output
* (The compare interrupt is disabled).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param OnePulseChannel: Timer output
+ * @param OnePulseChannel Timer output
* This parameter can be one of the following values:
* @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
* @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
@@ -3288,8 +3366,8 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Configures the burst mode feature of the HRTIM
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param pBurstModeCfg: pointer to the burst mode configuration structure
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param pBurstModeCfg pointer to the burst mode configuration structure
* @retval HAL status
* @note This function must be called before starting the burst mode
* controller
@@ -3356,8 +3434,8 @@ HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Configures the conditioning of an external event
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Event: external event to configure
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Event external event to configure
* This parameter can be one of the following values:
* @arg HRTIM_EVENT_1: External event 1
* @arg HRTIM_EVENT_2: External event 2
@@ -3369,7 +3447,7 @@ HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim,
* @arg HRTIM_EVENT_8: External event 8
* @arg HRTIM_EVENT_9: External event 9
* @arg HRTIM_EVENT_10: External event 10
- * @param pEventCfg: pointer to the event conditioning configuration structure
+ * @param pEventCfg pointer to the event conditioning configuration structure
* @note This function must be called before starting the timer
* @retval HAL status
*/
@@ -3407,8 +3485,8 @@ HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Configures the external event conditioning block prescaler
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Prescaler: Prescaler value
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Prescaler Prescaler value
* This parameter can be one of the following values:
* @arg HRTIM_EVENTPRESCALER_DIV1: fEEVS=fHRTIM
* @arg HRTIM_EVENTPRESCALER_DIV2: fEEVS=fHRTIM / 2
@@ -3453,15 +3531,15 @@ HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Configures the conditioning of fault input
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Fault: fault input to configure
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Fault fault input to configure
* This parameter can be one of the following values:
* @arg HRTIM_FAULT_1: Fault input 1
* @arg HRTIM_FAULT_2: Fault input 2
* @arg HRTIM_FAULT_3: Fault input 3
* @arg HRTIM_FAULT_4: Fault input 4
* @arg HRTIM_FAULT_5: Fault input 5
- * @param pFaultCfg: pointer to the fault conditioning configuration structure
+ * @param pFaultCfg pointer to the fault conditioning configuration structure
* @note This function must be called before starting the timer and before
* enabling faults inputs
* @retval HAL status
@@ -3559,8 +3637,8 @@ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Configures the fault conditioning block prescaler
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Prescaler: Prescaler value
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Prescaler Prescaler value
* This parameter can be one of the following values:
* @arg HRTIM_FAULTPRESCALER_DIV1: fFLTS=fHRTIM
* @arg HRTIM_FAULTPRESCALER_DIV2: fFLTS=fHRTIM / 2
@@ -3606,15 +3684,15 @@ HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Enables or disables the HRTIMx Fault mode.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Faults: fault input(s) to enable or disable
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Faults fault input(s) to enable or disable
* This parameter can be any combination of the following values:
* @arg HRTIM_FAULT_1: Fault input 1
* @arg HRTIM_FAULT_2: Fault input 2
* @arg HRTIM_FAULT_3: Fault input 3
* @arg HRTIM_FAULT_4: Fault input 4
* @arg HRTIM_FAULT_5: Fault input 5
- * @param Enable: Fault(s) enabling
+ * @param Enable Fault(s) enabling
* This parameter can be one of the following values:
* @arg HRTIM_FAULTMODECTL_ENABLED: Fault(s) enabled
* @arg HRTIM_FAULTMODECTL_DISABLED: Fault(s) disabled
@@ -3669,14 +3747,14 @@ void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Configures both the ADC trigger register update source and the ADC
* trigger source.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param ADCTrigger: ADC trigger to configure
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param ADCTrigger ADC trigger to configure
* This parameter can be one of the following values:
* @arg HRTIM_ADCTRIGGER_1: ADC trigger 1
* @arg HRTIM_ADCTRIGGER_2: ADC trigger 2
* @arg HRTIM_ADCTRIGGER_3: ADC trigger 3
* @arg HRTIM_ADCTRIGGER_4: ADC trigger 4
- * @param pADCTriggerCfg: pointer to the ADC trigger configuration structure
+ * @param pADCTriggerCfg pointer to the ADC trigger configuration structure
* @retval HAL status
* @note This function must be called before starting the timer
*/
@@ -3800,8 +3878,8 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Configures the general behavior of a timer operating in waveform mode
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_MASTER for master timer
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
@@ -3809,7 +3887,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim,
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param pTimerCfg: pointer to the timer configuration structure
+ * @param pTimerCfg pointer to the timer configuration structure
* @note When the timer operates in waveform mode, all the features supported by
* the HRTIM are available without any limitation.
* @retval HAL status
@@ -3892,15 +3970,15 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Configures the event filtering capabilities of a timer (blanking, windowing)
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param Event: external event for which timer event filtering must be configured
+ * @param Event external event for which timer event filtering must be configured
* This parameter can be one of the following values:
* @arg HRTIM_EVENT_NONE: Reset timer event filtering configuration
* @arg HRTIM_EVENT_1: External event 1
@@ -3913,7 +3991,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim,
* @arg HRTIM_EVENT_8: External event 8
* @arg HRTIM_EVENT_9: External event 9
* @arg HRTIM_EVENT_10: External event 10
- * @param pTimerEventFilteringCfg: pointer to the timer event filtering configuration structure
+ * @param pTimerEventFilteringCfg pointer to the timer event filtering configuration structure
* @note This function must be called before starting the timer
* @retval HAL status
*/
@@ -4043,15 +4121,15 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt
/**
* @brief Configures the deadtime insertion feature for a timer
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param pDeadTimeCfg: pointer to the deadtime insertion configuration structure
+ * @param pDeadTimeCfg pointer to the deadtime insertion configuration structure
* @retval HAL status
* @note This function must be called before starting the timer
*/
@@ -4112,15 +4190,15 @@ HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Configures the chopper mode feature for a timer
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param pChopperModeCfg: pointer to the chopper mode configuration structure
+ * @param pChopperModeCfg pointer to the chopper mode configuration structure
* @retval HAL status
* @note This function must be called before configuring the timer output(s)
*/
@@ -4169,8 +4247,8 @@ HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Configures the burst DMA controller for a timer
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_MASTER for master timer
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
@@ -4178,7 +4256,7 @@ HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim,
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param RegistersToUpdate: registers to be written by DMA
+ * @param RegistersToUpdate registers to be written by DMA
* This parameter can be any combination of the following values:
* @arg HRTIM_BURSTDMA_CR: HRTIM_MCR or HRTIM_TIMxCR
* @arg HRTIM_BURSTDMA_ICR: HRTIM_MICR or HRTIM_TIMxICR
@@ -4268,8 +4346,8 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Configures the compare unit of a timer operating in waveform mode
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_MASTER for master timer
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
@@ -4277,13 +4355,13 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim,
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param CompareUnit: Compare unit to configure
+ * @param CompareUnit Compare unit to configure
* This parameter can be one of the following values:
* @arg HRTIM_COMPAREUNIT_1: Compare unit 1
* @arg HRTIM_COMPAREUNIT_2: Compare unit 2
* @arg HRTIM_COMPAREUNIT_3: Compare unit 3
* @arg HRTIM_COMPAREUNIT_4: Compare unit 4
- * @param pCompareCfg: pointer to the compare unit configuration structure
+ * @param pCompareCfg pointer to the compare unit configuration structure
* @note When auto delayed mode is required for compare unit 2 or compare unit 4,
* application has to configure separately the capture unit. Capture unit
* to configure in that case depends on the compare unit auto delayed mode
@@ -4426,19 +4504,19 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Configures the capture unit of a timer operating in waveform mode
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param CaptureUnit: Capture unit to configure
+ * @param CaptureUnit Capture unit to configure
* This parameter can be one of the following values:
* @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
* @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
- * @param pCaptureCfg: pointer to the compare unit configuration structure
+ * @param pCaptureCfg pointer to the compare unit configuration structure
* @retval HAL status
* @note This function must be called before starting the timer
*/
@@ -4487,15 +4565,15 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Configures the output of a timer operating in waveform mode
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param Output: Timer output
+ * @param Output Timer output
* This parameter can be one of the following values:
* @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
* @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
@@ -4507,7 +4585,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim,
* @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
* @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
* @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @param pOutputCfg: pointer to the timer output configuration structure
+ * @param pOutputCfg pointer to the timer output configuration structure
* @retval HAL status
* @note This function must be called before configuring the timer and after
* configuring the deadtime insertion feature (if required).
@@ -4552,15 +4630,15 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Forces the timer output to its active or inactive state
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param Output: Timer output
+ * @param Output Timer output
* This parameter can be one of the following values:
* @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
* @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
@@ -4572,7 +4650,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim,
* @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
* @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
* @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
- * @param OutputLevel: indicates whether the output is forced to its active or inactive level
+ * @param OutputLevel indicates whether the output is forced to its active or inactive level
* This parameter can be one of the following values:
* @arg HRTIM_OUTPUTLEVEL_ACTIVE: output is forced to its active level
* @arg HRTIM_OUTPUTLEVEL_INACTIVE: output is forced to its inactive level
@@ -4653,8 +4731,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Enables the generation of the waveform signal on the designated output(s)
* Outputs can be combined (ORed) to allow for simultaneous output enabling.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param OutputsToStart: Timer output(s) to enable
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param OutputsToStart Timer output(s) to enable
* This parameter can be any combination of the following values:
* @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
* @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
@@ -4693,8 +4771,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Disables the generation of the waveform signal on the designated output(s)
* Outputs can be combined (ORed) to allow for simultaneous output disabling.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param OutputsToStop: Timer output(s) to disable
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param OutputsToStop Timer output(s) to disable
* This parameter can be any combination of the following values:
* @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
* @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
@@ -4733,8 +4811,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Starts the counter of the designated timer(s) operating in waveform mode
* Timers can be combined (ORed) to allow for simultaneous counter start.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Timers: Timer counter(s) to start
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Timers Timer counter(s) to start
* This parameter can be any combination of the following values:
* @arg HRTIM_TIMERID_MASTER
* @arg HRTIM_TIMERID_TIMER_A
@@ -4769,8 +4847,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Stops the counter of the designated timer(s) operating in waveform mode
* Timers can be combined (ORed) to allow for simultaneous counter stop.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Timers: Timer counter(s) to stop
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Timers Timer counter(s) to stop
* This parameter can be any combination of the following values:
* @arg HRTIM_TIMERID_MASTER
* @arg HRTIM_TIMERID_A
@@ -4806,8 +4884,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Starts the counter of the designated timer(s) operating in waveform mode
* Timers can be combined (ORed) to allow for simultaneous counter start.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Timers: Timer counter(s) to start
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Timers Timer counter(s) to start
* This parameter can be any combination of the following values:
* @arg HRTIM_TIMERID_MASTER
* @arg HRTIM_TIMERID_A
@@ -4870,8 +4948,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_IT(HRTIM_HandleTypeDef * hhrtim
/**
* @brief Stops the counter of the designated timer(s) operating in waveform mode
* Timers can be combined (ORed) to allow for simultaneous counter stop.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Timers: Timer counter(s) to stop
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Timers Timer counter(s) to stop
* This parameter can be any combination of the following values:
* @arg HRTIM_TIMERID_MASTER
* @arg HRTIM_TIMERID_A
@@ -4939,8 +5017,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_IT(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Starts the counter of the designated timer(s) operating in waveform mode
* Timers can be combined (ORed) to allow for simultaneous counter start.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Timers: Timer counter(s) to start
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Timers Timer counter(s) to start
* This parameter can be any combination of the following values:
* HRTIM_TIMERID_MASTER
* @arg HRTIM_TIMERID_A
@@ -5003,6 +5081,15 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_DMA(HRTIM_HandleTypeDef * hhrti
{
/* Get the timer DMA handler */
hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx);
+ if (hdma == NULL)
+ {
+ hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_ERROR;
+ }
/* Set the DMA error callback */
hdma->XferErrorCallback = HRTIM_DMAError ;
@@ -5037,8 +5124,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_DMA(HRTIM_HandleTypeDef * hhrti
/**
* @brief Stops the counter of the designated timer(s) operating in waveform mode
* Timers can be combined (ORed) to allow for simultaneous counter stop.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Timers: Timer counter(s) to stop
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Timers Timer counter(s) to stop
* This parameter can be any combination of the following values:
* @arg HRTIM_TIMERID_MASTER
* @arg HRTIM_TIMERID_A
@@ -5081,6 +5168,20 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_DMA(HRTIM_HandleTypeDef * hhrtim
{
/* Get the timer DMA handler */
hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx);
+ if (hdma == NULL)
+ {
+ /* Disable the DMA request(s) */
+ __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim,
+ timer_idx,
+ hhrtim->TimerParam[timer_idx].DMARequests);
+
+ /* Disable the timer counter */
+ __HAL_HRTIM_DISABLE(hhrtim, Timers);
+
+ hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
/* Disable the DMA */
HAL_DMA_Abort(hdma);
@@ -5102,8 +5203,8 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_DMA(HRTIM_HandleTypeDef * hhrtim
/**
* @brief Enables or disables the HRTIM burst mode controller.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Enable: Burst mode controller enabling
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Enable Burst mode controller enabling
* This parameter can be one of the following values:
* @arg HRTIM_BURSTMODECTL_ENABLED: Burst mode enabled
* @arg HRTIM_BURSTMODECTL_DISABLED: Burst mode disabled
@@ -5146,7 +5247,7 @@ HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Triggers the burst mode operation.
- * @param hhrtim: pointer to HAL HRTIM handle
+ * @param hhrtim pointer to HAL HRTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim)
@@ -5174,15 +5275,15 @@ HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim
/**
* @brief Triggers a software capture on the designed capture unit
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param CaptureUnit: Capture unit to trig
+ * @param CaptureUnit Capture unit to trig
* This parameter can be one of the following values:
* @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
* @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
@@ -5235,8 +5336,8 @@ HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Triggers the update of the registers of one or several timers
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Timers: timers concerned with the software register update
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Timers timers concerned with the software register update
* This parameter can be any combination of the following values:
* @arg HRTIM_TIMERUPDATE_MASTER
* @arg HRTIM_TIMERUPDATE_A
@@ -5277,8 +5378,8 @@ HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Triggers the reset of one or several timers
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Timers: timers concerned with the software counter reset
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Timers timers concerned with the software counter reset
* This parameter can be any combination of the following values:
* @arg HRTIM_TIMERRESET_MASTER
* @arg HRTIM_TIMERRESET_TIMER_A
@@ -5319,8 +5420,8 @@ HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Starts a burst DMA operation to update HRTIM control registers content
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_MASTER for master timer
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
@@ -5328,9 +5429,9 @@ HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim,
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param BurstBufferAddress: address of the buffer the HRTIM control registers
+ * @param BurstBufferAddress address of the buffer the HRTIM control registers
* content will be updated from.
- * @param BurstBufferLength: size (in WORDS) of the burst buffer.
+ * @param BurstBufferLength size (in WORDS) of the burst buffer.
* @retval HAL status
* @note The TimerIdx parameter determines the dma channel to be used by the
* DMA burst controller (see below)
@@ -5372,7 +5473,16 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
/* Get the timer DMA handler */
hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
-
+ if (hdma == NULL)
+ {
+ hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hhrtim);
+
+ return HAL_ERROR;
+ }
+
/* Set the DMA transfer completed callback */
hdma->XferCpltCallback = HRTIM_BurstDMACplt;
@@ -5396,8 +5506,8 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
/**
* @brief Enables the transfer from preload to active registers for one
* or several timing units (including master timer).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Timers: Timer(s) concerned by the register preload enabling command
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Timers Timer(s) concerned by the register preload enabling command
* This parameter can be any combination of the following values:
* @arg HRTIM_TIMERUPDATE_MASTER
* @arg HRTIM_TIMERUPDATE_A
@@ -5432,8 +5542,8 @@ HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
/**
* @brief Disables the transfer from preload to active registers for one
* or several timing units (including master timer).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Timers: Timer(s) concerned by the register preload disabling command
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Timers Timer(s) concerned by the register preload disabling command
* This parameter can be any combination of the following values:
* @arg HRTIM_TIMERUPDATE_MASTER
* @arg HRTIM_TIMERUPDATE_A
@@ -5492,7 +5602,7 @@ HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
/**
* @brief return the HRTIM HAL state
- * @param hhrtim: pointer to HAL HRTIM handle
+ * @param hhrtim pointer to HAL HRTIM handle
* @retval HAL state
*/
HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim)
@@ -5503,15 +5613,15 @@ HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim)
/**
* @brief Returns actual value of the capture register of the designated capture unit
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param CaptureUnit: Capture unit to trig
+ * @param CaptureUnit Capture unit to trig
* This parameter can be one of the following values:
* @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
* @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
@@ -5549,15 +5659,15 @@ uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Returns actual level (active or inactive) of the designated output
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param Output: Timer output
+ * @param Output Timer output
* This parameter can be one of the following values:
* @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
* @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
@@ -5626,15 +5736,15 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Returns actual state (RUN, IDLE, FAULT) of the designated output
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param Output: Timer output
+ * @param Output Timer output
* This parameter can be one of the following values:
* @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
* @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
@@ -5740,15 +5850,15 @@ uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Returns the level (active or inactive) of the designated output
* when the delayed protection was triggered.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
- * @param Output: Timer output
+ * @param Output Timer output
* This parameter can be one of the following values:
* @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
* @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
@@ -5819,7 +5929,7 @@ uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Returns the actual status (active or inactive) of the burst mode controller
- * @param hhrtim: pointer to HAL HRTIM handle
+ * @param hhrtim pointer to HAL HRTIM handle
* @retval Burst mode controller status
*/
uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef * hhrtim)
@@ -5835,8 +5945,8 @@ uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef * hhrtim)
/**
* @brief Indicates on which output the signal is currently active (when the
* push pull mode is enabled).
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
@@ -5863,8 +5973,8 @@ uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Indicates on which output the signal was applied, in push-pull mode,
balanced fault mode or delayed idle mode, when the protection was triggered.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
@@ -5951,8 +6061,8 @@ uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief This function handles HRTIM interrupt request.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be any value of @ref HRTIM_Timer_Index
* @retval None
*/
@@ -5979,7 +6089,7 @@ void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Callback function invoked when a fault 1 interrupt occured
- * @param hhrtim: pointer to HAL HRTIM handle * @retval None
+ * @param hhrtim pointer to HAL HRTIM handle * @retval None
* @retval None
*/
__weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim)
@@ -5994,7 +6104,7 @@ __weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim)
/**
* @brief Callback function invoked when a fault 2 interrupt occured
- * @param hhrtim: pointer to HAL HRTIM handle
+ * @param hhrtim pointer to HAL HRTIM handle
* @retval None
*/
__weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim)
@@ -6009,7 +6119,7 @@ __weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim)
/**
* @brief Callback function invoked when a fault 3 interrupt occured
- * @param hhrtim: pointer to HAL HRTIM handle
+ * @param hhrtim pointer to HAL HRTIM handle
* @retval None
*/
__weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim)
@@ -6024,7 +6134,7 @@ __weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim)
/**
* @brief Callback function invoked when a fault 4 interrupt occured
- * @param hhrtim: pointer to HAL HRTIM handle
+ * @param hhrtim pointer to HAL HRTIM handle
* @retval None
*/
__weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim)
@@ -6039,7 +6149,7 @@ __weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim)
/**
* @brief Callback function invoked when a fault 5 interrupt occured
- * @param hhrtim: pointer to HAL HRTIM handle
+ * @param hhrtim pointer to HAL HRTIM handle
* @retval None
*/
__weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim)
@@ -6054,7 +6164,7 @@ __weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim)
/**
* @brief Callback function invoked when a system fault interrupt occured
- * @param hhrtim: pointer to HAL HRTIM handle
+ * @param hhrtim pointer to HAL HRTIM handle
* @retval None
*/
__weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim)
@@ -6069,7 +6179,7 @@ __weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim)
/**
* @brief Callback function invoked when the DLL calibration is completed
- * @param hhrtim: pointer to HAL HRTIM handle
+ * @param hhrtim pointer to HAL HRTIM handle
* @retval None
*/
__weak void HAL_HRTIM_DLLCalbrationReadyCallback(HRTIM_HandleTypeDef * hhrtim)
@@ -6084,7 +6194,7 @@ __weak void HAL_HRTIM_DLLCalbrationReadyCallback(HRTIM_HandleTypeDef * hhrtim)
/**
* @brief Callback function invoked when the end of the burst mode period is reached
- * @param hhrtim: pointer to HAL HRTIM handle
+ * @param hhrtim pointer to HAL HRTIM handle
* @retval None
*/
__weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim)
@@ -6099,7 +6209,7 @@ __weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim)
/**
* @brief Callback function invoked when a synchronization input event is received
- * @param hhrtim: pointer to HAL HRTIM handle
+ * @param hhrtim pointer to HAL HRTIM handle
* @retval None
*/
__weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim)
@@ -6114,8 +6224,8 @@ __weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim)
/**
* @brief Callback function invoked when timer registers are updated
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_MASTER for master timer
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
@@ -6139,8 +6249,8 @@ __weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Callback function invoked when timer repetition period has elapsed
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_MASTER for master timer
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
@@ -6165,8 +6275,8 @@ __weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Callback function invoked when the timer counter matches the value
* programmed in the compare 1 register
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_MASTER for master timer
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
@@ -6191,9 +6301,9 @@ __weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Callback function invoked when the timer counter matches the value
* programmed in the compare 2 register
- * @param hhrtim: pointer to HAL HRTIM handle
+ * @param hhrtim pointer to HAL HRTIM handle
* @retval None
- * @param TimerIdx: Timer index
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_MASTER for master timer
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
@@ -6217,8 +6327,8 @@ __weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Callback function invoked when the timer counter matches the value
* programmed in the compare 3 register
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_MASTER for master timer
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
@@ -6243,8 +6353,8 @@ __weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Callback function invoked when the timer counter matches the value
* programmed in the compare 4 register.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_MASTER for master timer
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
@@ -6268,8 +6378,8 @@ __weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Callback function invoked when the timer x capture 1 event occurs
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
@@ -6292,8 +6402,8 @@ __weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Callback function invoked when the timer x capture 2 event occurs
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
@@ -6317,8 +6427,8 @@ __weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Callback function invoked when the delayed idle or balanced idle mode is
* entered.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
@@ -6342,8 +6452,8 @@ __weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Callback function invoked when the timer x counter reset/roll-over
* event occurs.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
@@ -6366,8 +6476,8 @@ __weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Callback function invoked when the timer x output 1 is set
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
@@ -6390,8 +6500,8 @@ __weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Callback function invoked when the timer x output 1 is reset
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
@@ -6414,8 +6524,8 @@ __weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Callback function invoked when the timer x output 2 is set
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
@@ -6438,8 +6548,8 @@ __weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Callback function invoked when the timer x output 2 is reset
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
@@ -6462,8 +6572,8 @@ __weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Callback function invoked when a DMA burst transfer is completed
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_MASTER for master timer
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
@@ -6487,7 +6597,7 @@ __weak void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Callback function invoked when a DMA error occurs
- * @param hhrtim: pointer to HAL HRTIM handle
+ * @param hhrtim pointer to HAL HRTIM handle
* @retval None
*/
__weak void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim)
@@ -6514,8 +6624,8 @@ __weak void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim)
/**
* @brief Configures the master timer time base
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param pTimeBaseCfg: pointer to the time base configuration structure
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param pTimeBaseCfg pointer to the time base configuration structure
* @retval None
*/
static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
@@ -6542,9 +6652,9 @@ static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Configures timing unit (timer A to timer E) time base
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * @param pTimeBaseCfg: pointer to the time base configuration structure
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * @param pTimeBaseCfg pointer to the time base configuration structure
* @retval None
*/
static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
@@ -6572,8 +6682,8 @@ static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Configures the master timer in waveform mode
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param pTimerCfg: pointer to the timer configuration data structure
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param pTimerCfg pointer to the timer configuration data structure
* @retval None
*/
static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
@@ -6625,9 +6735,9 @@ static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Configures timing unit (timer A to timer E) in waveform mode
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * @param pTimerCfg: pointer to the timer configuration data structure
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * @param pTimerCfg pointer to the timer configuration data structure
* @retval None
*/
static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
@@ -6772,10 +6882,10 @@ static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Configures a compare unit
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * @param CompareUnit: Compare unit identifier
- * @param pCompareCfg: pointer to the compare unit configuration data structure
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * @param CompareUnit Compare unit identifier
+ * @param pCompareCfg pointer to the compare unit configuration data structure
* @retval None
*/
static void HRTIM_CompareUnitConfig(HRTIM_HandleTypeDef * hhrtim,
@@ -6845,10 +6955,10 @@ static void HRTIM_CompareUnitConfig(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Configures a capture unit
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * @param CaptureUnit: Capture unit identifier
- * @param Event: Event reference
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * @param CaptureUnit Capture unit identifier
+ * @param Event Event reference
* @retval None
*/
static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
@@ -6933,10 +7043,10 @@ static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Configures the output of a timing unit
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * @param Output: timing unit output identifier
- * @param pOutputCfg: pointer to the output configuration data structure
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * @param Output timing unit output identifier
+ * @param pOutputCfg pointer to the output configuration data structure
* @retval None
*/
static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
@@ -7026,9 +7136,9 @@ static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Configures an external event channel
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param Event: Event channel identifier
- * @param pEventCfg: pointer to the event channel configuration data structure
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param Event Event channel identifier
+ * @param pEventCfg pointer to the event channel configuration data structure
* @retval None
*/
static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
@@ -7183,9 +7293,9 @@ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Configures the timer counter reset
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * @param Event: Event channel identifier
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * @param Event Event channel identifier
* @retval None
*/
static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
@@ -7252,9 +7362,9 @@ static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Returns the interrupt to enable or disable according to the
* OC mode.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * @param OCChannel: Timer output
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * @param OCChannel Timer output
* This parameter can be one of the following values:
* @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
* @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
@@ -7348,9 +7458,9 @@ static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief Returns the DMA request to enable or disable according to the
* OC mode.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
- * @param OCChannel: Timer output
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
+ * @param OCChannel Timer output
* This parameter can be one of the following values:
* @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
* @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
@@ -7520,8 +7630,8 @@ static uint32_t GetTimerIdxFromDMAHandle(DMA_HandleTypeDef *hdma)
/**
* @brief Forces an immediate transfer from the preload to the active
* registers.
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* @retval None
*/
static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
@@ -7567,7 +7677,7 @@ static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief HRTIM interrupts service routine
- * @param hhrtim: pointer to HAL HRTIM handle
+ * @param hhrtim pointer to HAL HRTIM handle
* @retval None
*/
static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim)
@@ -7647,7 +7757,7 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim)
/**
* @brief Master timer interrupts service routine
-* @param hhrtim: pointer to HAL HRTIM handle
+* @param hhrtim pointer to HAL HRTIM handle
* @retval None
*/
static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim)
@@ -7769,8 +7879,8 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim)
/**
* @brief Timer interrupts service routine
- * @param hhrtim: pointer to HAL HRTIM handle
- * @param TimerIdx: Timer index
+ * @param hhrtim pointer to HAL HRTIM handle
+ * @param TimerIdx Timer index
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
@@ -7953,7 +8063,7 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
/**
* @brief DMA callback invoked upon master timer related DMA request completion
- * @param hdma: pointer to DMA handle.
+ * @param hdma pointer to DMA handle.
* @retval None
*/
static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma)
@@ -7992,7 +8102,7 @@ static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA callback invoked upon timer A..E related DMA request completion
- * @param hdma: pointer to DMA handle.
+ * @param hdma pointer to DMA handle.
* @retval None
*/
static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma)
@@ -8003,67 +8113,70 @@ static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma)
timer_idx = GetTimerIdxFromDMAHandle(hdma);
- if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP1) != RESET)
- {
- HAL_HRTIM_Compare1EventCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP2) != RESET)
- {
- HAL_HRTIM_Compare2EventCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP3) != RESET)
- {
- HAL_HRTIM_Compare3EventCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP4) != RESET)
- {
- HAL_HRTIM_Compare4EventCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_REP) != RESET)
- {
- HAL_HRTIM_RepetitionEventCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_UPD) != RESET)
- {
- HAL_HRTIM_RegistersUpdateCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT1) != RESET)
- {
- HAL_HRTIM_Capture1EventCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT2) != RESET)
- {
- HAL_HRTIM_Capture2EventCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET1) != RESET)
- {
- HAL_HRTIM_Output1SetCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST1) != RESET)
- {
- HAL_HRTIM_Output1ResetCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET2) != RESET)
- {
- HAL_HRTIM_Output2SetCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST2) != RESET)
- {
- HAL_HRTIM_Output2ResetCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST) != RESET)
- {
- HAL_HRTIM_CounterResetCallback(hrtim, timer_idx);
- }
- else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_DLYPRT) != RESET)
+ if (IS_HRTIM_TIMING_UNIT( timer_idx))
{
- HAL_HRTIM_DelayedProtectionCallback(hrtim, timer_idx);
+ if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP1) != RESET)
+ {
+ HAL_HRTIM_Compare1EventCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP2) != RESET)
+ {
+ HAL_HRTIM_Compare2EventCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP3) != RESET)
+ {
+ HAL_HRTIM_Compare3EventCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP4) != RESET)
+ {
+ HAL_HRTIM_Compare4EventCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_REP) != RESET)
+ {
+ HAL_HRTIM_RepetitionEventCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_UPD) != RESET)
+ {
+ HAL_HRTIM_RegistersUpdateCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT1) != RESET)
+ {
+ HAL_HRTIM_Capture1EventCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT2) != RESET)
+ {
+ HAL_HRTIM_Capture2EventCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET1) != RESET)
+ {
+ HAL_HRTIM_Output1SetCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST1) != RESET)
+ {
+ HAL_HRTIM_Output1ResetCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET2) != RESET)
+ {
+ HAL_HRTIM_Output2SetCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST2) != RESET)
+ {
+ HAL_HRTIM_Output2ResetCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST) != RESET)
+ {
+ HAL_HRTIM_CounterResetCallback(hrtim, timer_idx);
+ }
+ else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_DLYPRT) != RESET)
+ {
+ HAL_HRTIM_DelayedProtectionCallback(hrtim, timer_idx);
+ }
}
}
/**
* @brief DMA error callback
-* @param hdma: pointer to DMA handle.
+* @param hdma pointer to DMA handle.
* @retval None
*/
static void HRTIM_DMAError(DMA_HandleTypeDef *hdma)
@@ -8075,7 +8188,7 @@ static void HRTIM_DMAError(DMA_HandleTypeDef *hdma)
/**
* @brief DMA callback invoked upon burst DMA transfer completion
- * @param hdma: pointer to DMA handle.
+ * @param hdma pointer to DMA handle.
* @retval None
*/
static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma)
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c
index 4e283ffa5c..7328bf6ca2 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_i2c.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief I2C HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Inter Integrated Circuit (I2C) peripheral:
@@ -238,7 +236,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal.h"
@@ -366,7 +364,7 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui
*/
/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
@@ -406,7 +404,7 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
/* Check the I2C handle allocation */
- if(hi2c == NULL)
+ if (hi2c == NULL)
{
return HAL_ERROR;
}
@@ -421,7 +419,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
- if(hi2c->State == HAL_I2C_STATE_RESET)
+ if (hi2c->State == HAL_I2C_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
@@ -444,7 +442,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
/* Configure I2Cx: Own Address1 and ack own address1 mode */
- if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
}
@@ -455,7 +453,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
/* Configure I2Cx: Addressing Master mode */
- if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
{
hi2c->Instance->CR2 = (I2C_CR2_ADD10);
}
@@ -493,7 +491,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
{
/* Check the I2C handle allocation */
- if(hi2c == NULL)
+ if (hi2c == NULL)
{
return HAL_ERROR;
}
@@ -557,7 +555,7 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
*/
/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
- * @brief Data transfers functions
+ * @brief Data transfers functions
*
@verbatim
===============================================================================
@@ -569,7 +567,7 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
(#) There are two modes of transfer:
(++) Blocking mode : The communication is performed in the polling mode.
- The status of all data processing is returned by the same function
+ The status of all data processing is returned by the same function
after finishing transfer.
(++) No-Blocking mode : The communication is performed using Interrupts
or DMA. These functions return the status of the transfer startup.
@@ -630,7 +628,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
{
uint32_t tickstart = 0U;
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
@@ -638,7 +636,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -646,7 +644,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
+
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
@@ -654,7 +652,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
@@ -665,12 +663,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
}
- while(hi2c->XferCount > 0U)
+ while (hi2c->XferCount > 0U)
{
/* Wait until TXIS flag is set */
- if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -684,15 +682,15 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
hi2c->XferCount--;
hi2c->XferSize--;
- if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U))
+ if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
{
/* Wait until TCR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
@@ -707,9 +705,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is set */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -754,15 +752,15 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
{
uint32_t tickstart = 0U;
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
/* Process Locked */
__HAL_LOCK(hi2c);
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -778,7 +776,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
@@ -789,12 +787,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
}
- while(hi2c->XferCount > 0U)
+ while (hi2c->XferCount > 0U)
{
/* Wait until RXNE flag is set */
- if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -809,15 +807,15 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
hi2c->XferSize--;
hi2c->XferCount--;
- if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
+ if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
{
/* Wait until TCR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
@@ -832,9 +830,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is set */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -843,7 +841,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
return HAL_TIMEOUT;
}
}
-
+
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
@@ -865,7 +863,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
}
/**
- * @brief Transmits in slave mode an amount of data in blocking mode.
+ * @brief Transmits in slave mode an amount of data in blocking mode.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param pData Pointer to data buffer
@@ -877,15 +875,15 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
{
uint32_t tickstart = 0U;
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hi2c);
-
+
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
@@ -902,7 +900,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
/* Wait until ADDR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -910,13 +908,13 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
}
/* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
/* If 10bit addressing mode is selected */
- if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
{
/* Wait until ADDR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -924,26 +922,26 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
}
/* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
}
/* Wait until DIR flag is set Transmitter mode */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
return HAL_TIMEOUT;
}
- while(hi2c->XferCount > 0U)
+ while (hi2c->XferCount > 0U)
{
/* Wait until TXIS flag is set */
- if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -959,16 +957,16 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
}
/* Wait until STOP flag is set */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
- /* Normal use case for Transmitter mode */
- /* A NACK is generated to confirm the end of transfer */
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ /* Normal use case for Transmitter mode */
+ /* A NACK is generated to confirm the end of transfer */
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
}
else
{
@@ -977,10 +975,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
}
/* Clear STOP flag */
- __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+ /* Wait until BUSY flag is reset */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -1017,9 +1015,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
{
uint32_t tickstart = 0U;
- if(hi2c->State == HAL_I2C_STATE_READY)
- {
- if((pData == NULL) || (Size == 0U))
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -1042,7 +1040,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
/* Wait until ADDR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -1050,33 +1048,33 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
}
/* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
/* Wait until DIR flag is reset Receiver mode */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
return HAL_TIMEOUT;
}
- while(hi2c->XferCount > 0U)
+ while (hi2c->XferCount > 0U)
{
/* Wait until RXNE flag is set */
- if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
/* Store Last receive data if any */
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
{
/* Read data from RXDR */
(*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
hi2c->XferCount--;
}
- if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
{
return HAL_TIMEOUT;
}
@@ -1092,12 +1090,12 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
}
/* Wait until STOP flag is set */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -1108,10 +1106,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
}
/* Clear STOP flag */
- __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -1149,9 +1147,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
{
uint32_t xfermode = 0U;
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
@@ -1168,8 +1166,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Master_ISR_IT;
-
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
@@ -1185,7 +1183,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
/* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ __HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
@@ -1218,9 +1216,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De
{
uint32_t xfermode = 0U;
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
@@ -1237,8 +1235,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Master_ISR_IT;
-
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
@@ -1252,7 +1250,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
-
+
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1283,7 +1281,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De
*/
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
{
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
@@ -1323,7 +1321,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD
}
/**
- * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
+ * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param pData Pointer to data buffer
@@ -1332,7 +1330,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD
*/
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
{
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
@@ -1385,9 +1383,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
{
uint32_t xfermode = 0U;
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
@@ -1404,8 +1402,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Master_ISR_DMA;
-
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
@@ -1416,7 +1414,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
xfermode = I2C_AUTOEND_MODE;
}
- if(hi2c->XferSize > 0U)
+ if (hi2c->XferSize > 0U)
{
/* Set the I2C DMA transfer complete callback */
hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
@@ -1454,7 +1452,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
{
/* Update Transfer ISR function pointer */
hi2c->XferISR = I2C_Master_ISR_IT;
-
+
/* Send Slave Address */
/* Set NBYTES to write and generate START condition */
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
@@ -1493,9 +1491,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
{
uint32_t xfermode = 0U;
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
@@ -1512,8 +1510,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Master_ISR_DMA;
-
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
@@ -1524,7 +1522,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
xfermode = I2C_AUTOEND_MODE;
}
- if(hi2c->XferSize > 0U)
+ if (hi2c->XferSize > 0U)
{
/* Set the I2C DMA transfer complete callback */
hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
@@ -1541,7 +1539,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
/* Send Slave Address */
/* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
/* Update XferCount value */
hi2c->XferCount -= hi2c->XferSize;
@@ -1562,7 +1560,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
{
/* Update Transfer ISR function pointer */
hi2c->XferISR = I2C_Master_ISR_IT;
-
+
/* Send Slave Address */
/* Set NBYTES to read and generate START condition */
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
@@ -1596,12 +1594,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
*/
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
{
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
- }
+ }
/* Process Locked */
__HAL_LOCK(hi2c);
@@ -1642,7 +1640,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
/* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
return HAL_OK;
}
@@ -1662,12 +1660,12 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
*/
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
{
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
- }
+ }
/* Process Locked */
__HAL_LOCK(hi2c);
@@ -1737,9 +1735,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -1750,7 +1748,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -1765,9 +1763,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
hi2c->XferISR = NULL;
/* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1782,7 +1780,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
}
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
@@ -1796,9 +1794,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
do
{
/* Wait until TXIS flag is set */
- if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -1813,15 +1811,15 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
hi2c->XferCount--;
hi2c->XferSize--;
- if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U))
+ if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
{
/* Wait until TCR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
@@ -1833,13 +1831,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
}
}
- }while(hi2c->XferCount > 0U);
+ }
+ while (hi2c->XferCount > 0U);
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is reset */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ /* Wait until STOPF flag is reset */
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -1889,9 +1888,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -1902,7 +1901,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -1917,9 +1916,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
hi2c->XferISR = NULL;
/* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1935,7 +1934,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
@@ -1949,7 +1948,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
do
{
/* Wait until RXNE flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -1959,15 +1958,15 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
hi2c->XferSize--;
hi2c->XferCount--;
- if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
+ if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
{
/* Wait until TCR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
@@ -1978,13 +1977,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
}
}
- }while(hi2c->XferCount > 0U);
+ }
+ while (hi2c->XferCount > 0U);
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is reset */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ /* Wait until STOPF flag is reset */
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -2033,14 +2033,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
-
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
@@ -2060,8 +2060,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Master_ISR_IT;
-
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
@@ -2073,9 +2073,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
}
/* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2090,12 +2090,12 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
}
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
/* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ __HAL_UNLOCK(hi2c);
- /* Note : The I2C interrupts must be enabled after unlocking current process
+ /* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
@@ -2132,14 +2132,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
-
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
@@ -2159,8 +2159,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Master_ISR_IT;
-
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
@@ -2172,9 +2172,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
}
/* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2189,7 +2189,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
}
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2230,14 +2230,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
@@ -2257,8 +2257,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Master_ISR_DMA;
-
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
@@ -2270,9 +2270,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
}
/* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2346,14 +2346,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
@@ -2374,7 +2374,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Master_ISR_DMA;
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
@@ -2386,9 +2386,9 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
}
/* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2416,7 +2416,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
/* Update XferCount value */
hi2c->XferCount -= hi2c->XferSize;
@@ -2458,9 +2458,9 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
__IO uint32_t I2C_Trials = 0U;
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
@@ -2474,16 +2474,16 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
do
{
/* Generate Start */
- hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress);
+ hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is set or a NACK flag is set*/
tickstart = HAL_GetTick();
- while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT))
+ while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT))
{
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
/* Device is ready */
hi2c->State = HAL_I2C_STATE_READY;
@@ -2491,14 +2491,14 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
__HAL_UNLOCK(hi2c);
return HAL_TIMEOUT;
}
- }
+ }
}
/* Check if the NACKF flag has not been set */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
{
- /* Wait until STOPF flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+ /* Wait until STOPF flag is reset */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -2517,7 +2517,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
else
{
/* Wait until STOPF flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -2535,8 +2535,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
/* Generate Stop */
hi2c->Instance->CR2 |= I2C_CR2_STOP;
- /* Wait until STOPF flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+ /* Wait until STOPF flag is reset */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -2544,7 +2544,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
}
- }while(I2C_Trials < Trials);
+ }
+ while (I2C_Trials < Trials);
hi2c->State = HAL_I2C_STATE_READY;
@@ -2579,7 +2580,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
@@ -2595,7 +2596,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
hi2c->XferISR = I2C_Master_ISR_IT;
/* If size > MAX_NBYTE_SIZE, use reload mode */
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
@@ -2608,7 +2609,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
/* If transfer direction not change, do not generate Restart Condition */
/* Mean Previous state is same as current state */
- if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
+ if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
{
xferrequest = I2C_NO_STARTSTOP;
}
@@ -2652,7 +2653,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c,
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
@@ -2668,7 +2669,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c,
hi2c->XferISR = I2C_Master_ISR_IT;
/* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
@@ -2681,13 +2682,13 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c,
/* If transfer direction not change, do not generate Restart Condition */
/* Mean Previous state is same as current state */
- if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
+ if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
{
xferrequest = I2C_NO_STARTSTOP;
}
/* Send Slave Address and set NBYTES to read */
- I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, xferrequest);
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2720,9 +2721,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
+ if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -2732,10 +2733,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
/* Process Locked */
__HAL_LOCK(hi2c);
-
+
/* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
/* and then toggle the HAL slave RX state to TX state */
- if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
{
/* Disable associated Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
@@ -2755,11 +2756,11 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
hi2c->XferOptions = XferOptions;
hi2c->XferISR = I2C_Slave_ISR_IT;
- if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
- __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
}
/* Process Unlocked */
@@ -2794,9 +2795,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
+ if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -2806,15 +2807,15 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u
/* Process Locked */
__HAL_LOCK(hi2c);
-
+
/* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
/* and then toggle the HAL slave TX state to RX state */
- if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
{
/* Disable associated Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
}
-
+
hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -2829,11 +2830,11 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u
hi2c->XferOptions = XferOptions;
hi2c->XferISR = I2C_Slave_ISR_IT;
- if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
- __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
}
/* Process Unlocked */
@@ -2861,7 +2862,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, u
*/
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
{
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
hi2c->State = HAL_I2C_STATE_LISTEN;
hi2c->XferISR = I2C_Slave_ISR_IT;
@@ -2889,7 +2890,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
uint32_t tmp;
/* Disable Address listen mode only if a transfer is not ongoing */
- if(hi2c->State == HAL_I2C_STATE_LISTEN)
+ if (hi2c->State == HAL_I2C_STATE_LISTEN)
{
tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
@@ -2918,7 +2919,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
*/
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
{
- if(hi2c->Mode == HAL_I2C_MODE_MASTER)
+ if (hi2c->Mode == HAL_I2C_MODE_MASTER)
{
/* Process Locked */
__HAL_LOCK(hi2c);
@@ -2937,7 +2938,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- /* Note : The I2C interrupts must be enabled after unlocking current process
+ /* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
@@ -2958,7 +2959,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA
/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
* @{
- */
+ */
/**
* @brief This function handles I2C event interrupt request.
@@ -2973,7 +2974,7 @@ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
uint32_t itsources = READ_REG(hi2c->Instance->CR1);
/* I2C events treatment -------------------------------------*/
- if(hi2c->XferISR != NULL)
+ if (hi2c->XferISR != NULL)
{
hi2c->XferISR(hi2c, itflags, itsources);
}
@@ -2991,7 +2992,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
uint32_t itsources = READ_REG(hi2c->Instance->CR1);
/* I2C Bus error interrupt occurred ------------------------------------*/
- if(((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
+ if (((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
@@ -3000,7 +3001,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
}
/* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
- if(((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
+ if (((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
@@ -3009,7 +3010,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
}
/* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
- if(((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
+ if (((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
@@ -3018,7 +3019,7 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
}
/* Call the Error Callback in case of Error detected */
- if((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
+ if ((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
{
I2C_ITError(hi2c, hi2c->ErrorCode);
}
@@ -3091,8 +3092,8 @@ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
* @brief Slave Address Match callback.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
- * @param AddrMatchCode: Address Match Code
+ * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
+ * @param AddrMatchCode Address Match Code
* @retval None
*/
__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
@@ -3242,7 +3243,7 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
/**
* @}
- */
+ */
/**
* @}
@@ -3260,14 +3261,14 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
{
uint16_t devaddress = 0U;
/* Process Locked */
__HAL_LOCK(hi2c);
- if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
+ if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@@ -3280,27 +3281,27 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
}
- else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
+ else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
{
/* Read data from RXDR */
(*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
hi2c->XferSize--;
hi2c->XferCount--;
}
- else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
+ else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
{
/* Write data to TXDR */
hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
hi2c->XferSize--;
- hi2c->XferCount--;
+ hi2c->XferCount--;
}
- else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
+ else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
{
- if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
+ if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
{
devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
-
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
@@ -3308,7 +3309,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
else
{
hi2c->XferSize = hi2c->XferCount;
- if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+ if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
{
I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
}
@@ -3321,7 +3322,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
else
{
/* Call TxCpltCallback() if no stop mode is set */
- if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+ if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
{
/* Call I2C Master Sequential complete process */
I2C_ITMasterSequentialCplt(hi2c);
@@ -3334,14 +3335,14 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
}
}
}
- else if(((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
+ else if (((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
{
- if(hi2c->XferCount == 0U)
+ if (hi2c->XferCount == 0U)
{
- if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+ if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
{
/* Generate a stop condition in case of no transfer option */
- if(hi2c->XferOptions == I2C_NO_OPTION_FRAME)
+ if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
{
/* Generate Stop */
hi2c->Instance->CR2 |= I2C_CR2_STOP;
@@ -3361,7 +3362,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
}
}
- if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
+ if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
{
/* Call I2C Master complete process */
I2C_ITMasterCplt(hi2c, ITFlags);
@@ -3381,26 +3382,26 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
{
/* Process locked */
__HAL_LOCK(hi2c);
-
- if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
+
+ if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
/* Mean XferCount == 0*/
/* So clear Flag NACKF only */
- if(hi2c->XferCount == 0U)
+ if (hi2c->XferCount == 0U)
{
- if(((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \
- (hi2c->State == HAL_I2C_STATE_LISTEN))
+ if (((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \
+ (hi2c->State == HAL_I2C_STATE_LISTEN))
{
/* Call I2C Listen complete process */
I2C_ITListenCplt(hi2c, ITFlags);
}
- else if((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN))
+ else if ((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN))
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@@ -3428,9 +3429,9 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
}
- else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
+ else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
{
- if(hi2c->XferCount > 0U)
+ if (hi2c->XferCount > 0U)
{
/* Read data from RXDR */
(*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
@@ -3438,24 +3439,24 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
hi2c->XferCount--;
}
- if((hi2c->XferCount == 0U) && \
- (hi2c->XferOptions != I2C_NO_OPTION_FRAME))
+ if ((hi2c->XferCount == 0U) && \
+ (hi2c->XferOptions != I2C_NO_OPTION_FRAME))
{
/* Call I2C Slave Sequential complete process */
I2C_ITSlaveSequentialCplt(hi2c);
- }
+ }
}
- else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
+ else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
{
I2C_ITAddrCplt(hi2c, ITFlags);
}
- else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
+ else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
{
/* Write data to TXDR only if XferCount not reach "0" */
/* A TXIS flag can be set, during STOP treatment */
/* Check if all Datas have already been sent */
/* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
- if(hi2c->XferCount > 0U)
+ if (hi2c->XferCount > 0U)
{
/* Write data to TXDR */
hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
@@ -3464,7 +3465,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
}
else
{
- if((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME))
+ if ((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME))
{
/* Last Byte is Transmitted */
/* Call I2C Slave Sequential complete process */
@@ -3474,7 +3475,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
}
/* Check if STOPF is set */
- if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
+ if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
{
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, ITFlags);
@@ -3494,7 +3495,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
{
uint16_t devaddress = 0U;
uint32_t xfermode = 0U;
@@ -3502,14 +3503,14 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui
/* Process Locked */
__HAL_LOCK(hi2c);
- if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
+ if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
/* Set corresponding Error Code */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-
+
/* No need to generate STOP, it is automatically done */
/* But enable STOP interrupt, to treat it */
/* Error callback will be send during stop flag treatment */
@@ -3518,18 +3519,18 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
}
- else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
+ else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
{
/* Disable TC interrupt */
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
-
- if(hi2c->XferCount != 0U)
+
+ if (hi2c->XferCount != 0U)
{
/* Recover Slave address */
devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
-
+
/* Prepare the new XferSize to transfer */
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
@@ -3547,7 +3548,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui
hi2c->XferCount -= hi2c->XferSize;
/* Enable DMA Request */
- if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
}
@@ -3563,7 +3564,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui
I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
}
}
- else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
+ else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
{
/* Call I2C Master complete process */
I2C_ITMasterCplt(hi2c, ITFlags);
@@ -3583,18 +3584,18 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
{
/* Process locked */
__HAL_LOCK(hi2c);
-
- if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
+
+ if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
/* Mean XferCount == 0 */
/* So clear Flag NACKF only */
- if(I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U)
+ if (I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U)
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@@ -3604,17 +3605,17 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
/* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
+
/* Set ErrorCode corresponding to a Non-Acknowledge */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
}
- else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
+ else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
{
/* Clear ADDR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
}
- else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
+ else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
{
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, ITFlags);
@@ -3640,12 +3641,12 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
*/
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
{
- I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+ I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
/* Wait until TXIS flag is set */
- if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -3656,7 +3657,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_
}
/* If Memory address size is 8Bit */
- if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
+ if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
/* Send Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
@@ -3668,9 +3669,9 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
/* Wait until TXIS flag is set */
- if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -3679,18 +3680,18 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_
return HAL_TIMEOUT;
}
}
-
+
/* Send LSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
}
/* Wait until TCR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
-return HAL_OK;
+ return HAL_OK;
}
/**
@@ -3707,12 +3708,12 @@ return HAL_OK;
*/
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
{
- I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
+ I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
/* Wait until TXIS flag is set */
- if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -3723,7 +3724,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t
}
/* If Memory address size is 8Bit */
- if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
+ if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
/* Send Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
@@ -3735,9 +3736,9 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
/* Wait until TXIS flag is set */
- if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -3746,17 +3747,17 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t
return HAL_TIMEOUT;
}
}
-
+
/* Send LSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
}
/* Wait until TC flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
-
+
return HAL_OK;
}
@@ -3777,7 +3778,7 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
UNUSED(ITFlags);
/* In case of Listen state, need to inform upper layer of address match code event */
- if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
+ if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
{
transferdirection = I2C_GET_DIR(hi2c);
slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);
@@ -3785,19 +3786,19 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c);
/* If 10bits addressing mode is selected */
- if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
{
- if((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
+ if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
{
slaveaddrcode = ownadd1code;
hi2c->AddrEventCount++;
- if(hi2c->AddrEventCount == 2U)
+ if (hi2c->AddrEventCount == 2U)
{
/* Reset Address Event counter */
hi2c->AddrEventCount = 0U;
/* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -3899,7 +3900,7 @@ static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c)
/* Reset I2C handle mode */
hi2c->Mode = HAL_I2C_MODE_NONE;
- if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
{
/* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
hi2c->State = HAL_I2C_STATE_LISTEN;
@@ -3915,7 +3916,7 @@ static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c)
HAL_I2C_SlaveTxCpltCallback(hi2c);
}
- else if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
{
/* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
hi2c->State = HAL_I2C_STATE_LISTEN;
@@ -3951,7 +3952,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
hi2c->XferISR = NULL;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- if((ITFlags & I2C_FLAG_AF) != RESET)
+ if ((ITFlags & I2C_FLAG_AF) != RESET)
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@@ -3964,16 +3965,16 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C_Flush_TXDR(hi2c);
/* Disable Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT| I2C_XFER_RX_IT);
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT);
/* Call the corresponding callback to inform upper layer of End of Transfer */
- if((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT))
+ if ((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT))
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, hi2c->ErrorCode);
}
/* hi2c->State == HAL_I2C_STATE_BUSY_TX */
- else if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
{
hi2c->State = HAL_I2C_STATE_READY;
@@ -3999,7 +4000,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
}
}
/* hi2c->State == HAL_I2C_STATE_BUSY_RX */
- else if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
hi2c->State = HAL_I2C_STATE_READY;
@@ -4036,7 +4037,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
/* Disable all interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
@@ -4051,26 +4052,26 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
I2C_Flush_TXDR(hi2c);
/* If a DMA is ongoing, Update handle size context */
- if(((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) ||
- ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN))
+ if (((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) ||
+ ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN))
{
hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c);
}
/* All data are not transferred, so set error code accordingly */
- if(hi2c->XferCount != 0U)
+ if (hi2c->XferCount != 0U)
{
/* Set ErrorCode corresponding to a Non-Acknowledge */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
/* Store Last receive data if any */
- if(((ITFlags & I2C_FLAG_RXNE) != RESET))
+ if (((ITFlags & I2C_FLAG_RXNE) != RESET))
{
/* Read data from RXDR */
(*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
- if((hi2c->XferSize > 0U))
+ if ((hi2c->XferSize > 0U))
{
hi2c->XferSize--;
hi2c->XferCount--;
@@ -4084,19 +4085,19 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->XferISR = NULL;
- if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, hi2c->ErrorCode);
/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
- if(hi2c->State == HAL_I2C_STATE_LISTEN)
+ if (hi2c->State == HAL_I2C_STATE_LISTEN)
{
/* Call I2C Listen complete process */
I2C_ITListenCplt(hi2c, ITFlags);
}
}
- else if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+ else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
{
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->State = HAL_I2C_STATE_READY;
@@ -4108,7 +4109,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
HAL_I2C_ListenCpltCallback(hi2c);
}
/* Call the corresponding callback to inform upper layer of End of Transfer */
- else if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
hi2c->State = HAL_I2C_STATE_READY;
@@ -4146,12 +4147,12 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
hi2c->XferISR = NULL;
/* Store Last receive data if any */
- if(((ITFlags & I2C_FLAG_RXNE) != RESET))
+ if (((ITFlags & I2C_FLAG_RXNE) != RESET))
{
/* Read data from RXDR */
(*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
- if((hi2c->XferSize > 0U))
+ if ((hi2c->XferSize > 0U))
{
hi2c->XferSize--;
hi2c->XferCount--;
@@ -4191,9 +4192,9 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
hi2c->ErrorCode |= ErrorCode;
/* Disable Interrupts */
- if((hi2c->State == HAL_I2C_STATE_LISTEN) ||
- (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
- (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ if ((hi2c->State == HAL_I2C_STATE_LISTEN) ||
+ (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
+ (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
{
/* Disable all interrupts, except interrupts related to LISTEN state */
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
@@ -4207,10 +4208,10 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
{
/* Disable all interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
-
+
/* If state is an abort treatment on goind, don't change state */
/* This change will be do later */
- if(hi2c->State != HAL_I2C_STATE_ABORT)
+ if (hi2c->State != HAL_I2C_STATE_ABORT)
{
/* Set HAL_I2C_STATE_READY */
hi2c->State = HAL_I2C_STATE_READY;
@@ -4220,7 +4221,7 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
}
/* Abort DMA TX transfer if any */
- if((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+ if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
{
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
@@ -4232,14 +4233,14 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
__HAL_UNLOCK(hi2c);
/* Abort DMA TX */
- if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
{
/* Call Directly XferAbortCallback function in case of error */
hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
}
}
/* Abort DMA RX transfer if any */
- else if((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+ else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
{
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
@@ -4251,16 +4252,16 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
__HAL_UNLOCK(hi2c);
/* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
{
/* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
}
}
- else if(hi2c->State == HAL_I2C_STATE_ABORT)
+ else if (hi2c->State == HAL_I2C_STATE_ABORT)
{
hi2c->State = HAL_I2C_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -4286,13 +4287,13 @@ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
{
/* If a pending TXIS flag is set */
/* Write a dummy data in TXDR to clear it */
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
{
- hi2c->Instance->TXDR = 0x00U;
+ hi2c->Instance->TXDR = 0x00U;
}
/* Flush TX register if not empty */
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
{
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
}
@@ -4305,13 +4306,13 @@ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
*/
static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
{
- I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
/* If last transfer, enable STOP interrupt */
- if(hi2c->XferCount == 0U)
+ if (hi2c->XferCount == 0U)
{
/* Enable STOP interrupt */
I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
@@ -4323,7 +4324,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
hi2c->pBuffPtr += hi2c->XferSize;
/* Set the XferSize to transfer */
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
}
@@ -4362,13 +4363,13 @@ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
*/
static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
{
- I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
/* If last transfer, enable STOP interrupt */
- if(hi2c->XferCount == 0U)
+ if (hi2c->XferCount == 0U)
{
/* Enable STOP interrupt */
I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
@@ -4380,7 +4381,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
hi2c->pBuffPtr += hi2c->XferSize;
/* Set the XferSize to transfer */
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
}
@@ -4419,7 +4420,7 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
*/
static void I2C_DMAError(DMA_HandleTypeDef *hdma)
{
- I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Disable Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -4431,12 +4432,12 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma)
/**
* @brief DMA I2C communication abort callback
* (To be called at end of DMA Abort procedure).
- * @param hdma: DMA handle.
+ * @param hdma DMA handle.
* @retval None
*/
static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
{
- I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Disable Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -4446,10 +4447,10 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
hi2c->hdmarx->XferAbortCallback = NULL;
/* Check if come from abort from user */
- if(hi2c->State == HAL_I2C_STATE_ABORT)
+ if (hi2c->State == HAL_I2C_STATE_ABORT)
{
hi2c->State = HAL_I2C_STATE_READY;
-
+
/* Call the corresponding callback to inform upper layer of End of Transfer */
HAL_I2C_AbortCpltCallback(hi2c);
}
@@ -4472,14 +4473,14 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
*/
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
{
- while(__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
+ while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
{
- hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
@@ -4501,21 +4502,21 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin
*/
static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
{
/* Check if a NACK is detected */
- if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+ if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
@@ -4538,19 +4539,19 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
*/
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
{
/* Check if a NACK is detected */
- if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+ if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Check for the Timeout */
- if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
@@ -4572,16 +4573,16 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
*/
static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
{
/* Check if a NACK is detected */
- if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+ if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Check if a STOPF is detected */
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
{
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
@@ -4590,7 +4591,7 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
I2C_RESET_CR2(hi2c);
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
@@ -4600,10 +4601,10 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
}
/* Check for the Timeout */
- if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -4624,18 +4625,18 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
*/
static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
{
/* Wait until STOP Flag is reset */
/* AutoEnd should be initiate after AF */
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
{
- hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
@@ -4658,7 +4659,7 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32
I2C_RESET_CR2(hi2c);
hi2c->ErrorCode = HAL_I2C_ERROR_AF;
- hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
@@ -4704,8 +4705,8 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui
tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
/* update tmpreg */
- tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \
- (uint32_t)Mode | (uint32_t)Request);
+ tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16) & I2C_CR2_NBYTES) | \
+ (uint32_t)Mode | (uint32_t)Request);
/* update CR2 register */
hi2c->Instance->CR2 = tmpreg;
@@ -4722,28 +4723,28 @@ static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Interr
{
uint32_t tmpisr = 0U;
- if((hi2c->XferISR == I2C_Master_ISR_DMA) || \
- (hi2c->XferISR == I2C_Slave_ISR_DMA))
+ if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \
+ (hi2c->XferISR == I2C_Slave_ISR_DMA))
{
- if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+ if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
{
/* Enable ERR, STOP, NACK and ADDR interrupts */
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
- if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
+ if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
{
/* Enable ERR and NACK interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
}
- if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+ if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= I2C_IT_STOPI;
}
-
- if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
+
+ if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
{
/* Enable TC interrupts */
tmpisr |= I2C_IT_TCI;
@@ -4751,31 +4752,31 @@ static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Interr
}
else
{
- if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+ if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
{
/* Enable ERR, STOP, NACK, and ADDR interrupts */
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
- if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+ if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
{
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
}
- if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+ if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
{
/* Enable ERR, TC, STOP, NACK and TXI interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
}
- if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+ if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= I2C_IT_STOPI;
}
}
-
+
/* Enable interrupts only at the end */
/* to avoid the risk of I2C interrupt handle execution before */
/* all interrupts requested done */
@@ -4795,49 +4796,49 @@ static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Inter
{
uint32_t tmpisr = 0U;
- if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+ if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
{
/* Disable TC and TXI interrupts */
tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
- if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
+ if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
{
/* Disable NACK and STOP interrupts */
tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
}
- if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+ if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
{
/* Disable TC and RXI interrupts */
tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
- if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
+ if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
{
/* Disable NACK and STOP interrupts */
tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
}
- if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+ if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
{
/* Disable ADDR, NACK and STOP interrupts */
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
- if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
+ if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
{
/* Enable ERR and NACK interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
}
- if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+ if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= I2C_IT_STOPI;
}
-
- if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
+
+ if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
{
/* Enable TC interrupts */
tmpisr |= I2C_IT_TCI;
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c
index 7825006715..e58a72eb3e 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c
@@ -2,10 +2,8 @@
******************************************************************************
* @file stm32f3xx_hal_i2c_ex.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief I2C Extended HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of I2C Extended peripheral:
* + Extended features functions
*
@@ -96,7 +94,7 @@
##### Extended features functions #####
===============================================================================
[..] This section provides functions allowing to:
- (+) Configure Noise Filters
+ (+) Configure Noise Filters
(+) Configure Wake Up Feature
@endverbatim
@@ -116,7 +114,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
@@ -162,7 +160,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
@@ -205,12 +203,12 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_
* the configuration information for the specified I2Cx peripheral.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
{
/* Check the parameters */
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
@@ -244,12 +242,12 @@ HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
* the configuration information for the specified I2Cx peripheral.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
{
/* Check the parameters */
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
@@ -262,7 +260,7 @@ HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
/* Enable wakeup from stop mode */
hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
- __HAL_I2C_ENABLE(hi2c);
+ __HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2s.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2s.c
index c31d058831..d9a40f4296 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2s.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2s.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_i2s.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Integrated Interchip Sound (I2S) peripheral:
@@ -343,13 +341,13 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
* @brief Transmit an amount of data in blocking mode
* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pData: a 16-bit pointer to data buffer.
- * @param Size: number of data sample to be sent:
+ * @param pData a 16-bit pointer to data buffer.
+ * @param Size number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 16-bit data length.
- * @param Timeout: Timeout duration
+ * @param Timeout Timeout duration
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @retval HAL status
@@ -434,13 +432,13 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
* @brief Receive an amount of data in blocking mode
* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pData: a 16-bit pointer to data buffer.
- * @param Size: number of data sample to be sent:
+ * @param pData a 16-bit pointer to data buffer.
+ * @param Size number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 16-bit data length.
- * @param Timeout: Timeout duration
+ * @param Timeout Timeout duration
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
@@ -537,8 +535,8 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint
* @brief Transmit an amount of data in non-blocking mode with Interrupt
* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pData: a 16-bit pointer to data buffer.
- * @param Size: number of data sample to be sent:
+ * @param pData a 16-bit pointer to data buffer.
+ * @param Size number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
@@ -600,8 +598,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData,
* @brief Receive an amount of data in non-blocking mode with Interrupt
* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pData: a 16-bit pointer to the Receive data buffer.
- * @param Size: number of data sample to be sent:
+ * @param pData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
@@ -664,8 +662,8 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u
* @brief Transmit an amount of data in non-blocking mode with DMA
* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pData: a 16-bit pointer to the Transmit data buffer.
- * @param Size: number of data sample to be sent:
+ * @param pData a 16-bit pointer to the Transmit data buffer.
+ * @param Size number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
@@ -742,8 +740,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
* @brief Receive an amount of data in non-blocking mode with DMA
* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pData: a 16-bit pointer to the Receive data buffer.
- * @param Size: number of data sample to be sent:
+ * @param pData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
@@ -1133,7 +1131,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
*/
/**
* @brief DMA I2S transmit process complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -1154,7 +1152,7 @@ static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA I2S transmit process half complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -1167,7 +1165,7 @@ static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA I2S receive process complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -1187,7 +1185,7 @@ static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA I2S receive process half complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -1200,7 +1198,7 @@ static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA I2S communication error callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -1267,9 +1265,9 @@ static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
* @brief This function handles I2S Communication Timeout.
* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param Flag: Flag checked
- * @param State: Value of the flag expected
- * @param Timeout: Duration of the timeout
+ * @param Flag Flag checked
+ * @param State Value of the flag expected
+ * @param Timeout Duration of the timeout
* @retval HAL status
*/
static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout)
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2s_ex.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2s_ex.c
index a3f6554b23..41118092b4 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2s_ex.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2s_ex.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_i2s_ex.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief I2S Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2S Extended peripheral:
@@ -19,23 +17,9 @@
called I2Sxext ie. I2S2ext for SPI2 and I2S3ext for SPI3).
(#) The Extended block is not a full SPI IP, it is used only as I2S slave to
implement full duplex mode. The Extended block uses the same clock sources
- as its master (refer to the following Figure).
+ as its master.
- +-----------------------+
- I2Sx_SCK | |
- ----------+-->| I2Sx |------------------->I2Sx_SD(in/out)
- +--|-->| |
- | | +-----------------------+
- | |
- I2S_WS | |
- ------>| |
- | | +-----------------------+
- | +-->| |
- | | I2Sx_ext |------------------->I2Sx_extSD(in/out)
- +----->| |
- +-----------------------+
-
- (#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers.
+ (#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers.
-@- Only I2Sx can deliver SCK and WS to I2Sx_ext in full duplex mode, where
I2Sx can be I2S2 or I2S3.
@@ -113,7 +97,24 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
+/*
+ Additional Figure: The Extended block uses the same clock sources as its master.
+
+ +-----------------------+
+ I2Sx_SCK | |
+ ----------+-->| I2Sx |------------------->I2Sx_SD(in/out)
+ +--|-->| |
+ | | +-----------------------+
+ | |
+ I2S_WS | |
+ ------>| |
+ | | +-----------------------+
+ | +-->| |
+ | | I2Sx_ext |------------------->I2Sx_extSD(in/out)
+ +----->| |
+ +-----------------------+
+*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal.h"
@@ -157,6 +158,7 @@ typedef enum
* @{
*/
static void I2S_TxRxDMACplt(DMA_HandleTypeDef *hdma);
+static void I2S_TxRxDMAHalfCplt(DMA_HandleTypeDef *hdma);
static void I2S_TxRxDMAError(DMA_HandleTypeDef *hdma);
static void I2S_FullDuplexTx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed);
static void I2S_FullDuplexRx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed);
@@ -535,7 +537,22 @@ __weak void HAL_I2S_TxRxCpltCallback(I2S_HandleTypeDef *hi2s)
UNUSED(hi2s);
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_TxRxCpltCallback could be implenetd in the user file
+ the HAL_I2S_TxRxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Tx and Rx Transfer half completed callbacks
+ * @param hi2s: I2S handle
+ * @retval None
+ */
+__weak void HAL_I2S_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2S_TxRxHalfCpltCallback could be implemented in the user file
*/
}
@@ -752,6 +769,7 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
(#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
(++) HAL_I2S_TxRxCpltCallback()
+ (++) HAL_I2S_TxRxHalfCpltCallback()
(++) HAL_I2S_TxRxErrorCallback()
@endverbatim
@@ -761,14 +779,14 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
/**
* @brief Full-Duplex Transmit/Receive data in blocking mode.
* @param hi2s: I2S handle
- * @param pTxData: a 16-bit pointer to the Transmit data buffer.
- * @param pRxData: a 16-bit pointer to the Receive data buffer.
- * @param Size: number of data sample to be sent:
+ * @param pTxData a 16-bit pointer to the Transmit data buffer.
+ * @param pRxData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 16-bit data length.
- * @param Timeout: Timeout duration
+ * @param Timeout Timeout duration
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @retval HAL status
@@ -999,9 +1017,9 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *p
/**
* @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
* @param hi2s: I2S handle
- * @param pTxData: a 16-bit pointer to the Transmit data buffer.
- * @param pRxData: a 16-bit pointer to the Receive data buffer.
- * @param Size: number of data sample to be sent:
+ * @param pTxData a 16-bit pointer to the Transmit data buffer.
+ * @param pRxData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
@@ -1147,9 +1165,9 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t
/**
* @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA
* @param hi2s: I2S handle
- * @param pTxData: a 16-bit pointer to the Transmit data buffer.
- * @param pRxData: a 16-bit pointer to the Receive data buffer.
- * @param Size: number of data sample to be sent:
+ * @param pTxData a 16-bit pointer to the Transmit data buffer.
+ * @param pRxData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
@@ -1197,17 +1215,22 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
-
+
/* Set the I2S Rx DMA transfer complete callback */
hi2s->hdmarx->XferCpltCallback = I2S_TxRxDMACplt;
-
- /* Set the DMA error callback */
+
+ /* Set the I2S Rx DMA Half transfer complete callback */
+ hi2s->hdmarx->XferHalfCpltCallback = I2S_TxRxDMAHalfCplt;
+
+ /* Set the I2S Rx DMA error callback */
hi2s->hdmarx->XferErrorCallback = I2S_TxRxDMAError;
-
- /* Set the I2S Tx DMA transfer complete callback */
- hi2s->hdmatx->XferCpltCallback = I2S_TxRxDMACplt;
-
- /* Set the DMA error callback */
+
+ /* Set the I2S Tx DMA transfer callbacks as NULL because the
+ communication closing is performed in DMA reception callbacks */
+ hi2s->hdmatx->XferCpltCallback = NULL;
+ hi2s->hdmatx->XferHalfCpltCallback = NULL;
+
+ /* Set the I2S Tx DMA error callback */
hi2s->hdmatx->XferErrorCallback = I2S_TxRxDMAError;
/* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
@@ -1297,56 +1320,42 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_
/**
* @brief DMA I2S transmit receive process complete callback
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void I2S_TxRxDMACplt(DMA_HandleTypeDef *hdma)
{
I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- if (hi2s->hdmarx == hdma)
+
+ /* DMA Normal Mode */
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{
- /* Disable Rx DMA Request */
+ /* Disable Rx/Tx DMA Request */
if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
{
+ hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
}
else
{
hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
+ I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
}
hi2s->RxXferCount = 0U;
+ hi2s->TxXferCount = 0U;
- if (hi2s->TxXferCount == 0U)
- {
- hi2s->State = HAL_I2S_STATE_READY;
-
- HAL_I2S_TxRxCpltCallback(hi2s);
- }
+ hi2s->State = HAL_I2S_STATE_READY;
}
-
- if (hi2s->hdmatx == hdma)
- {
- /* Disable Tx DMA Request */
- if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
- {
- hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
- }
- else
- {
- I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
- }
- hi2s->TxXferCount = 0U;
+ HAL_I2S_TxRxCpltCallback(hi2s);
+}
- if (hi2s->RxXferCount == 0U)
- {
- hi2s->State = HAL_I2S_STATE_READY;
+static void I2S_TxRxDMAHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- HAL_I2S_TxRxCpltCallback(hi2s);
- }
- }
+ HAL_I2S_TxRxHalfCpltCallback(hi2s);
}
/**
@@ -1467,9 +1476,9 @@ static void I2S_FullDuplexRx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed)
/**
* @brief This function handles I2S Communication Timeout.
* @param hi2s: I2S handle
- * @param Flag: Flag checked
- * @param State: Value of the flag expected
- * @param Timeout: Duration of the timeout
+ * @param Flag Flag checked
+ * @param State Value of the flag expected
+ * @param Timeout Duration of the timeout
* @param i2sUsed: I2S instance reference
* @retval HAL status
*/
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_irda.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_irda.c
index 225f5d02ef..8acb904fcb 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_irda.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_irda.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_irda.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief IRDA HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the IrDA (Infrared Data Association) Peripheral
@@ -1569,7 +1567,7 @@ __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
/**
* @brief Rx Half Transfer complete callback.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
@@ -1942,7 +1940,7 @@ static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA IRDA receive process complete callback.
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -1972,7 +1970,7 @@ static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA IRDA receive process half complete callback.
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_iwdg.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_iwdg.c
index b47b9dae54..26f556fc1e 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_iwdg.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_iwdg.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_iwdg.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief IWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Independent Watchdog (IWDG) peripheral:
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_msp_template.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_msp_template.c
index 186b477d2d..fbfab5ea77 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_msp_template.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_msp_template.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_msp_template.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief HAL MSP module.
* This file template is located in the HAL folder and should be copied
* to the user folder.
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_nand.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_nand.c
index e7a90cb14a..eb025c991c 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_nand.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_nand.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_nand.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief NAND HAL module driver.
* This file provides a generic firmware to drive NAND memories mounted
* as external device.
@@ -25,7 +23,10 @@
structure declared by the function caller.
(+) Access NAND flash memory by read/write operations using the functions
- HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea()
+ HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(),
+ HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(),
+ HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(),
+ HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b()
to read/write page(s)/spare area(s). These functions use specific device
information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef
structure. The read/write address information is contained by the Nand_Address_Typedef
@@ -116,19 +117,9 @@
/**
* @}
*/
-
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/** @defgroup NAND_Private_Functions NAND Private Functions
- * @{
- */
-static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef* Address);
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-
+/* Exported functions --------------------------------------------------------*/
/** @defgroup NAND_Exported_Functions NAND Exported Functions
* @{
*/
@@ -150,10 +141,10 @@ static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTyp
/**
* @brief Perform NAND memory Initialization sequence
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param ComSpace_Timing: pointer to Common space timing structure
- * @param AttSpace_Timing: pointer to Attribute space timing structure
+ * @param ComSpace_Timing pointer to Common space timing structure
+ * @param AttSpace_Timing pointer to Attribute space timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
@@ -168,7 +159,6 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT
{
/* Allocate lock resource and initialize it */
hnand->Lock = HAL_UNLOCKED;
-
/* Initialize the low level hardware (MSP) */
HAL_NAND_MspInit(hnand);
}
@@ -193,7 +183,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT
/**
* @brief Perform NAND memory De-Initialization sequence
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL status
*/
@@ -216,7 +206,7 @@ HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
/**
* @brief NAND MSP Init
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval None
*/
@@ -224,7 +214,6 @@ __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hnand);
-
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_NAND_MspInit could be implemented in the user file
*/
@@ -232,7 +221,7 @@ __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
/**
* @brief NAND MSP DeInit
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval None
*/
@@ -240,7 +229,6 @@ __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hnand);
-
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_NAND_MspDeInit could be implemented in the user file
*/
@@ -249,7 +237,7 @@ __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
/**
* @brief This function handles NAND device interrupt request.
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL status
*/
@@ -293,12 +281,12 @@ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
/* Clear NAND interrupt FIFO empty pending bit */
__FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT);
- }
+ }
}
/**
* @brief NAND interrupt feature callback
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval None
*/
@@ -306,7 +294,6 @@ __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hnand);
-
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_NAND_ITCallback could be implemented in the user file
*/
@@ -333,14 +320,15 @@ __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
/**
* @brief Read the NAND memory electronic signature
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param pNAND_ID: NAND ID structure
+ * @param pNAND_ID NAND ID structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
{
__IO uint32_t data = 0U;
+ __IO uint32_t data1 = 0U;
uint32_t deviceaddress = 0U;
/* Process Locked */
@@ -365,48 +353,62 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
- /* Send Read ID command sequence */
+ /* Send Read ID command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID;
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- /* Read the electronic signature from NAND flash */
- data = *(__IO uint32_t *)deviceaddress;
-
- /* Return the data read */
- pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
- pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
- pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
- pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
+ /* Read the electronic signature from NAND flash */
+ if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8)
+ {
+ data = *(__IO uint32_t *)deviceaddress;
+
+ /* Return the data read */
+ pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
+ pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
+ pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
+ pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
+ }
+ else
+ {
+ data = *(__IO uint32_t *)deviceaddress;
+ data1 = *((__IO uint32_t *)deviceaddress + 4U);
+
+ /* Return the data read */
+ pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
+ pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data);
+ pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1);
+ pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1);
+ }
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
- __HAL_UNLOCK(hnand);
+ __HAL_UNLOCK(hnand);
return HAL_OK;
}
/**
* @brief NAND memory reset
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
{
uint32_t deviceaddress = 0U;
-
+
/* Process Locked */
__HAL_LOCK(hnand);
-
+
/* Check the NAND controller state */
if(hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
- /* Identify the device address */
+ /* Identify the device address */
if(hnand->Init.NandBank == FMC_NAND_BANK2)
{
deviceaddress = NAND_DEVICE1;
@@ -416,38 +418,189 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
deviceaddress = NAND_DEVICE2;
}
- /* Update the NAND controller state */
+ /* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Send NAND reset command */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
-
-
- /* Update the NAND controller state */
+
+
+ /* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
- __HAL_UNLOCK(hnand);
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Configure the device: Enter the physical parameters of the device
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
+{
+ hnand->Config.PageSize = pDeviceConfig->PageSize;
+ hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize;
+ hnand->Config.BlockSize = pDeviceConfig->BlockSize;
+ hnand->Config.BlockNbr = pDeviceConfig->BlockNbr;
+ hnand->Config.PlaneSize = pDeviceConfig->PlaneSize;
+ hnand->Config.PlaneNbr = pDeviceConfig->PlaneNbr;
+ hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable;
return HAL_OK;
+}
+
+/**
+ * @brief Read Page(s) from NAND memory block (8-bits addressing)
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to destination read buffer
+ * @param NumPageToRead number of pages to read from block
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
+{
+ __IO uint32_t index = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, numPagesRead = 0U, nandaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Page(s) read loop */
+ while((NumPageToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
+ /* update the buffer size */
+ size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
+
+ /* Send read page command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+
+ /* Cards with page size <= 512 bytes */
+ if((hnand->Config.PageSize) <= 512U)
+ {
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+
+ /* Check if an extra command is needed for reading pages */
+ if(hnand->Config.ExtraCommandEnable == ENABLE)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Go back to read mode */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
+ __DSB();
+ }
+
+ /* Get Data into Buffer */
+ for(; index < size; index++)
+ {
+ *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
+ }
+
+ /* Increment read pages number */
+ numPagesRead++;
+
+ /* Decrement pages to read */
+ NumPageToRead--;
+
+ /* Increment the NAND address */
+ nandaddress = (uint32_t)(nandaddress + 1U);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
}
/**
- * @brief Read Page(s) from NAND memory block
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @brief Read Page(s) from NAND memory block (16-bits addressing)
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param pAddress: pointer to NAND address structure
- * @param pBuffer: pointer to destination read buffer
- * @param NumPageToRead: number of pages to read from block
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to destination read buffer. pBuffer should be 16bits aligned
+ * @param NumPageToRead number of pages to read from block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
+HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
{
__IO uint32_t index = 0U;
- uint32_t deviceaddress = 0U, size = 0U, numpagesread = 0U, addressstatus = NAND_VALID_ADDRESS;
- NAND_AddressTypeDef nandaddress;
- uint32_t addressoffset = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, numPagesRead = 0U, nandaddress = 0U;
/* Process Locked */
__HAL_LOCK(hnand);
@@ -471,50 +624,89 @@ HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressType
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
- /* Save the content of pAddress as it will be modified */
- nandaddress.Block = pAddress->Block;
- nandaddress.Page = pAddress->Page;
- nandaddress.Zone = pAddress->Zone;
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Page(s) read loop */
- while((NumPageToRead != 0U) && (addressstatus == NAND_VALID_ADDRESS))
- {
+ while((NumPageToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
/* update the buffer size */
- size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpagesread);
-
- /* Get the address offset */
- addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
+ size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
/* Send read page command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
-
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
-
- /* for 512 and 1 GB devices, 4th cycle is required */
- if(hnand->Info.BlockNbr >= 1024U)
+ __DSB();
+
+ /* Cards with page size <= 512 bytes */
+ if((hnand->Config.PageSize) <= 512U)
+ {
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
{
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
}
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+
+ if(hnand->Config.ExtraCommandEnable == ENABLE)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+ /* Go back to read mode */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
+ }
+
/* Get Data into Buffer */
for(; index < size; index++)
{
- *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
+ *(uint16_t *)pBuffer++ = *(uint16_t *)deviceaddress;
}
/* Increment read pages number */
- numpagesread++;
+ numPagesRead++;
/* Decrement pages to read */
NumPageToRead--;
/* Increment the NAND address */
- addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
+ nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
@@ -524,25 +716,22 @@ HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressType
__HAL_UNLOCK(hnand);
return HAL_OK;
-
}
/**
- * @brief Write Page(s) to NAND memory block
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @brief Write Page(s) to NAND memory block (8-bits addressing)
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param pAddress: pointer to NAND address structure
- * @param pBuffer: pointer to source buffer to write
- * @param NumPageToWrite: number of pages to write to block
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write
+ * @param NumPageToWrite : number of pages to write to block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
+HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
{
- __IO uint32_t index = 0U;
+ __IO uint32_t index = 0U;
uint32_t tickstart = 0U;
- uint32_t deviceaddress = 0U , size = 0U, numpageswritten = 0U, addressstatus = NAND_VALID_ADDRESS;
- NAND_AddressTypeDef nandaddress;
- uint32_t addressoffset = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, numPagesWritten = 0U, nandaddress = 0U;
/* Process Locked */
__HAL_LOCK(hnand);
@@ -566,35 +755,58 @@ HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTyp
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
- /* Save the content of pAddress as it will be modified */
- nandaddress.Block = pAddress->Block;
- nandaddress.Page = pAddress->Page;
- nandaddress.Zone = pAddress->Zone;
-
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
/* Page(s) write loop */
- while((NumPageToWrite != 0U) && (addressstatus == NAND_VALID_ADDRESS))
- {
+ while((NumPageToWrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
/* update the buffer size */
- size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpageswritten);
+ size = hnand->Config.PageSize + ((hnand->Config.PageSize) * numPagesWritten);
- /* Get the address offset */
- addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
-
/* Send write page command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
-
- /* for 512 and 1 GB devices, 4th cycle is required */
- if(hnand->Info.BlockNbr >= 1024U)
+ /* Cards with page size <= 512 bytes */
+ if((hnand->Config.PageSize) <= 512U)
+ {
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
{
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ __DSB();
+ }
}
+
/* Write data to memory */
for(; index < size; index++)
{
@@ -603,56 +815,55 @@ HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTyp
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
- /* Get tick */
- tickstart = HAL_GetTick();
-
/* Read status until NAND is ready */
while(HAL_NAND_Read_Status(hnand) != NAND_READY)
{
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
{
return HAL_TIMEOUT;
- }
- }
+ }
+ }
/* Increment written pages number */
- numpageswritten++;
+ numPagesWritten++;
/* Decrement pages to write */
NumPageToWrite--;
/* Increment the NAND address */
- addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
+ nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
- __HAL_UNLOCK(hnand);
+ __HAL_UNLOCK(hnand);
return HAL_OK;
}
/**
- * @brief Read Spare area(s) from NAND memory
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @brief Write Page(s) to NAND memory block (16-bits addressing)
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param pAddress: pointer to NAND address structure
- * @param pBuffer: pointer to source buffer to write
- * @param NumSpareAreaToRead: Number of spare area to read
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned
+ * @param NumPageToWrite : number of pages to write to block
* @retval HAL status
-*/
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
+ */
+HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
{
- __IO uint32_t index = 0U;
- uint32_t deviceaddress = 0U, size = 0U, num_spare_area_read = 0U, addressstatus = NAND_VALID_ADDRESS;
- NAND_AddressTypeDef nandaddress;
- uint32_t addressoffset = 0U;
+ __IO uint32_t index = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, numPagesWritten = 0U, nandaddress = 0U;
/* Process Locked */
__HAL_LOCK(hnand);
-
+
/* Check the NAND controller state */
if(hnand->State == HAL_NAND_STATE_BUSY)
{
@@ -669,83 +880,116 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addres
deviceaddress = NAND_DEVICE2;
}
- /* Update the NAND controller state */
- hnand->State = HAL_NAND_STATE_BUSY;
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
- /* Save the content of pAddress as it will be modified */
- nandaddress.Block = pAddress->Block;
- nandaddress.Page = pAddress->Page;
- nandaddress.Zone = pAddress->Zone;
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
- /* Spare area(s) read loop */
- while((NumSpareAreaToRead != 0U) && (addressstatus == NAND_VALID_ADDRESS))
- {
+ /* Page(s) write loop */
+ while((NumPageToWrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
/* update the buffer size */
- size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_read);
-
- /* Get the address offset */
- addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
-
- /* Send read spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+ size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesWritten);
+
+ /* Send write page command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ __DSB();
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+ __DSB();
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
+ /* Cards with page size <= 512 bytes */
+ if((hnand->Config.PageSize) <= 512U)
+ {
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
- /* for 512 and 1 GB devices, 4th cycle is required */
- if(hnand->Info.BlockNbr >= 1024U)
+ /* Write data to memory */
+ for(; index < size; index++)
{
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
- }
-
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+ *(__IO uint16_t *)deviceaddress = *(uint16_t *)pBuffer++;
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
- /* Get Data into Buffer */
- for ( ;index < size; index++)
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
{
- *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
- }
+ /* Get tick */
+ tickstart = HAL_GetTick();
- /* Increment read spare areas number */
- num_spare_area_read++;
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Increment written pages number */
+ numPagesWritten++;
- /* Decrement spare areas to read */
- NumSpareAreaToRead--;
+ /* Decrement pages to write */
+ NumPageToWrite--;
/* Increment the NAND address */
- addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
+ nandaddress = (uint32_t)(nandaddress + 1U);
}
- /* Update the NAND controller state */
+ /* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
- __HAL_UNLOCK(hnand);
-
- return HAL_OK;
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
}
/**
- * @brief Write Spare area(s) to NAND memory
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @brief Read Spare area(s) from NAND memory
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param pAddress: pointer to NAND address structure
- * @param pBuffer: pointer to source buffer to write
- * @param NumSpareAreaTowrite: number of spare areas to write to block
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write
+ * @param NumSpareAreaToRead Number of spare area to read
* @retval HAL status
- */
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
+*/
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
{
__IO uint32_t index = 0U;
uint32_t tickstart = 0U;
- uint32_t deviceaddress = 0U, size = 0U, num_spare_area_written = 0U, addressstatus = NAND_VALID_ADDRESS;
- NAND_AddressTypeDef nandaddress;
- uint32_t addressoffset = 0U;
-
+ uint32_t deviceaddress = 0U, size = 0U, numSpareAreaRead = 0U, nandaddress = 0U, columnaddress = 0U;
+
/* Process Locked */
- __HAL_LOCK(hnand);
+ __HAL_LOCK(hnand);
/* Check the NAND controller state */
if(hnand->State == HAL_NAND_STATE_BUSY)
@@ -763,36 +1007,335 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addre
deviceaddress = NAND_DEVICE2;
}
- /* Update the FMC_NAND controller state */
+ /* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
-
- /* Save the content of pAddress as it will be modified */
- nandaddress.Block = pAddress->Block;
- nandaddress.Page = pAddress->Page;
- nandaddress.Zone = pAddress->Zone;
- /* Spare area(s) write loop */
- while((NumSpareAreaTowrite != 0U) && (addressstatus == NAND_VALID_ADDRESS))
- {
- /* update the buffer size */
- size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_written);
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Column in page address */
+ columnaddress = COLUMN_ADDRESS(hnand);
+
+ /* Spare area(s) read loop */
+ while((NumSpareAreaToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
+ /* update the buffer size */
+ size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
- /* Get the address offset */
- addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
+ /* Cards with page size <= 512 bytes */
+ if((hnand->Config.PageSize) <= 512U)
+ {
+ /* Send read spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ /* Send read spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
- /* Send write Spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+
+ if(hnand->Config.ExtraCommandEnable == ENABLE)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Go back to read mode */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
+ }
+
+ /* Get Data into Buffer */
+ for(; index < size; index++)
+ {
+ *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
+ }
+
+ /* Increment read spare areas number */
+ numSpareAreaRead++;
+
+ /* Decrement spare areas to read */
+ NumSpareAreaToRead--;
+
+ /* Increment the NAND address */
+ nandaddress = (uint32_t)(nandaddress + 1U);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
+ return HAL_OK;
+}
+
+/**
+ * @brief Read Spare area(s) from NAND memory (16-bits addressing)
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
+ * @param NumSpareAreaToRead Number of spare area to read
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
+{
+ __IO uint32_t index = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, numSpareAreaRead = 0U, nandaddress = 0U, columnaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Column in page address */
+ columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
- /* for 512 and 1 GB devices, 4th cycle is required */
- if(hnand->Info.BlockNbr >= 1024U)
+ /* Spare area(s) read loop */
+ while((NumSpareAreaToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
+ /* update the buffer size */
+ size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
+
+ /* Cards with page size <= 512 bytes */
+ if((hnand->Config.PageSize) <= 512U)
+ {
+ /* Send read spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
{
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
+ /* Send read spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+
+ if(hnand->Config.ExtraCommandEnable == ENABLE)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Go back to read mode */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
+ }
+
+ /* Get Data into Buffer */
+ for(; index < size; index++)
+ {
+ *(uint16_t *)pBuffer++ = *(uint16_t *)deviceaddress;
+ }
+
+ /* Increment read spare areas number */
+ numSpareAreaRead++;
+
+ /* Decrement spare areas to read */
+ NumSpareAreaToRead--;
+
+ /* Increment the NAND address */
+ nandaddress = (uint32_t)(nandaddress + 1U);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Write Spare area(s) to NAND memory
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write
+ * @param NumSpareAreaTowrite : number of spare areas to write to block
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
+{
+ __IO uint32_t index = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, numSpareAreaWritten = 0U, nandaddress = 0U, columnaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the FMC_NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* Page address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Column in page address */
+ columnaddress = COLUMN_ADDRESS(hnand);
+
+ /* Spare area(s) write loop */
+ while((NumSpareAreaTowrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
+ /* update the buffer size */
+ size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
+
+ /* Cards with page size <= 512 bytes */
+ if((hnand->Config.PageSize) <= 512U)
+ {
+ /* Send write Spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ /* Send write Spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
}
/* Write data to memory */
@@ -805,24 +1348,24 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addre
/* Get tick */
tickstart = HAL_GetTick();
-
+
/* Read status until NAND is ready */
while(HAL_NAND_Read_Status(hnand) != NAND_READY)
{
if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
{
return HAL_TIMEOUT;
- }
+ }
}
/* Increment written spare areas number */
- num_spare_area_written++;
+ numSpareAreaWritten++;
/* Decrement spare areas to write */
NumSpareAreaTowrite--;
/* Increment the NAND address */
- addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
+ nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
@@ -831,14 +1374,146 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addre
/* Process unlocked */
__HAL_UNLOCK(hnand);
+ return HAL_OK;
+}
+
+/**
+ * @brief Write Spare area(s) to NAND memory (16-bits addressing)
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
+ * @param NumSpareAreaTowrite : number of spare areas to write to block
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
+{
+ __IO uint32_t index = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, numSpareAreaWritten = 0U, nandaddress = 0U, columnaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the FMC_NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Column in page address */
+ columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
+
+ /* Spare area(s) write loop */
+ while((NumSpareAreaTowrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
+ /* update the buffer size */
+ size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
+
+ /* Cards with page size <= 512 bytes */
+ if((hnand->Config.PageSize) <= 512U)
+ {
+ /* Send write Spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ /* Send write Spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+
+ /* Write data to memory */
+ for(; index < size; index++)
+ {
+ *(__IO uint16_t *)deviceaddress = *(uint16_t *)pBuffer++;
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Increment written spare areas number */
+ numSpareAreaWritten++;
+
+ /* Decrement spare areas to write */
+ NumSpareAreaTowrite--;
+
+ /* Increment the NAND address */
+ nandaddress = (uint32_t)(nandaddress + 1U);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
return HAL_OK;
}
/**
* @brief NAND memory Block erase
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param pAddress: pointer to NAND address structure
+ * @param pAddress pointer to NAND address structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
@@ -874,13 +1549,7 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTy
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
-
- /* for 512 and 1 GB devices, 4th cycle is required */
- if(hnand->Info.BlockNbr >= 1024U)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
- }
-
+
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
/* Update the NAND controller state */
@@ -894,13 +1563,13 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTy
{
if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
{
- /* Process unlocked */
- __HAL_UNLOCK(hnand);
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
return HAL_TIMEOUT;
}
-}
-
+ }
+
/* Process unlocked */
__HAL_UNLOCK(hnand);
@@ -909,7 +1578,7 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTy
/**
* @brief NAND memory read status
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval NAND status
*/
@@ -949,9 +1618,9 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
/**
* @brief Increment the NAND memory address
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param pAddress: pointer to NAND address structure
+ * @param pAddress pointer to NAND address structure
* @retval The new status of the increment address operation. It can be:
* - NAND_VALID_ADDRESS: When the new address is valid address
* - NAND_INVALID_ADDRESS: When the new address is invalid address
@@ -964,17 +1633,17 @@ uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pA
pAddress->Page++;
/* Check NAND address is valid */
- if(pAddress->Page == hnand->Info.BlockSize)
+ if(pAddress->Page == hnand->Config.BlockSize)
{
pAddress->Page = 0U;
pAddress->Block++;
- if(pAddress->Block == hnand->Info.ZoneSize)
+ if(pAddress->Block == hnand->Config.PlaneSize)
{
pAddress->Block = 0U;
- pAddress->Zone++;
+ pAddress->Plane++;
- if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr))
+ if(pAddress->Plane == (hnand->Config.PlaneNbr))
{
status = NAND_INVALID_ADDRESS;
}
@@ -1005,7 +1674,7 @@ uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pA
/**
* @brief Enables dynamically NAND ECC feature.
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL status
*/
@@ -1026,16 +1695,16 @@ HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
/* Update the NAND state */
hnand->State = HAL_NAND_STATE_READY;
- return HAL_OK;
+ return HAL_OK;
}
/**
* @brief Disables dynamically FMC_NAND ECC feature.
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
+HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
{
/* Check the NAND controller state */
if(hnand->State == HAL_NAND_STATE_BUSY)
@@ -1057,10 +1726,10 @@ HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
/**
* @brief Disables dynamically NAND ECC feature.
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param ECCval: pointer to ECC value
- * @param Timeout: maximum timeout to wait
+ * @param ECCval pointer to ECC value
+ * @param Timeout maximum timeout to wait
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
@@ -1084,7 +1753,7 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval,
return status;
}
-
+
/**
* @}
*/
@@ -1107,7 +1776,7 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval,
/**
* @brief return the NAND state
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL state
*/
@@ -1120,49 +1789,6 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
* @}
*/
-/**
- * @}
- */
-
-/** @addtogroup NAND_Private_Functions
- * @{
- */
-
-/**
- * @brief Increment the NAND memory address.
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param Address: address to be incremented.
- * @retval The new status of the increment address operation. It can be:
- * - NAND_VALID_ADDRESS: When the new address is valid address
- * - NAND_INVALID_ADDRESS: When the new address is invalid address
- */
-static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef* Address)
-{
- uint32_t status = NAND_VALID_ADDRESS;
-
- Address->Page++;
-
- if(Address->Page == hnand->Info.BlockSize)
- {
- Address->Page = 0U;
- Address->Block++;
-
- if(Address->Block == hnand->Info.ZoneSize)
- {
- Address->Block = 0U;
- Address->Zone++;
-
- if(Address->Zone == hnand->Info.BlockNbr)
- {
- status = NAND_INVALID_ADDRESS;
- }
- }
- }
-
- return (status);
-}
-
/**
* @}
*/
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_nor.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_nor.c
index 7dc621a3ab..18d13958b0 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_nor.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_nor.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_nor.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief NOR HAL module driver.
* This file provides a generic firmware to drive NOR memories mounted
* as external device.
@@ -179,10 +177,10 @@ static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
/**
* @brief Perform the NOR memory Initialization sequence
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
- * @param Timing: pointer to NOR control timing structure
- * @param ExtTiming: pointer to NOR extended mode timing structure
+ * @param Timing pointer to NOR control timing structure
+ * @param ExtTiming pointer to NOR extended mode timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
@@ -232,7 +230,7 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe
/**
* @brief Perform NOR memory De-Initialization sequence
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval HAL status
*/
@@ -255,7 +253,7 @@ HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
/**
* @brief NOR MSP Init
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval None
*/
@@ -271,7 +269,7 @@ __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
/**
* @brief NOR MSP DeInit
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval None
*/
@@ -287,9 +285,9 @@ __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
/**
* @brief NOR MSP Wait fro Ready/Busy signal
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
- * @param Timeout: Maximum timeout value
+ * @param Timeout Maximum timeout value
* @retval None
*/
__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
@@ -323,9 +321,9 @@ __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
/**
* @brief Read NOR flash IDs
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
- * @param pNOR_ID: pointer to NOR ID structure
+ * @param pNOR_ID pointer to NOR ID structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
@@ -384,7 +382,7 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I
/**
* @brief Returns the NOR memory to Read mode.
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval HAL status
*/
@@ -432,10 +430,10 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
/**
* @brief Read data from NOR memory
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
- * @param pAddress: pointer to Device address
- * @param pData: pointer to read data
+ * @param pAddress pointer to Device address
+ * @param pData pointer to read data
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
@@ -491,10 +489,10 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint
/**
* @brief Program data to NOR memory
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
- * @param pAddress: Device address
- * @param pData: pointer to the data to write
+ * @param pAddress Device address
+ * @param pData pointer to the data to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
@@ -550,12 +548,12 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u
/**
* @brief Reads a block of data from the FMC NOR memory.
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
- * @param uwAddress: NOR memory internal address to read from.
- * @param pData: pointer to the buffer that receives the data read from the
+ * @param uwAddress NOR memory internal address to read from.
+ * @param pData pointer to the buffer that receives the data read from the
* NOR memory.
- * @param uwBufferSize: number of Half word to read.
+ * @param uwBufferSize number of Half word to read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
@@ -617,13 +615,13 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress
/**
* @brief Writes a half-word buffer to the FMC NOR memory. This function
* must be used only with S29GL128P NOR memory.
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
- * @param uwAddress: NOR memory internal address from which the data
+ * @param uwAddress NOR memory internal address from which the data
* @note Some NOR memory need Address aligned to xx bytes (can be aligned to
* 64 bytes boundary for example).
- * @param pData: pointer to source data buffer.
- * @param uwBufferSize: number of Half words to write.
+ * @param pData pointer to source data buffer.
+ * @param uwBufferSize number of Half words to write.
* @note The maximum buffer size allowed is NOR memory dependent
* (can be 64 Bytes max for example).
* @retval HAL status
@@ -702,10 +700,10 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr
/**
* @brief Erase the specified block of the NOR memory
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
- * @param BlockAddress: Block to erase address
- * @param Address: Device address
+ * @param BlockAddress Block to erase address
+ * @param Address Device address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
@@ -762,9 +760,9 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd
/**
* @brief Erase the entire NOR chip.
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
- * @param Address: Device address
+ * @param Address Device address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
@@ -820,9 +818,9 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
/**
* @brief Read NOR flash CFI IDs
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
- * @param pNOR_CFI: pointer to NOR CFI IDs structure
+ * @param pNOR_CFI pointer to NOR CFI IDs structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
@@ -898,7 +896,7 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR
/**
* @brief Enables dynamically NOR write operation.
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval HAL status
*/
@@ -921,7 +919,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
/**
* @brief Disables dynamically NOR write operation.
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval HAL status
*/
@@ -966,7 +964,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
/**
* @brief return the NOR controller state
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval NOR controller state
*/
@@ -977,10 +975,10 @@ HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
/**
* @brief Returns the NOR operation status.
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
- * @param Address: Device address
- * @param Timeout: NOR progamming Timeout
+ * @param Address Device address
+ * @param Timeout NOR progamming Timeout
* @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
* or HAL_NOR_STATUS_TIMEOUT
*/
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_opamp.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_opamp.c
index ceb20f5671..ca3bfa7db4 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_opamp.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_opamp.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_opamp.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief OPAMP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the operational amplifiers (OPAMP1,...OPAMP4)
@@ -170,14 +168,14 @@
|-----------------|--------|--------|--------|--------|--------|
| | No conn| X | X | X | X |
| Inverting Input | VM0 | PC5 | PC5 | PB10 | PB10 |
- | (1U) | VM1 | PA3 | PA5 | PB2 | PD8 |
+ | (1) | VM1 | PA3 | PA5 | PB2 | PD8 |
|-----------------|--------|--------|--------|--------|--------|
| | VP0 | PA1 | PA7 | PB0 | PB13 |
| Non Inverting | VP1 | PA7 | PD14 | PB13 | PD11 |
| Input | VP2 | PA3 | PB0 | PA1 | PA4 |
| | VP3 | PA5 | PB14 | PA5 | PB11 |
+--------------------------------------------------------------+
- (1U): NA in follower mode.
+ (1): NA in follower mode.
Table 2. OPAMPs outputs for the STM32F3 devices:
+--------------------------------------------------------------+
@@ -245,7 +243,7 @@
* parameters in the OPAMP_InitTypeDef and create the associated handle.
* @note If the selected opamp is locked, initialization can't be performed.
* To unlock the configuration, perform a system reset.
- * @param hopamp: OPAMP handle
+ * @param hopamp OPAMP handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
@@ -376,7 +374,7 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
* @brief DeInitializes the OPAMP peripheral
* @note Deinitialization can't be performed if the OPAMP configuration is locked.
* To unlock the configuration, perform a system reset.
- * @param hopamp: OPAMP handle
+ * @param hopamp OPAMP handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp)
@@ -416,17 +414,17 @@ HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp)
/* The OPAMP state is NOT updated */
}
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hopamp);
}
- /* Process unlocked */
- __HAL_UNLOCK(hopamp);
-
return status;
}
/**
* @brief Initializes the OPAMP MSP.
- * @param hopamp: OPAMP handle
+ * @param hopamp OPAMP handle
* @retval None
*/
__weak void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp)
@@ -443,7 +441,7 @@ __weak void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp)
/**
* @brief DeInitializes OPAMP MSP.
- * @param hopamp: OPAMP handle
+ * @param hopamp OPAMP handle
* @retval None
*/
__weak void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp)
@@ -479,7 +477,7 @@ __weak void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp)
/**
* @brief Start the opamp
- * @param hopamp: OPAMP handle
+ * @param hopamp OPAMP handle
* @retval HAL status
*/
@@ -520,7 +518,7 @@ HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp)
/**
* @brief Stop the opamp
- * @param hopamp: OPAMP handle
+ * @param hopamp OPAMP handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp)
@@ -760,7 +758,7 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp)
/**
* @brief Lock the selected opamp configuration.
- * @param hopamp: OPAMP handle
+ * @param hopamp OPAMP handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp)
@@ -815,7 +813,7 @@ HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp)
/**
* @brief Return the OPAMP state
- * @param hopamp: OPAMP handle
+ * @param hopamp OPAMP handle
* @retval HAL state
*/
HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp)
@@ -834,8 +832,8 @@ HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp)
/**
* @brief Return the OPAMP factory trimming value
- * @param hopamp: OPAMP handle
- * @param trimmingoffset: Trimming offset (P or N)
+ * @param hopamp OPAMP handle
+ * @param trimmingoffset Trimming offset (P or N)
* @retval Trimming value (P or N): range: 0->31
* or OPAMP_FACTORYTRIMMING_DUMMY if trimming value is not available
*/
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_opamp_ex.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_opamp_ex.c
index 6d04781871..e6929f1a24 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_opamp_ex.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_opamp_ex.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_opamp_ex.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief Extended OPAMP HAL module driver.
*
* This file provides firmware functions to manage the following
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pccard.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pccard.c
index 083035aa9b..cbfe452c03 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pccard.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pccard.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_pccard.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief PCCARD HAL module driver.
* This file provides a generic firmware to drive PCCARD memories mounted
* as external device.
@@ -131,11 +129,11 @@
/**
* @brief Perform the PCCARD memory Initialization sequence
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
- * @param ComSpaceTiming: Common space timing structure
- * @param AttSpaceTiming: Attribute space timing structure
- * @param IOSpaceTiming: IO space timing structure
+ * @param ComSpaceTiming Common space timing structure
+ * @param AttSpaceTiming Attribute space timing structure
+ * @param IOSpaceTiming IO space timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming)
@@ -182,7 +180,7 @@ HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_Ti
/**
* @brief Perform the PCCARD memory De-initialization sequence
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval HAL status
*/
@@ -205,7 +203,7 @@ HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard)
/**
* @brief PCCARD MSP Init
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval None
*/
@@ -221,7 +219,7 @@ __weak void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard)
/**
* @brief PCCARD MSP DeInit
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval None
*/
@@ -255,10 +253,10 @@ __weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard)
/**
* @brief Read Compact Flash's ID.
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
- * @param CompactFlash_ID: Compact flash ID structure.
- * @param pStatus: pointer to compact flash status
+ * @param CompactFlash_ID Compact flash ID structure.
+ * @param pStatus pointer to compact flash status
* @retval HAL status
*
*/
@@ -318,11 +316,11 @@ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t Comp
/**
* @brief Read sector from PCCARD memory
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
- * @param pBuffer: pointer to destination read buffer
- * @param SectorAddress: Sector address to read
- * @param pStatus: pointer to CF status
+ * @param pBuffer pointer to destination read buffer
+ * @param SectorAddress Sector address to read
+ * @param pStatus pointer to CF status
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
@@ -394,11 +392,11 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t
/**
* @brief Write sector to PCCARD memory
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
- * @param pBuffer: pointer to source write buffer
- * @param SectorAddress: Sector address to write
- * @param pStatus: pointer to CF status
+ * @param pBuffer pointer to source write buffer
+ * @param SectorAddress Sector address to write
+ * @param pStatus pointer to CF status
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
@@ -468,10 +466,10 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_
/**
* @brief Erase sector from PCCARD memory
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
- * @param SectorAddress: Sector address to erase
- * @param pStatus: pointer to CF status
+ * @param SectorAddress Sector address to erase
+ * @param pStatus pointer to CF status
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus)
@@ -527,7 +525,7 @@ HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16
/**
* @brief Reset the PCCARD memory
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval HAL status
*/
@@ -565,7 +563,7 @@ HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard)
/**
* @brief This function handles PCCARD device interrupt request.
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval HAL status
*/
@@ -615,7 +613,7 @@ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard)
/**
* @brief PCCARD interrupt feature callback
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval None
*/
@@ -650,7 +648,7 @@ __weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard)
/**
* @brief return the PCCARD controller state
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval HAL state
*/
@@ -661,7 +659,7 @@ HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard)
/**
* @brief Get the compact flash memory status
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval New status of the CF operation. This parameter can be:
* - CompactFlash_TIMEOUT_ERROR: when the previous operation generate
@@ -698,7 +696,7 @@ HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard)
/**
* @brief Reads the Compact Flash memory status using the Read status command
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval The status of the Compact Flash memory. This parameter can be:
* - CompactFlash_BUSY: when memory is busy
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pcd.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pcd.c
index 8f3028da10..f8b6ccb0e9 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pcd.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pcd.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_pcd.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@@ -134,7 +132,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
/**
* @brief Initializes the PCD according to the specified
* parameters in the PCD_InitTypeDef and create the associated handle.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
@@ -215,7 +213,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
/**
* @brief DeInitializes the PCD peripheral
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
@@ -241,7 +239,7 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
/**
* @brief Initializes the PCD MSP.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
@@ -256,7 +254,7 @@ __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
/**
* @brief DeInitializes PCD MSP.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
@@ -290,7 +288,7 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
/**
* @brief Start the USB device.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
@@ -303,7 +301,7 @@ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
/**
* @brief Stop the USB device.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
@@ -335,7 +333,7 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
*/
/**
* @brief This function handles PCD Endpoint interrupt request.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL status
*/
static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
@@ -393,7 +391,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
{
/* Get SETUP Packet*/
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
- PCD_ReadPMA(hpcd->Instance, (uint8_t*)hpcd->Setup ,ep->pmaadress , ep->xfer_count);
+ PCD_ReadPMA(hpcd->Instance, (uint8_t*)(void*)hpcd->Setup ,ep->pmaadress , ep->xfer_count);
/* SETUP bit kept frozen while CTR_RX = 1U*/
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
@@ -552,12 +550,11 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
/**
* @brief This function handles PCD interrupt request.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL status
*/
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
- uint32_t wInterrupt_Mask = 0U;
if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR))
{
@@ -584,27 +581,22 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP))
{
- hpcd->Instance->CNTR &= (uint16_t)(~(USB_CNTR_LPMODE));
+ hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LPMODE);
+ hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
- /*set wInterrupt_Mask global variable*/
- wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
- | USB_CNTR_ESOFM | USB_CNTR_RESETM;
-
- /*Set interrupt mask*/
- hpcd->Instance->CNTR = wInterrupt_Mask;
-
HAL_PCD_ResumeCallback(hpcd);
-
+
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
}
if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SUSP))
- {
- /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
-
+ {
/* Force low-power mode in the macrocell */
hpcd->Instance->CNTR |= USB_CNTR_FSUSP;
+
+ /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
+
hpcd->Instance->CNTR |= USB_CNTR_LPMODE;
if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0U)
{
@@ -627,8 +619,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
/**
* @brief Data out stage callbacks
- * @param hpcd: PCD handle
- * @param epnum: endpoint number
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
* @retval None
*/
__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
@@ -644,8 +636,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
/**
* @brief Data IN stage callbacks
- * @param hpcd: PCD handle
- * @param epnum: endpoint number
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
* @retval None
*/
__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
@@ -660,7 +652,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
}
/**
* @brief Setup stage callback
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
@@ -675,7 +667,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
/**
* @brief USB Start Of Frame callbacks
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
@@ -690,7 +682,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
/**
* @brief USB Reset callbacks
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
@@ -705,7 +697,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
/**
* @brief Suspend event callbacks
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
@@ -720,7 +712,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
/**
* @brief Resume event callbacks
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
@@ -735,8 +727,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
/**
* @brief Incomplete ISO OUT callbacks
- * @param hpcd: PCD handle
- * @param epnum: endpoint number
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
* @retval None
*/
__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
@@ -752,8 +744,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
/**
* @brief Incomplete ISO IN callbacks
- * @param hpcd: PCD handle
- * @param epnum: endpoint number
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
* @retval None
*/
__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
@@ -769,7 +761,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
/**
* @brief Connection event callbacks
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
@@ -784,7 +776,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
/**
* @brief Disconnection event callbacks
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
@@ -817,7 +809,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
/**
* @brief Connect the USB device
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
@@ -833,7 +825,7 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
/**
* @brief Disconnect the USB device
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
@@ -849,8 +841,8 @@ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
/**
* @brief Set the USB Device address
- * @param hpcd: PCD handle
- * @param address: new device address
+ * @param hpcd PCD handle
+ * @param address new device address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
@@ -872,10 +864,10 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
}
/**
* @brief Open and configure an endpoint
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
- * @param ep_mps: endpoint max packet size
- * @param ep_type: endpoint type
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @param ep_mps endpoint max packet size
+ * @param ep_type endpoint type
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
@@ -980,8 +972,8 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint
/**
* @brief Deactivate an endpoint
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
@@ -1051,10 +1043,10 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
/**
* @brief Receive an amount of data
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
- * @param pBuf: pointer to the reception buffer
- * @param len: amount of data to be received
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @param pBuf pointer to the reception buffer
+ * @param len amount of data to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
@@ -1070,9 +1062,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
ep->xfer_count = 0U;
ep->is_in = 0U;
ep->num = ep_addr & 0x7FU;
-
- __HAL_LOCK(hpcd);
-
+
/* Multi packet transfer*/
if (ep->xfer_len > ep->maxpacket)
{
@@ -1098,16 +1088,14 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
}
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
-
- __HAL_UNLOCK(hpcd);
-
+
return HAL_OK;
}
/**
* @brief Get Received Data Size
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
* @retval Data Size
*/
uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
@@ -1116,10 +1104,10 @@ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
}
/**
* @brief Send an amount of data
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
- * @param pBuf: pointer to the transmission buffer
- * @param len: amount of data to be sent
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @param pBuf pointer to the transmission buffer
+ * @param len amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
@@ -1135,9 +1123,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
ep->xfer_count = 0U;
ep->is_in = 1U;
ep->num = ep_addr & 0x7FU;
-
- __HAL_LOCK(hpcd);
-
+
/*Multi packet transfer*/
if (ep->xfer_len > ep->maxpacket)
{
@@ -1172,16 +1158,14 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
}
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID)
-
- __HAL_UNLOCK(hpcd);
-
+
return HAL_OK;
}
/**
* @brief Set a STALL condition over an endpoint
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
@@ -1226,8 +1210,8 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
/**
* @brief Clear a STALL condition over in an endpoint
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
@@ -1266,8 +1250,8 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
/**
* @brief Flush an endpoint
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
@@ -1277,24 +1261,24 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
/**
* @brief HAL_PCD_ActivateRemoteWakeup : active remote wakeup signalling
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
{
hpcd->Instance->CNTR |= USB_CNTR_RESUME;
- return HAL_OK;
+ return HAL_OK;
}
/**
* @brief HAL_PCD_DeActivateRemoteWakeup : de-active remote wakeup signalling
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
{
hpcd->Instance->CNTR &=~((uint32_t)USB_CNTR_RESUME);
- return HAL_OK;
+ return HAL_OK;
}
/**
@@ -1318,7 +1302,7 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
/**
* @brief Return the PCD state
- * @param hpcd : PCD handle
+ * @param hpcd PCD handle
* @retval HAL state
*/
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pcd_ex.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pcd_ex.c
index ea61f7acaa..9919743dfa 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pcd_ex.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pcd_ex.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_pcd_ex.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief Extended PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@@ -85,12 +83,12 @@
/**
* @brief Configure PMA for EP
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
- * @param ep_kind: endpoint Kind
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @param ep_kind endpoint Kind
* @arg USB_SNG_BUF: Single Buffer used
* @arg USB_DBL_BUF: Double Buffer used
- * @param pmaadress: EP address in The PMA: In case of single buffer endpoint
+ * @param pmaadress EP address in The PMA: In case of single buffer endpoint
* this parameter is 16-bit value providing the address
* in PMA allocated to endpoint.
* In case of double buffer endpoint this parameter
@@ -191,20 +189,24 @@ void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, u
*/
void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
{
- uint32_t n = ((uint32_t)((uint32_t)wNBytes + 1U)) >> 1U;
+ uint32_t n = (uint32_t)wNBytes >> 1U;
uint32_t i;
- uint32_t *pdwVal;
-
- pdwVal = (uint32_t *)((uint32_t)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400U));
- uint32_t tmp = *pdwVal++;
- *pbUsrBuf++ = (uint16_t)((tmp >> 0) & 0xFF);
- *pbUsrBuf++ = (uint16_t)((tmp >> 8) & 0xFF);
-
+ uint16_t *pdwVal;
+ uint32_t temp;
+ pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400U));
- for (i = n; i != 0; i--)
+ for (i = n; i != 0U; i--)
{
- *(uint16_t*)((uint32_t)pbUsrBuf++) = *pdwVal++;
- pbUsrBuf++;
+ temp = *pdwVal++;
+ *pbUsrBuf++ = ((temp >> 0) & 0xFF);
+ *pbUsrBuf++ = ((temp >> 8) & 0xFF);
+ pdwVal++;
+ }
+
+ if (wNBytes % 2)
+ {
+ temp = *pdwVal++;
+ *pbUsrBuf++ = ((temp >> 0) & 0xFF);
}
}
#endif /* STM32F303xC || */
@@ -249,14 +251,23 @@ void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, u
*/
void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
{
- uint32_t n = ((uint32_t)((uint32_t)wNBytes + 1U)) >> 1U;
+ uint32_t n = (uint32_t)wNBytes >> 1U;
uint32_t i;
uint16_t *pdwVal;
+ uint32_t temp;
pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr + (uint32_t)USBx + 0x400U));
+
for (i = n; i != 0U; i--)
{
- *(uint16_t*)((uint32_t)pbUsrBuf++) = *pdwVal++;
- pbUsrBuf++;
+ temp = *pdwVal++;
+ *pbUsrBuf++ = ((temp >> 0) & 0xFF);
+ *pbUsrBuf++ = ((temp >> 8) & 0xFF);
+ }
+
+ if (wNBytes % 2)
+ {
+ temp = *pdwVal++;
+ *pbUsrBuf++ = ((temp >> 0) & 0xFF);
}
}
#endif /* STM32F302xE || STM32F303xE || */
@@ -276,8 +287,8 @@ void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, ui
*/
/**
* @brief Software Device Connection
- * @param hpcd: PCD handle
- * @param state: Device state
+ * @param hpcd PCD handle
+ * @param state Device state
* @retval None
*/
__weak void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c
index dd362a0841..15599cf0d5 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_pwr.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
@@ -253,7 +251,7 @@ void HAL_PWR_DisableBkUpAccess(void)
/**
* @brief Enables the WakeUp PINx functionality.
- * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
+ * @param WakeUpPinx Specifies the Power Wake-Up pin to enable.
* This parameter can be value of :
* @ref PWR_WakeUp_Pins
* @retval None
@@ -268,7 +266,7 @@ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
/**
* @brief Disables the WakeUp PINx functionality.
- * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
+ * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
* This parameter can be values of :
* @ref PWR_WakeUp_Pins
* @retval None
@@ -284,13 +282,13 @@ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
/**
* @brief Enters Sleep mode.
* @note In Sleep mode, all I/O pins keep the same state as in Run mode.
- * @param Regulator: Specifies the regulator state in SLEEP mode.
+ * @param Regulator Specifies the regulator state in SLEEP mode.
* This parameter can be one of the following values:
* @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
* @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
* @note This parameter has no effect in F3 family and is just maintained to
* offer full portability of other STM32 families softwares.
- * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.
+ * @param SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction.
* When WFI entry is used, tick interrupt have to be disabled if not desired as
* the interrupt wake up source.
* This parameter can be one of the following values:
@@ -330,11 +328,11 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
* startup delay is incurred when waking up from Stop mode.
* By keeping the internal regulator ON during Stop mode, the consumption
* is higher although the startup time is reduced.
- * @param Regulator: Specifies the regulator state in STOP mode.
+ * @param Regulator Specifies the regulator state in STOP mode.
* This parameter can be one of the following values:
* @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON
* @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON
- * @param STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
+ * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.
* This parameter can be one of the following values:
* @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction
* @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c
index b57368e343..188535e185 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_pwr_ex.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief Extended PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
@@ -137,7 +135,7 @@
/**
* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
- * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
+ * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration
* information for the PVD.
* @note Refer to the electrical characteristics of your device datasheet for
* more details about the voltage threshold corresponding to each
@@ -239,7 +237,7 @@ __weak void HAL_PWR_PVDCallback(void)
/**
* @brief Enables the SDADC peripheral functionaliy
- * @param Analogx: specifies the SDADC peripheral instance.
+ * @param Analogx specifies the SDADC peripheral instance.
* This parameter can be: PWR_SDADC_ANALOG1, PWR_SDADC_ANALOG2 or PWR_SDADC_ANALOG3.
* @retval None
*/
@@ -256,7 +254,7 @@ void HAL_PWREx_EnableSDADC(uint32_t Analogx)
/**
* @brief Disables the SDADC peripheral functionaliy
- * @param Analogx: specifies the SDADC peripheral instance.
+ * @param Analogx specifies the SDADC peripheral instance.
* This parameter can be: PWR_SDADC_ANALOG1, PWR_SDADC_ANALOG2 or PWR_SDADC_ANALOG3.
* @retval None
*/
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c
index 5522e3ae96..0fa36cc975 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_rcc.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Reset and Clock Control (RCC) peripheral:
@@ -836,7 +834,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
#endif
void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
{
- GPIO_InitTypeDef gpio = {0};
+ GPIO_InitTypeDef gpio;
/* Check the parameters */
assert_param(IS_RCC_MCO(RCC_MCOx));
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c
index 45ed8e6088..b1f4705796 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_rcc_ex.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief Extended RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities RCC extension peripheral:
@@ -959,10 +957,12 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
*/
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
+ /* frequency == 0 : means that no available frequency for the peripheral */
uint32_t frequency = 0U;
+
uint32_t srcclk = 0U;
#if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
- uint16_t adc_pll_prediv_table[12] = { 1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
+ uint16_t adc_pll_prediv_table[16] = { 1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U, 256U, 256U, 256U, 256U};
#endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
#if defined(RCC_CFGR_SDPRE)
uint8_t sdadc_prescaler_table[16] = { 2U, 4U, 6U, 8U, 10U, 12U, 14U, 16U, 20U, 24U, 28U, 32U, 36U, 40U, 44U, 48U};
@@ -993,11 +993,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
frequency = HSE_VALUE / 32U;
}
- /* Clock not enabled for RTC*/
- else
- {
- frequency = 0U;
- }
break;
}
case RCC_PERIPHCLK_USART1:
@@ -1032,11 +1027,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
frequency = LSE_VALUE;
}
- /* Clock not enabled for USART1*/
- else
- {
- frequency = 0U;
- }
break;
}
#if defined(RCC_CFGR3_USART2SW)
@@ -1065,11 +1055,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
frequency = LSE_VALUE;
}
- /* Clock not enabled for USART2*/
- else
- {
- frequency = 0U;
- }
break;
}
#endif /* RCC_CFGR3_USART2SW */
@@ -1099,12 +1084,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
frequency = LSE_VALUE;
}
- /* Clock not enabled for USART3*/
- else
- {
- frequency = 0U;
- }
- break;
+ break;
}
#endif /* RCC_CFGR3_USART3SW */
#if defined(RCC_CFGR3_UART4SW)
@@ -1133,11 +1113,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
frequency = LSE_VALUE;
}
- /* Clock not enabled for UART4*/
- else
- {
- frequency = 0U;
- }
break;
}
#endif /* RCC_CFGR3_UART4SW */
@@ -1167,11 +1142,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
frequency = LSE_VALUE;
}
- /* Clock not enabled for UART5*/
- else
- {
- frequency = 0U;
- }
break;
}
#endif /* RCC_CFGR3_UART5SW */
@@ -1190,11 +1160,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
frequency = HAL_RCC_GetSysClockFreq();
}
- /* Clock not enabled for I2C1*/
- else
- {
- frequency = 0U;
- }
break;
}
#if defined(RCC_CFGR3_I2C2SW)
@@ -1213,11 +1178,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
frequency = HAL_RCC_GetSysClockFreq();
}
- /* Clock not enabled for I2C2*/
- else
- {
- frequency = 0U;
- }
break;
}
#endif /* RCC_CFGR3_I2C2SW */
@@ -1237,11 +1197,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
frequency = HAL_RCC_GetSysClockFreq();
}
- /* Clock not enabled for I2C3*/
- else
- {
- frequency = 0U;
- }
break;
}
#endif /* RCC_CFGR3_I2C3SW */
@@ -1262,11 +1217,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
frequency = HAL_RCC_GetSysClockFreq();
}
- /* Clock not enabled for I2S*/
- else
- {
- frequency = 0U;
- }
break;
}
#endif /* RCC_CFGR_I2SSRC */
@@ -1290,11 +1240,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
frequency = (RCC_GetPLLCLKFreq() * 3U) / 2U;
}
}
- /* Clock not enabled for USB*/
- else
- {
- frequency = 0U;
- }
break;
}
#endif /* RCC_CFGR_USBPRE */
@@ -1318,11 +1263,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6U/8U/10U/12U/16U/32U/64U/128U/256U) */
frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADC1PRES)) & 0xFU];
}
- /* Clock not enabled for ADC1*/
- else
- {
- frequency = 0U;
- }
}
#else /* RCC_CFGR_ADCPRE */
/* ADC1 is set to PLCK2 frequency divided by 2U/4U/6U/8U */
@@ -1350,11 +1290,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6/8U/10U/12U/16U/32U/64U/128U/256U) */
frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADCPRE12)) & 0xF];
}
- /* Clock not enabled for ADC12*/
- else
- {
- frequency = 0U;
- }
}
break;
}
@@ -1378,11 +1313,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6U/8U/10U/12U/16U/32U/64U/128U/256U) */
frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ADCPRE34)) & 0xF];
}
- /* Clock not enabled for ADC34*/
- else
- {
- frequency = 0U;
- }
}
break;
}
@@ -1403,11 +1333,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
frequency = SystemCoreClock;
}
- /* Clock not enabled for TIM1*/
- else
- {
- frequency = 0U;
- }
break;
}
#endif /* RCC_CFGR3_TIM1SW */
@@ -1427,11 +1352,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
frequency = SystemCoreClock;
}
- /* Clock not enabled for TIM2*/
- else
- {
- frequency = 0U;
- }
break;
}
#endif /* RCC_CFGR3_TIM2SW */
@@ -1451,11 +1371,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
frequency = SystemCoreClock;
}
- /* Clock not enabled for TIM8*/
- else
- {
- frequency = 0U;
- }
break;
}
#endif /* RCC_CFGR3_TIM8SW */
@@ -1475,11 +1390,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
frequency = SystemCoreClock;
}
- /* Clock not enabled for TIM15*/
- else
- {
- frequency = 0U;
- }
break;
}
#endif /* RCC_CFGR3_TIM15SW */
@@ -1499,11 +1409,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
frequency = SystemCoreClock;
}
- /* Clock not enabled for TIM16*/
- else
- {
- frequency = 0U;
- }
break;
}
#endif /* RCC_CFGR3_TIM16SW */
@@ -1523,11 +1428,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
frequency = SystemCoreClock;
}
- /* Clock not enabled for TIM17*/
- else
- {
- frequency = 0U;
- }
break;
}
#endif /* RCC_CFGR3_TIM17SW */
@@ -1547,11 +1447,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
frequency = SystemCoreClock;
}
- /* Clock not enabled for TIM20*/
- else
- {
- frequency = 0U;
- }
break;
}
#endif /* RCC_CFGR3_TIM20SW */
@@ -1571,11 +1466,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
frequency = SystemCoreClock;
}
- /* Clock not enabled for TIM34*/
- else
- {
- frequency = 0U;
- }
break;
}
#endif /* RCC_CFGR3_TIM34SW */
@@ -1595,12 +1485,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
frequency = SystemCoreClock;
}
- /* Clock not enabled for HRTIM1*/
- else
- {
- frequency = 0U;
- }
- break;
+ break;
}
#endif /* RCC_CFGR3_HRTIM1SW */
#if defined(RCC_CFGR_SDPRE)
@@ -1629,11 +1514,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
frequency = LSE_VALUE;
}
- /* Clock not enabled for CEC*/
- else
- {
- frequency = 0U;
- }
break;
}
#endif /* RCC_CFGR3_CECSW */
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rtc.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rtc.c
index d522e9fbce..642074cff2 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rtc.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rtc.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_rtc.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real-Time Clock (RTC) peripheral:
@@ -237,7 +235,7 @@
/**
* @brief Initialize the RTC according to the specified parameters
* in the RTC_InitTypeDef structure and initialize the associated handle.
- * @param hrtc: RTC handle
+ * @param hrtc RTC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
@@ -296,7 +294,21 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
/* Exit Initialization mode */
hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
-
+
+ /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+ {
+ if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+
hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_ALARMOUTTYPE;
hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType);
@@ -312,7 +324,7 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
/**
* @brief DeInitialize the RTC peripheral.
- * @param hrtc: RTC handle
+ * @param hrtc RTC handle
* @note This function doesn't reset the RTC Backup Data registers.
* @retval HAL status
*/
@@ -413,7 +425,7 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
/**
* @brief Initialize the RTC MSP.
- * @param hrtc: RTC handle
+ * @param hrtc RTC handle
* @retval None
*/
__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
@@ -428,7 +440,7 @@ __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
/**
* @brief DeInitialize the RTC MSP.
- * @param hrtc: RTC handle
+ * @param hrtc RTC handle
* @retval None
*/
__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
@@ -461,9 +473,9 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
/**
* @brief Set RTC current time.
- * @param hrtc: RTC handle
- * @param sTime: Pointer to Time structure
- * @param Format: Specifies the format of the entered parameters.
+ * @param hrtc RTC handle
+ * @param sTime Pointer to Time structure
+ * @param Format Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
@@ -585,9 +597,9 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
/**
* @brief Get RTC current time.
- * @param hrtc: RTC handle
- * @param sTime: Pointer to Time structure
- * @param Format: Specifies the format of the entered parameters.
+ * @param hrtc RTC handle
+ * @param sTime Pointer to Time structure
+ * @param Format Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
@@ -635,9 +647,9 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
/**
* @brief Set RTC current date.
- * @param hrtc: RTC handle
- * @param sDate: Pointer to date structure
- * @param Format: specifies the format of the entered parameters.
+ * @param hrtc RTC handle
+ * @param sDate Pointer to date structure
+ * @param Format specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
@@ -743,9 +755,9 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat
/**
* @brief Get RTC current date.
- * @param hrtc: RTC handle
- * @param sDate: Pointer to Date structure
- * @param Format: Specifies the format of the entered parameters.
+ * @param hrtc RTC handle
+ * @param sDate Pointer to Date structure
+ * @param Format Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN : Binary data format
* @arg RTC_FORMAT_BCD : BCD data format
@@ -797,9 +809,9 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat
*/
/**
* @brief Set the specified RTC Alarm.
- * @param hrtc: RTC handle
- * @param sAlarm: Pointer to Alarm structure
- * @param Format: Specifies the format of the entered parameters.
+ * @param hrtc RTC handle
+ * @param sAlarm Pointer to Alarm structure
+ * @param Format Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
@@ -978,9 +990,9 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
/**
* @brief Set the specified RTC Alarm with Interrupt.
- * @param hrtc: RTC handle
- * @param sAlarm: Pointer to Alarm structure
- * @param Format: Specifies the format of the entered parameters.
+ * @param hrtc RTC handle
+ * @param sAlarm Pointer to Alarm structure
+ * @param Format Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
@@ -1167,8 +1179,8 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
/**
* @brief Deactivate the specified RTC Alarm.
- * @param hrtc: RTC handle
- * @param Alarm: Specifies the Alarm.
+ * @param hrtc RTC handle
+ * @param Alarm Specifies the Alarm.
* This parameter can be one of the following values:
* @arg RTC_ALARM_A : AlarmA
* @arg RTC_ALARM_B : AlarmB
@@ -1256,13 +1268,13 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar
/**
* @brief Get the RTC Alarm value and masks.
- * @param hrtc: RTC handle
- * @param sAlarm: Pointer to Date structure
- * @param Alarm: Specifies the Alarm.
+ * @param hrtc RTC handle
+ * @param sAlarm Pointer to Date structure
+ * @param Alarm Specifies the Alarm.
* This parameter can be one of the following values:
* @arg RTC_ALARM_A: AlarmA
* @arg RTC_ALARM_B: AlarmB
- * @param Format: Specifies the format of the entered parameters.
+ * @param Format Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
@@ -1315,7 +1327,7 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
/**
* @brief Handle Alarm interrupt request.
- * @param hrtc: RTC handle
+ * @param hrtc RTC handle
* @retval None
*/
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
@@ -1357,7 +1369,7 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
/**
* @brief Alarm A callback.
- * @param hrtc: RTC handle
+ * @param hrtc RTC handle
* @retval None
*/
__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
@@ -1372,8 +1384,8 @@ __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
/**
* @brief Handle AlarmA Polling request.
- * @param hrtc: RTC handle
- * @param Timeout: Timeout duration
+ * @param hrtc RTC handle
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
@@ -1432,7 +1444,7 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T
* The software must then wait until it is set again before reading
* the calendar, which means that the calendar registers have been
* correctly copied into the RTC_TR and RTC_DR shadow registers.
- * @param hrtc: RTC handle
+ * @param hrtc RTC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
@@ -1476,7 +1488,7 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
*/
/**
* @brief Return the RTC handle state.
- * @param hrtc: RTC handle
+ * @param hrtc RTC handle
* @retval HAL state
*/
HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
@@ -1501,7 +1513,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
* @brief Enter the RTC Initialization mode.
* @note The RTC Initialization mode is write protected, use the
* __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
- * @param hrtc: RTC handle
+ * @param hrtc RTC handle
* @retval An ErrorStatus enumeration value:
* - HAL_OK : RTC is in Init mode
* - HAL_TIMEOUT : RTC is not in Init mode and in Timeout
@@ -1533,7 +1545,7 @@ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
/**
* @brief Convert a 2 digit decimal to BCD format.
- * @param Value: Byte to be converted
+ * @param Value Byte to be converted
* @retval Converted byte
*/
uint8_t RTC_ByteToBcd2(uint8_t Value)
@@ -1551,7 +1563,7 @@ uint8_t RTC_ByteToBcd2(uint8_t Value)
/**
* @brief Convert from 2 digit BCD to Binary.
- * @param Value: BCD value to be converted
+ * @param Value BCD value to be converted
* @retval Converted word
*/
uint8_t RTC_Bcd2ToByte(uint8_t Value)
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rtc_ex.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rtc_ex.c
index 057bc3f4c5..429bb904f7 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rtc_ex.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rtc_ex.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_rtc_ex.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief Extended RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) Extended peripheral:
@@ -135,15 +133,15 @@
/**
* @brief Set TimeStamp.
* @note This API must be called before enabling the TimeStamp feature.
- * @param hrtc: RTC handle
- * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is
+ * @param hrtc RTC handle
+ * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is
* activated.
* This parameter can be one of the following values:
* @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
* rising edge of the related pin.
* @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
* falling edge of the related pin.
- * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin.
+ * @param RTC_TimeStampPin specifies the RTC TimeStamp Pin.
* This parameter can be one of the following values:
* @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
* @retval HAL status
@@ -188,16 +186,16 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS
/**
* @brief Set TimeStamp with Interrupt.
- * @param hrtc: RTC handle
+ * @param hrtc RTC handle
* @note This API must be called before enabling the TimeStamp feature.
- * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is
+ * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is
* activated.
* This parameter can be one of the following values:
* @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
* rising edge of the related pin.
* @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
* falling edge of the related pin.
- * @param RTC_TimeStampPin: Specifies the RTC TimeStamp Pin.
+ * @param RTC_TimeStampPin Specifies the RTC TimeStamp Pin.
* This parameter can be one of the following values:
* @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
* @retval HAL status
@@ -249,7 +247,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti
/**
* @brief Deactivate TimeStamp.
- * @param hrtc: RTC handle
+ * @param hrtc RTC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
@@ -286,10 +284,10 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
/**
* @brief Get the RTC TimeStamp value.
- * @param hrtc: RTC handle
- * @param sTimeStamp: Pointer to Time structure
- * @param sTimeStampDate: Pointer to Date structure
- * @param Format: specifies the format of the entered parameters.
+ * @param hrtc RTC handle
+ * @param sTimeStamp Pointer to Time structure
+ * @param sTimeStampDate Pointer to Date structure
+ * @param Format specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
@@ -342,8 +340,8 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe
/**
* @brief Set Tamper
* @note By calling this API we disable the tamper interrupt for all tampers.
- * @param hrtc: RTC handle
- * @param sTamper: Pointer to Tamper Structure.
+ * @param hrtc RTC handle
+ * @param sTamper Pointer to Tamper Structure.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
@@ -390,8 +388,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef
/**
* @brief Set Tamper with interrupt.
* @note By calling this API we force the tamper interrupt for all tampers.
- * @param hrtc: RTC handle
- * @param sTamper: Pointer to RTC Tamper.
+ * @param hrtc RTC handle
+ * @param sTamper Pointer to RTC Tamper.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
@@ -446,8 +444,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType
/**
* @brief Deactivate Tamper.
- * @param hrtc: RTC handle
- * @param Tamper: Selected tamper pin.
+ * @param hrtc RTC handle
+ * @param Tamper Selected tamper pin.
* This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3 (*)
* @note (*) RTC_TAMPER_3 not present on all the devices
* @retval HAL status
@@ -474,7 +472,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t T
/**
* @brief Handle TimeStamp interrupt request.
- * @param hrtc: RTC handle
+ * @param hrtc RTC handle
* @retval None
*/
void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
@@ -546,7 +544,7 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
/**
* @brief TimeStamp callback.
- * @param hrtc: RTC handle
+ * @param hrtc RTC handle
* @retval None
*/
__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
@@ -561,7 +559,7 @@ __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
/**
* @brief Tamper 1 callback.
- * @param hrtc: RTC handle
+ * @param hrtc RTC handle
* @retval None
*/
__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
@@ -576,7 +574,7 @@ __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
/**
* @brief Tamper 2 callback.
- * @param hrtc: RTC handle
+ * @param hrtc RTC handle
* @retval None
*/
__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
@@ -592,7 +590,7 @@ __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
#if defined(RTC_TAMPER3_SUPPORT)
/**
* @brief Tamper 3 callback.
- * @param hrtc: RTC handle
+ * @param hrtc RTC handle
* @retval None
*/
__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)
@@ -608,8 +606,8 @@ __weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)
/**
* @brief Handle TimeStamp polling request.
- * @param hrtc: RTC handle
- * @param Timeout: Timeout duration
+ * @param hrtc RTC handle
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
@@ -647,8 +645,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3
/**
* @brief Handle Tamper 1 Polling.
- * @param hrtc: RTC handle
- * @param Timeout: Timeout duration
+ * @param hrtc RTC handle
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
@@ -679,8 +677,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_
/**
* @brief Handle Tamper 2 Polling.
- * @param hrtc: RTC handle
- * @param Timeout: Timeout duration
+ * @param hrtc RTC handle
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
@@ -712,8 +710,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_
#if defined(RTC_TAMPER3_SUPPORT)
/**
* @brief Handle Tamper 3 Polling.
- * @param hrtc: RTC handle
- * @param Timeout: Timeout duration
+ * @param hrtc RTC handle
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
@@ -763,9 +761,9 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_
/**
* @brief Set wake up timer.
- * @param hrtc: RTC handle
- * @param WakeUpCounter: Wake up counter
- * @param WakeUpClock: Wake up clock
+ * @param hrtc RTC handle
+ * @param WakeUpCounter Wake up counter
+ * @param WakeUpClock Wake up clock
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
@@ -852,9 +850,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak
/**
* @brief Set wake up timer with interrupt.
- * @param hrtc: RTC handle
- * @param WakeUpCounter: Wake up counter
- * @param WakeUpClock: Wake up clock
+ * @param hrtc RTC handle
+ * @param WakeUpCounter Wake up counter
+ * @param WakeUpClock Wake up clock
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
@@ -953,7 +951,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
/**
* @brief Deactivate wake up timer counter.
- * @param hrtc: RTC handle
+ * @param hrtc RTC handle
* @retval HAL status
*/
uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
@@ -1005,7 +1003,7 @@ uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
/**
* @brief Get wake up timer counter.
- * @param hrtc: RTC handle
+ * @param hrtc RTC handle
* @retval Counter value
*/
uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
@@ -1016,7 +1014,7 @@ uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
/**
* @brief Handle Wake Up Timer interrupt request.
- * @param hrtc: RTC handle
+ * @param hrtc RTC handle
* @retval None
*/
void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
@@ -1040,7 +1038,7 @@ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
/**
* @brief Wake Up Timer callback.
- * @param hrtc: RTC handle
+ * @param hrtc RTC handle
* @retval None
*/
__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
@@ -1055,8 +1053,8 @@ __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
/**
* @brief Handle Wake Up Timer Polling.
- * @param hrtc: RTC handle
- * @param Timeout: Timeout duration
+ * @param hrtc RTC handle
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
@@ -1118,11 +1116,11 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin
/**
* @brief Write a data in a specified RTC Backup data register.
- * @param hrtc: RTC handle
- * @param BackupRegister: RTC Backup data Register number.
+ * @param hrtc RTC handle
+ * @param BackupRegister RTC Backup data Register number.
* This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
* specify the register.
- * @param Data: Data to be written in the specified RTC Backup data register.
+ * @param Data Data to be written in the specified RTC Backup data register.
* @retval None
*/
void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
@@ -1141,8 +1139,8 @@ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint3
/**
* @brief Reads data from the specified RTC Backup data Register.
- * @param hrtc: RTC handle
- * @param BackupRegister: RTC Backup data Register number.
+ * @param hrtc RTC handle
+ * @param BackupRegister RTC Backup data Register number.
* This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
* specify the register.
* @retval Read value
@@ -1163,17 +1161,17 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
/**
* @brief Set the Smooth calibration parameters.
- * @param hrtc: RTC handle
- * @param SmoothCalibPeriod: Select the Smooth Calibration Period.
+ * @param hrtc RTC handle
+ * @param SmoothCalibPeriod Select the Smooth Calibration Period.
* This parameter can be can be one of the following values :
* @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
* @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
* @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
- * @param SmoothCalibPlusPulses: Select to Set or reset the CALP bit.
+ * @param SmoothCalibPlusPulses Select to Set or reset the CALP bit.
* This parameter can be one of the following values:
* @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
* @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
- * @param SmoothCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
+ * @param SmoothCalibMinusPulsesValue Select the value of CALM[8:0] bits.
* This parameter can be one any value from 0 to 0x000001FF.
* @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses
* must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
@@ -1239,12 +1237,12 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t Smo
/**
* @brief Configure the Synchronization Shift Control Settings.
* @note When REFCKON is set, firmware must not write to Shift control register.
- * @param hrtc: RTC handle
+ * @param hrtc RTC handle
* @param ShiftAdd1S: Select to add or not 1 second to the time calendar.
* This parameter can be one of the following values :
* @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
* @arg RTC_SHIFTADD1S_RESET: No effect.
- * @param ShiftSubFS: Select the number of Second Fractions to substitute.
+ * @param ShiftSubFS Select the number of Second Fractions to substitute.
* This parameter can be one any value from 0 to 0x7FFF.
* @retval HAL status
*/
@@ -1334,8 +1332,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t Sh
/**
* @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- * @param hrtc: RTC handle
- * @param CalibOutput: Select the Calibration output Selection .
+ * @param hrtc RTC handle
+ * @param CalibOutput Select the Calibration output Selection .
* This parameter can be one of the following values:
* @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
* @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
@@ -1376,7 +1374,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32
/**
* @brief Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- * @param hrtc: RTC handle
+ * @param hrtc RTC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)
@@ -1405,7 +1403,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)
/**
* @brief Enable the RTC reference clock detection.
- * @param hrtc: RTC handle
+ * @param hrtc RTC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)
@@ -1454,7 +1452,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)
/**
* @brief Disable the RTC reference clock detection.
- * @param hrtc: RTC handle
+ * @param hrtc RTC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
@@ -1503,7 +1501,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
/**
* @brief Enable the Bypass Shadow feature.
- * @param hrtc: RTC handle
+ * @param hrtc RTC handle
* @note When the Bypass Shadow is enabled the calendar value are taken
* directly from the Calendar counter.
* @retval HAL status
@@ -1535,7 +1533,7 @@ HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc)
/**
* @brief Disable the Bypass Shadow feature.
- * @param hrtc: RTC handle
+ * @param hrtc RTC handle
* @note When the Bypass Shadow is enabled the calendar value are taken
* directly from the Calendar counter.
* @retval HAL status
@@ -1586,7 +1584,7 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc)
/**
* @brief Alarm B callback.
- * @param hrtc: RTC handle
+ * @param hrtc RTC handle
* @retval None
*/
__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
@@ -1601,8 +1599,8 @@ __weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
/**
* @brief This function handles AlarmB Polling request.
- * @param hrtc: RTC handle
- * @param Timeout: Timeout duration
+ * @param hrtc RTC handle
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_sdadc.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_sdadc.c
index 8042759d92..5845cba10a 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_sdadc.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_sdadc.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_sdadc.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Sigma-Delta Analog to Digital Converter
* (SDADC) peripherals:
@@ -265,11 +263,17 @@ static void SDADC_DMAError(DMA_HandleTypeDef *hdma);
* parameters in the SDADC_InitTypeDef structure.
* @note If multiple SDADC are used, please configure first SDADC1 to set
* the common reference voltage.
- * @param hsdadc: SDADC handle.
+ * @param hsdadc SDADC handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_SDADC_Init(SDADC_HandleTypeDef* hsdadc)
{
+ /* Check SDADC handle */
+ if(hsdadc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
/* Check parameters */
assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
assert_param(IS_SDADC_LOWPOWER_MODE(hsdadc->Init.IdleLowPowerMode));
@@ -277,12 +281,6 @@ HAL_StatusTypeDef HAL_SDADC_Init(SDADC_HandleTypeDef* hsdadc)
assert_param(IS_SDADC_SLOW_CLOCK_MODE(hsdadc->Init.SlowClockMode));
assert_param(IS_SDADC_VREF(hsdadc->Init.ReferenceVoltage));
- /* Check SDADC handle */
- if(hsdadc == NULL)
- {
- return HAL_ERROR;
- }
-
/* Initialize SDADC variables with default values */
hsdadc->RegularContMode = SDADC_CONTINUOUS_CONV_OFF;
hsdadc->InjectedContMode = SDADC_CONTINUOUS_CONV_OFF;
@@ -337,20 +335,20 @@ HAL_StatusTypeDef HAL_SDADC_Init(SDADC_HandleTypeDef* hsdadc)
/**
* @brief De-initializes the SDADC.
- * @param hsdadc: SDADC handle.
+ * @param hsdadc SDADC handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_SDADC_DeInit(SDADC_HandleTypeDef* hsdadc)
{
- /* Check parameters */
- assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
-
/* Check SDADC handle */
if(hsdadc == NULL)
{
return HAL_ERROR;
}
+ /* Check parameters */
+ assert_param(IS_SDADC_ALL_INSTANCE(hsdadc->Instance));
+
/* Disable the SDADC */
hsdadc->Instance->CR2 &= ~(SDADC_CR2_ADON);
@@ -376,7 +374,7 @@ HAL_StatusTypeDef HAL_SDADC_DeInit(SDADC_HandleTypeDef* hsdadc)
/**
* @brief Initializes the SDADC MSP.
- * @param hsdadc: SDADC handle
+ * @param hsdadc SDADC handle
* @retval None
*/
__weak void HAL_SDADC_MspInit(SDADC_HandleTypeDef* hsdadc)
@@ -391,7 +389,7 @@ __weak void HAL_SDADC_MspInit(SDADC_HandleTypeDef* hsdadc)
/**
* @brief De-initializes the SDADC MSP.
- * @param hsdadc: SDADC handle
+ * @param hsdadc SDADC handle
* @retval None
*/
__weak void HAL_SDADC_MspDeInit(SDADC_HandleTypeDef* hsdadc)
@@ -434,10 +432,10 @@ __weak void HAL_SDADC_MspDeInit(SDADC_HandleTypeDef* hsdadc)
* Parameters are input mode, common mode, gain and offset.
* @note This function should be called only when SDADC instance is in idle state
* (neither calibration nor regular or injected conversion ongoing)
- * @param hsdadc: SDADC handle.
- * @param ConfIndex: Index of configuration to modify.
+ * @param hsdadc SDADC handle.
+ * @param ConfIndex Index of configuration to modify.
* This parameter can be a value of @ref SDADC_ConfIndex.
- * @param ConfParamStruct: Parameters to apply for this configuration.
+ * @param ConfParamStruct Parameters to apply for this configuration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDADC_PrepareChannelConfig(SDADC_HandleTypeDef *hsdadc,
@@ -493,10 +491,10 @@ HAL_StatusTypeDef HAL_SDADC_PrepareChannelConfig(SDADC_HandleTypeDef *hsdadc,
* available configurations.
* @note This function should be called only when SDADC instance is in idle state
* (neither calibration nor regular or injected conversion ongoing)
- * @param hsdadc: SDADC handle.
- * @param Channel: Channel to associate with configuration.
+ * @param hsdadc SDADC handle.
+ * @param Channel Channel to associate with configuration.
* This parameter can be a value of @ref SDADC_Channel_Selection.
- * @param ConfIndex: Index of configuration to associate with channel.
+ * @param ConfIndex Index of configuration to associate with channel.
* This parameter can be a value of @ref SDADC_ConfIndex.
* @retval HAL status
*/
@@ -553,10 +551,10 @@ HAL_StatusTypeDef HAL_SDADC_AssociateChannelConfig(SDADC_HandleTypeDef *hsdadc,
/**
* @brief This function allows to select channel for regular conversion and
* to enable/disable continuous mode for regular conversion.
- * @param hsdadc: SDADC handle.
- * @param Channel: Channel for regular conversion.
+ * @param hsdadc SDADC handle.
+ * @param Channel Channel for regular conversion.
* This parameter can be a value of @ref SDADC_Channel_Selection.
- * @param ContinuousMode: Enable/disable continuous mode for regular conversion.
+ * @param ContinuousMode Enable/disable continuous mode for regular conversion.
* This parameter can be a value of @ref SDADC_ContinuousMode.
* @retval HAL status
*/
@@ -598,10 +596,10 @@ HAL_StatusTypeDef HAL_SDADC_ConfigChannel(SDADC_HandleTypeDef *hsdadc,
/**
* @brief This function allows to select channels for injected conversion and
* to enable/disable continuous mode for injected conversion.
- * @param hsdadc: SDADC handle.
- * @param Channel: Channels for injected conversion.
+ * @param hsdadc SDADC handle.
+ * @param Channel Channels for injected conversion.
* This parameter can be a values combination of @ref SDADC_Channel_Selection.
- * @param ContinuousMode: Enable/disable continuous mode for injected conversion.
+ * @param ContinuousMode Enable/disable continuous mode for injected conversion.
* This parameter can be a value of @ref SDADC_ContinuousMode.
* @retval HAL status
*/
@@ -646,8 +644,8 @@ HAL_StatusTypeDef HAL_SDADC_InjectedConfigChannel(SDADC_HandleTypeDef *hsdadc,
/**
* @brief This function allows to select trigger for regular conversions.
* @note This function should not be called if regular conversion is ongoing.
- * @param hsdadc: SDADC handle.
- * @param Trigger: Trigger for regular conversions.
+ * @param hsdadc SDADC handle.
+ * @param Trigger Trigger for regular conversions.
* This parameter can be one of the following value :
* @arg SDADC_SOFTWARE_TRIGGER : Software trigger.
* @arg SDADC_SYNCHRONOUS_TRIGGER : Synchronous with SDADC1 (only for SDADC2 and SDADC3).
@@ -685,8 +683,8 @@ HAL_StatusTypeDef HAL_SDADC_SelectRegularTrigger(SDADC_HandleTypeDef *hsdadc, ui
/**
* @brief This function allows to select trigger for injected conversions.
* @note This function should not be called if injected conversion is ongoing.
- * @param hsdadc: SDADC handle.
- * @param Trigger: Trigger for injected conversions.
+ * @param hsdadc SDADC handle.
+ * @param Trigger Trigger for injected conversions.
* This parameter can be one of the following value :
* @arg SDADC_SOFTWARE_TRIGGER : Software trigger.
* @arg SDADC_SYNCHRONOUS_TRIGGER : Synchronous with SDADC1 (only for SDADC2 and SDADC3).
@@ -726,10 +724,10 @@ HAL_StatusTypeDef HAL_SDADC_SelectInjectedTrigger(SDADC_HandleTypeDef *hsdadc, u
* @brief This function allows to select and configure injected external trigger.
* @note This function should be called only when SDADC instance is in idle state
* (neither calibration nor regular or injected conversion ongoing)
- * @param hsdadc: SDADC handle.
- * @param InjectedExtTrigger: External trigger for injected conversions.
+ * @param hsdadc SDADC handle.
+ * @param InjectedExtTrigger External trigger for injected conversions.
* This parameter can be a value of @ref SDADC_InjectedExtTrigger.
- * @param ExtTriggerEdge: Edge of external injected trigger.
+ * @param ExtTriggerEdge Edge of external injected trigger.
* This parameter can be a value of @ref SDADC_ExtTriggerEdge.
* @retval HAL status
*/
@@ -779,8 +777,8 @@ HAL_StatusTypeDef HAL_SDADC_SelectInjectedExtTrigger(SDADC_HandleTypeDef *hsdadc
* @brief This function allows to enable/disable delay addition for injected conversions.
* @note This function should be called only when SDADC instance is in idle state
* (neither calibration nor regular or injected conversion ongoing)
- * @param hsdadc: SDADC handle.
- * @param InjectedDelay: Enable/disable delay for injected conversions.
+ * @param hsdadc SDADC handle.
+ * @param InjectedDelay Enable/disable delay for injected conversions.
* This parameter can be a value of @ref SDADC_InjectedDelay.
* @retval HAL status
*/
@@ -825,8 +823,8 @@ HAL_StatusTypeDef HAL_SDADC_SelectInjectedDelay(SDADC_HandleTypeDef *hsdadc,
* @brief This function allows to configure multimode for regular conversions.
* @note This function should not be called if regular conversion is ongoing
* and should be could only for SDADC1.
- * @param hsdadc: SDADC handle.
- * @param MultimodeType: Type of multimode for regular conversions.
+ * @param hsdadc SDADC handle.
+ * @param MultimodeType Type of multimode for regular conversions.
* This parameter can be a value of @ref SDADC_MultimodeType.
* @retval HAL status
*/
@@ -864,8 +862,8 @@ HAL_StatusTypeDef HAL_SDADC_MultiModeConfigChannel(SDADC_HandleTypeDef* hsdadc,
* @brief This function allows to configure multimode for injected conversions.
* @note This function should not be called if injected conversion is ongoing
* and should be could only for SDADC1.
- * @param hsdadc: SDADC handle.
- * @param MultimodeType: Type of multimode for injected conversions.
+ * @param hsdadc SDADC handle.
+ * @param MultimodeType Type of multimode for injected conversions.
* This parameter can be a value of @ref SDADC_MultimodeType.
* @retval HAL status
*/
@@ -937,8 +935,8 @@ HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeConfigChannel(SDADC_HandleTypeDef*
* @brief This function allows to start calibration in polling mode.
* @note This function should be called only when SDADC instance is in idle state
* (neither calibration nor regular or injected conversion ongoing).
- * @param hsdadc: SDADC handle.
- * @param CalibrationSequence: Calibration sequence.
+ * @param hsdadc SDADC handle.
+ * @param CalibrationSequence Calibration sequence.
* This parameter can be a value of @ref SDADC_CalibrationSequence.
* @retval HAL status
*/
@@ -988,8 +986,8 @@ HAL_StatusTypeDef HAL_SDADC_CalibrationStart(SDADC_HandleTypeDef *hsdadc,
/**
* @brief This function allows to poll for the end of calibration.
* @note This function should be called only if calibration is ongoing.
- * @param hsdadc: SDADC handle.
- * @param Timeout: Timeout value in milliseconds.
+ * @param hsdadc SDADC handle.
+ * @param Timeout Timeout value in milliseconds.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDADC_PollForCalibEvent(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout)
@@ -1038,8 +1036,8 @@ HAL_StatusTypeDef HAL_SDADC_PollForCalibEvent(SDADC_HandleTypeDef* hsdadc, uint3
* @brief This function allows to start calibration in interrupt mode.
* @note This function should be called only when SDADC instance is in idle state
* (neither calibration nor regular or injected conversion ongoing).
- * @param hsdadc: SDADC handle.
- * @param CalibrationSequence: Calibration sequence.
+ * @param hsdadc SDADC handle.
+ * @param CalibrationSequence Calibration sequence.
* This parameter can be a value of @ref SDADC_CalibrationSequence.
* @retval HAL status
*/
@@ -1093,7 +1091,7 @@ HAL_StatusTypeDef HAL_SDADC_CalibrationStart_IT(SDADC_HandleTypeDef *hsdadc,
* @brief This function allows to start regular conversion in polling mode.
* @note This function should be called only when SDADC instance is in idle state
* or if injected conversion is ongoing.
- * @param hsdadc: SDADC handle.
+ * @param hsdadc SDADC handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDADC_Start(SDADC_HandleTypeDef *hsdadc)
@@ -1121,8 +1119,8 @@ HAL_StatusTypeDef HAL_SDADC_Start(SDADC_HandleTypeDef *hsdadc)
/**
* @brief This function allows to poll for the end of regular conversion.
* @note This function should be called only if regular conversion is ongoing.
- * @param hsdadc: SDADC handle.
- * @param Timeout: Timeout value in milliseconds.
+ * @param hsdadc SDADC handle.
+ * @param Timeout Timeout value in milliseconds.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDADC_PollForConversion(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout)
@@ -1182,7 +1180,7 @@ HAL_StatusTypeDef HAL_SDADC_PollForConversion(SDADC_HandleTypeDef* hsdadc, uint3
/**
* @brief This function allows to stop regular conversion in polling mode.
* @note This function should be called only if regular conversion is ongoing.
- * @param hsdadc: SDADC handle.
+ * @param hsdadc SDADC handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDADC_Stop(SDADC_HandleTypeDef *hsdadc)
@@ -1212,7 +1210,7 @@ HAL_StatusTypeDef HAL_SDADC_Stop(SDADC_HandleTypeDef *hsdadc)
* @brief This function allows to start regular conversion in interrupt mode.
* @note This function should be called only when SDADC instance is in idle state
* or if injected conversion is ongoing.
- * @param hsdadc: SDADC handle.
+ * @param hsdadc SDADC handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDADC_Start_IT(SDADC_HandleTypeDef *hsdadc)
@@ -1243,7 +1241,7 @@ HAL_StatusTypeDef HAL_SDADC_Start_IT(SDADC_HandleTypeDef *hsdadc)
/**
* @brief This function allows to stop regular conversion in interrupt mode.
* @note This function should be called only if regular conversion is ongoing.
- * @param hsdadc: SDADC handle.
+ * @param hsdadc SDADC handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDADC_Stop_IT(SDADC_HandleTypeDef *hsdadc)
@@ -1276,9 +1274,9 @@ HAL_StatusTypeDef HAL_SDADC_Stop_IT(SDADC_HandleTypeDef *hsdadc)
* @brief This function allows to start regular conversion in DMA mode.
* @note This function should be called only when SDADC instance is in idle state
* or if injected conversion is ongoing.
- * @param hsdadc: SDADC handle.
- * @param pData: The destination buffer address.
- * @param Length: The length of data to be transferred from SDADC peripheral to memory.
+ * @param hsdadc SDADC handle.
+ * @param pData The destination buffer address.
+ * @param Length The length of data to be transferred from SDADC peripheral to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDADC_Start_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pData,
@@ -1350,7 +1348,7 @@ HAL_StatusTypeDef HAL_SDADC_Start_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pDa
/**
* @brief This function allows to stop regular conversion in DMA mode.
* @note This function should be called only if regular conversion is ongoing.
- * @param hsdadc: SDADC handle.
+ * @param hsdadc SDADC handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDADC_Stop_DMA(SDADC_HandleTypeDef *hsdadc)
@@ -1391,7 +1389,7 @@ HAL_StatusTypeDef HAL_SDADC_Stop_DMA(SDADC_HandleTypeDef *hsdadc)
/**
* @brief This function allows to get regular conversion value.
- * @param hsdadc: SDADC handle.
+ * @param hsdadc SDADC handle.
* @retval Regular conversion value
*/
uint32_t HAL_SDADC_GetValue(SDADC_HandleTypeDef *hsdadc)
@@ -1407,7 +1405,7 @@ uint32_t HAL_SDADC_GetValue(SDADC_HandleTypeDef *hsdadc)
* @brief This function allows to start injected conversion in polling mode.
* @note This function should be called only when SDADC instance is in idle state
* or if regular conversion is ongoing.
- * @param hsdadc: SDADC handle.
+ * @param hsdadc SDADC handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDADC_InjectedStart(SDADC_HandleTypeDef *hsdadc)
@@ -1435,8 +1433,8 @@ HAL_StatusTypeDef HAL_SDADC_InjectedStart(SDADC_HandleTypeDef *hsdadc)
/**
* @brief This function allows to poll for the end of injected conversion.
* @note This function should be called only if injected conversion is ongoing.
- * @param hsdadc: SDADC handle.
- * @param Timeout: Timeout value in milliseconds.
+ * @param hsdadc SDADC handle.
+ * @param Timeout Timeout value in milliseconds.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDADC_PollForInjectedConversion(SDADC_HandleTypeDef* hsdadc,
@@ -1507,7 +1505,7 @@ HAL_StatusTypeDef HAL_SDADC_PollForInjectedConversion(SDADC_HandleTypeDef* hsdad
/**
* @brief This function allows to stop injected conversion in polling mode.
* @note This function should be called only if injected conversion is ongoing.
- * @param hsdadc: SDADC handle.
+ * @param hsdadc SDADC handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDADC_InjectedStop(SDADC_HandleTypeDef *hsdadc)
@@ -1537,7 +1535,7 @@ HAL_StatusTypeDef HAL_SDADC_InjectedStop(SDADC_HandleTypeDef *hsdadc)
* @brief This function allows to start injected conversion in interrupt mode.
* @note This function should be called only when SDADC instance is in idle state
* or if regular conversion is ongoing.
- * @param hsdadc: SDADC handle.
+ * @param hsdadc SDADC handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDADC_InjectedStart_IT(SDADC_HandleTypeDef *hsdadc)
@@ -1568,7 +1566,7 @@ HAL_StatusTypeDef HAL_SDADC_InjectedStart_IT(SDADC_HandleTypeDef *hsdadc)
/**
* @brief This function allows to stop injected conversion in interrupt mode.
* @note This function should be called only if injected conversion is ongoing.
- * @param hsdadc: SDADC handle.
+ * @param hsdadc SDADC handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDADC_InjectedStop_IT(SDADC_HandleTypeDef *hsdadc)
@@ -1601,9 +1599,9 @@ HAL_StatusTypeDef HAL_SDADC_InjectedStop_IT(SDADC_HandleTypeDef *hsdadc)
* @brief This function allows to start injected conversion in DMA mode.
* @note This function should be called only when SDADC instance is in idle state
* or if regular conversion is ongoing.
- * @param hsdadc: SDADC handle.
- * @param pData: The destination buffer address.
- * @param Length: The length of data to be transferred from SDADC peripheral to memory.
+ * @param hsdadc SDADC handle.
+ * @param pData The destination buffer address.
+ * @param Length The length of data to be transferred from SDADC peripheral to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDADC_InjectedStart_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pData,
@@ -1675,7 +1673,7 @@ HAL_StatusTypeDef HAL_SDADC_InjectedStart_DMA(SDADC_HandleTypeDef *hsdadc, uint3
/**
* @brief This function allows to stop injected conversion in DMA mode.
* @note This function should be called only if injected conversion is ongoing.
- * @param hsdadc: SDADC handle.
+ * @param hsdadc SDADC handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDADC_InjectedStop_DMA(SDADC_HandleTypeDef *hsdadc)
@@ -1716,8 +1714,8 @@ HAL_StatusTypeDef HAL_SDADC_InjectedStop_DMA(SDADC_HandleTypeDef *hsdadc)
/**
* @brief This function allows to get injected conversion value.
- * @param hsdadc: SDADC handle.
- * @param Channel: Corresponding channel of injected conversion.
+ * @param hsdadc SDADC handle.
+ * @param Channel Corresponding channel of injected conversion.
* @retval Injected conversion value
*/
uint32_t HAL_SDADC_InjectedGetValue(SDADC_HandleTypeDef *hsdadc, uint32_t* Channel)
@@ -1741,9 +1739,9 @@ uint32_t HAL_SDADC_InjectedGetValue(SDADC_HandleTypeDef *hsdadc, uint32_t* Chann
* @brief This function allows to start multimode regular conversions in DMA mode.
* @note This function should be called only when SDADC instance is in idle state
* or if injected conversion is ongoing.
- * @param hsdadc: SDADC handle.
- * @param pData: The destination buffer address.
- * @param Length: The length of data to be transferred from SDADC peripheral to memory.
+ * @param hsdadc SDADC handle.
+ * @param pData The destination buffer address.
+ * @param Length The length of data to be transferred from SDADC peripheral to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDADC_MultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc, uint32_t* pData,
@@ -1828,7 +1826,7 @@ HAL_StatusTypeDef HAL_SDADC_MultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc, uint
/**
* @brief This function allows to stop multimode regular conversions in DMA mode.
* @note This function should be called only if regular conversion is ongoing.
- * @param hsdadc: SDADC handle.
+ * @param hsdadc SDADC handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDADC_MultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc)
@@ -1874,7 +1872,7 @@ HAL_StatusTypeDef HAL_SDADC_MultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc)
/**
* @brief This function allows to get multimode regular conversion value.
- * @param hsdadc: SDADC handle.
+ * @param hsdadc SDADC handle.
* @retval Multimode regular conversion value
*/
uint32_t HAL_SDADC_MultiModeGetValue(SDADC_HandleTypeDef* hsdadc)
@@ -1897,9 +1895,9 @@ uint32_t HAL_SDADC_MultiModeGetValue(SDADC_HandleTypeDef* hsdadc)
* @brief This function allows to start multimode injected conversions in DMA mode.
* @note This function should be called only when SDADC instance is in idle state
* or if regular conversion is ongoing.
- * @param hsdadc: SDADC handle.
- * @param pData: The destination buffer address.
- * @param Length: The length of data to be transferred from SDADC peripheral to memory.
+ * @param hsdadc SDADC handle.
+ * @param pData The destination buffer address.
+ * @param Length The length of data to be transferred from SDADC peripheral to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc,
@@ -1984,7 +1982,7 @@ HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStart_DMA(SDADC_HandleTypeDef* hsda
/**
* @brief This function allows to stop multimode injected conversions in DMA mode.
* @note This function should be called only if injected conversion is ongoing.
- * @param hsdadc: SDADC handle.
+ * @param hsdadc SDADC handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc)
@@ -2030,7 +2028,7 @@ HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStop_DMA(SDADC_HandleTypeDef* hsdad
/**
* @brief This function allows to get multimode injected conversion value.
- * @param hsdadc: SDADC handle.
+ * @param hsdadc SDADC handle.
* @retval Multimode injected conversion value
*/
uint32_t HAL_SDADC_InjectedMultiModeGetValue(SDADC_HandleTypeDef* hsdadc)
@@ -2051,7 +2049,7 @@ uint32_t HAL_SDADC_InjectedMultiModeGetValue(SDADC_HandleTypeDef* hsdadc)
/**
* @brief This function handles the SDADC interrupts.
- * @param hsdadc: SDADC handle.
+ * @param hsdadc SDADC handle.
* @retval None
*/
void HAL_SDADC_IRQHandler(SDADC_HandleTypeDef* hsdadc)
@@ -2155,7 +2153,7 @@ void HAL_SDADC_IRQHandler(SDADC_HandleTypeDef* hsdadc)
/**
* @brief Calibration complete callback.
- * @param hsdadc: SDADC handle.
+ * @param hsdadc SDADC handle.
* @retval None
*/
__weak void HAL_SDADC_CalibrationCpltCallback(SDADC_HandleTypeDef* hsdadc)
@@ -2170,7 +2168,7 @@ __weak void HAL_SDADC_CalibrationCpltCallback(SDADC_HandleTypeDef* hsdadc)
/**
* @brief Half regular conversion complete callback.
- * @param hsdadc: SDADC handle.
+ * @param hsdadc SDADC handle.
* @retval None
*/
__weak void HAL_SDADC_ConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc)
@@ -2187,7 +2185,7 @@ __weak void HAL_SDADC_ConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc)
* @brief Regular conversion complete callback.
* @note In interrupt mode, user has to read conversion value in this function
using HAL_SDADC_GetValue or HAL_SDADC_MultiModeGetValue.
- * @param hsdadc: SDADC handle.
+ * @param hsdadc SDADC handle.
* @retval None
*/
__weak void HAL_SDADC_ConvCpltCallback(SDADC_HandleTypeDef* hsdadc)
@@ -2202,7 +2200,7 @@ __weak void HAL_SDADC_ConvCpltCallback(SDADC_HandleTypeDef* hsdadc)
/**
* @brief Half injected conversion complete callback.
- * @param hsdadc: SDADC handle.
+ * @param hsdadc SDADC handle.
* @retval None
*/
__weak void HAL_SDADC_InjectedConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc)
@@ -2219,7 +2217,7 @@ __weak void HAL_SDADC_InjectedConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc)
* @brief Injected conversion complete callback.
* @note In interrupt mode, user has to read conversion value in this function
using HAL_SDADC_InjectedGetValue or HAL_SDADC_InjectedMultiModeGetValue.
- * @param hsdadc: SDADC handle.
+ * @param hsdadc SDADC handle.
* @retval None
*/
__weak void HAL_SDADC_InjectedConvCpltCallback(SDADC_HandleTypeDef* hsdadc)
@@ -2234,7 +2232,7 @@ __weak void HAL_SDADC_InjectedConvCpltCallback(SDADC_HandleTypeDef* hsdadc)
/**
* @brief Error callback.
- * @param hsdadc: SDADC handle.
+ * @param hsdadc SDADC handle.
* @retval None
*/
__weak void HAL_SDADC_ErrorCallback(SDADC_HandleTypeDef* hsdadc)
@@ -2249,7 +2247,7 @@ __weak void HAL_SDADC_ErrorCallback(SDADC_HandleTypeDef* hsdadc)
/**
* @brief DMA half transfer complete callback for regular conversion.
- * @param hdma : DMA handle.
+ * @param hdma DMA handle.
* @retval None
*/
static void SDADC_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
@@ -2263,7 +2261,7 @@ static void SDADC_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA transfer complete callback for regular conversion.
- * @param hdma : DMA handle.
+ * @param hdma DMA handle.
* @retval None
*/
static void SDADC_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
@@ -2277,7 +2275,7 @@ static void SDADC_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA half transfer complete callback for injected conversion.
- * @param hdma : DMA handle.
+ * @param hdma DMA handle.
* @retval None
*/
static void SDADC_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
@@ -2291,7 +2289,7 @@ static void SDADC_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA transfer complete callback for injected conversion.
- * @param hdma : DMA handle.
+ * @param hdma DMA handle.
* @retval None
*/
static void SDADC_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
@@ -2305,7 +2303,7 @@ static void SDADC_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA error callback.
- * @param hdma : DMA handle.
+ * @param hdma DMA handle.
* @retval None
*/
static void SDADC_DMAError(DMA_HandleTypeDef *hdma)
@@ -2341,7 +2339,7 @@ static void SDADC_DMAError(DMA_HandleTypeDef *hdma)
/**
* @brief This function allows to get the current SDADC state.
- * @param hsdadc: SDADC handle.
+ * @param hsdadc SDADC handle.
* @retval SDADC state.
*/
HAL_SDADC_StateTypeDef HAL_SDADC_GetState(SDADC_HandleTypeDef* hsdadc)
@@ -2351,7 +2349,7 @@ HAL_SDADC_StateTypeDef HAL_SDADC_GetState(SDADC_HandleTypeDef* hsdadc)
/**
* @brief This function allows to get the current SDADC error code.
- * @param hsdadc: SDADC handle.
+ * @param hsdadc SDADC handle.
* @retval SDADC error code.
*/
uint32_t HAL_SDADC_GetError(SDADC_HandleTypeDef* hsdadc)
@@ -2369,7 +2367,7 @@ uint32_t HAL_SDADC_GetError(SDADC_HandleTypeDef* hsdadc)
/**
* @brief This function allows to enter in init mode for SDADC instance.
- * @param hsdadc: SDADC handle.
+ * @param hsdadc SDADC handle.
* @retval HAL status.
*/
static HAL_StatusTypeDef SDADC_EnterInitMode(SDADC_HandleTypeDef* hsdadc)
@@ -2395,7 +2393,7 @@ static HAL_StatusTypeDef SDADC_EnterInitMode(SDADC_HandleTypeDef* hsdadc)
/**
* @brief This function allows to exit from init mode for SDADC instance.
- * @param hsdadc: SDADC handle.
+ * @param hsdadc SDADC handle.
* @retval None.
*/
static void SDADC_ExitInitMode(SDADC_HandleTypeDef* hsdadc)
@@ -2406,7 +2404,7 @@ static void SDADC_ExitInitMode(SDADC_HandleTypeDef* hsdadc)
/**
* @brief This function allows to get the number of injected channels.
- * @param Channels : bitfield of injected channels.
+ * @param Channels bitfield of injected channels.
* @retval Number of injected channels.
*/
static uint32_t SDADC_GetInjChannelsNbr(uint32_t Channels)
@@ -2429,7 +2427,7 @@ static uint32_t SDADC_GetInjChannelsNbr(uint32_t Channels)
/**
* @brief This function allows to really start regular conversion.
- * @param hsdadc: SDADC handle.
+ * @param hsdadc SDADC handle.
* @retval HAL status.
*/
static HAL_StatusTypeDef SDADC_RegConvStart(SDADC_HandleTypeDef* hsdadc)
@@ -2472,7 +2470,7 @@ static HAL_StatusTypeDef SDADC_RegConvStart(SDADC_HandleTypeDef* hsdadc)
/**
* @brief This function allows to really stop regular conversion.
- * @param hsdadc: SDADC handle.
+ * @param hsdadc SDADC handle.
* @retval HAL status.
*/
static HAL_StatusTypeDef SDADC_RegConvStop(SDADC_HandleTypeDef* hsdadc)
@@ -2543,7 +2541,7 @@ static HAL_StatusTypeDef SDADC_RegConvStop(SDADC_HandleTypeDef* hsdadc)
/**
* @brief This function allows to really start injected conversion.
- * @param hsdadc: SDADC handle.
+ * @param hsdadc SDADC handle.
* @retval HAL status.
*/
static HAL_StatusTypeDef SDADC_InjConvStart(SDADC_HandleTypeDef* hsdadc)
@@ -2596,7 +2594,7 @@ static HAL_StatusTypeDef SDADC_InjConvStart(SDADC_HandleTypeDef* hsdadc)
/**
* @brief This function allows to really stop injected conversion.
- * @param hsdadc: SDADC handle.
+ * @param hsdadc SDADC handle.
* @retval HAL status.
*/
static HAL_StatusTypeDef SDADC_InjConvStop(SDADC_HandleTypeDef* hsdadc)
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smartcard.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smartcard.c
index 57bac802c3..c79d507e82 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smartcard.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smartcard.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_smartcard.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief SMARTCARD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the SMARTCARD peripheral:
@@ -1298,7 +1296,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc
/**
* @brief Handle SMARTCARD interrupt requests.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @retval None
*/
@@ -1662,7 +1660,7 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
/**
* @brief Configure the SMARTCARD associated USART peripheral.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @retval HAL status
*/
@@ -1760,7 +1758,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard
/**
* @brief Configure the SMARTCARD associated USART peripheral advanced features.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @retval None
*/
@@ -1822,7 +1820,7 @@ static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard)
/**
* @brief Check the SMARTCARD Idle State.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @retval HAL status
*/
@@ -2162,7 +2160,7 @@ static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
/**
* @brief Send an amount of data in non-blocking mode.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* Function called under interruption only, once
* interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
@@ -2235,7 +2233,7 @@ static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmar
/**
* @brief Receive an amount of data in non-blocking mode.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* Function called under interruption only, once
* interruptions have been enabled by HAL_SMARTCARD_Receive_IT().
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smartcard_ex.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smartcard_ex.c
index e7ec0d93a4..8e96545409 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smartcard_ex.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smartcard_ex.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_smartcard_ex.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief SMARTCARD HAL module driver.
* This file provides extended firmware functions to manage the following
* functionalities of the SmartCard.
@@ -99,9 +97,9 @@
/**
* @brief Update on the fly the SMARTCARD block length in RTOR register.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
- * @param BlockLength: SMARTCARD block length (8-bit long at most)
+ * @param BlockLength SMARTCARD block length (8-bit long at most)
* @retval None
*/
void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
@@ -111,9 +109,9 @@ void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uin
/**
* @brief Update on the fly the receiver timeout value in RTOR register.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
- * @param TimeOutValue: receiver timeout value in number of baud blocks. The timeout
+ * @param TimeOutValue receiver timeout value in number of baud blocks. The timeout
* value must be less or equal to 0x0FFFFFFFF.
* @retval None
*/
@@ -125,7 +123,7 @@ void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_
/**
* @brief Enable the SMARTCARD receiver timeout feature.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @retval HAL status
*/
@@ -157,7 +155,7 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef
/**
* @brief Disable the SMARTCARD receiver timeout feature.
- * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @retval HAL status
*/
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smbus.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smbus.c
index 4b58fa1b5e..e1256ac71c 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smbus.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_smbus.c
@@ -2,25 +2,23 @@
******************************************************************************
* @file stm32f3xx_hal_smbus.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief SMBUS HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the System Management Bus (SMBus) peripheral,
* based on I2C principles of operation :
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral State and Errors functions
- *
+ *
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The SMBUS HAL driver can be used as follows:
-
+
(#) Declare a SMBUS_HandleTypeDef handle structure, for example:
- SMBUS_HandleTypeDef hsmbus;
+ SMBUS_HandleTypeDef hsmbus;
(#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API:
(##) Enable the SMBUSx interface clock
@@ -28,7 +26,7 @@
(+++) Enable the clock for the SMBUS GPIOs
(+++) Configure SMBUS pins as alternate function open-drain
(##) NVIC configuration if you need to use interrupt process
- (+++) Configure the SMBUSx interrupt priority
+ (+++) Configure the SMBUSx interrupt priority
(+++) Enable the NVIC SMBUS IRQ Channel
(#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode,
@@ -92,7 +90,7 @@
[..]
(@) You can refer to the SMBUS HAL driver header file for more useful macros
-
+
@endverbatim
******************************************************************************
* @attention
@@ -121,8 +119,8 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- ******************************************************************************
- */
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal.h"
@@ -156,7 +154,7 @@
/**
* @}
*/
-
+
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -172,6 +170,8 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus);
static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus);
+static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus);
+
static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
/**
* @}
@@ -184,19 +184,19 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre
*/
/** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
- [..] This subsection provides a set of functions allowing to initialize and
+ [..] This subsection provides a set of functions allowing to initialize and
deinitialize the SMBUSx peripheral:
- (+) User must Implement HAL_SMBUS_MspInit() function in which he configures
+ (+) User must Implement HAL_SMBUS_MspInit() function in which he configures
all related peripherals resources (CLOCK, GPIO, IT and NVIC ).
- (+) Call the function HAL_SMBUS_Init() to configure the selected device with
+ (+) Call the function HAL_SMBUS_Init() to configure the selected device with
the selected configuration:
(++) Clock Timing
(++) Bus Timeout
@@ -212,28 +212,31 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre
(++) Peripheral mode
- (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
- of the selected SMBUSx peripheral.
+ (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
+ of the selected SMBUSx peripheral.
+
+ (+) Enable/Disable Analog/Digital filters with HAL_SMBUS_ConfigAnalogFilter() and
+ HAL_SMBUS_ConfigDigitalFilter().
@endverbatim
* @{
*/
/**
- * @brief Initialize the SMBUS according to the specified parameters
+ * @brief Initialize the SMBUS according to the specified parameters
* in the SMBUS_InitTypeDef and initialize the associated handle.
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
-{
+{
/* Check the SMBUS handle allocation */
- if(hsmbus == NULL)
+ if (hsmbus == NULL)
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter));
@@ -247,7 +250,7 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode));
assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode));
- if(hsmbus->State == HAL_SMBUS_STATE_RESET)
+ if (hsmbus->State == HAL_SMBUS_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hsmbus->Lock = HAL_UNLOCKED;
@@ -255,17 +258,17 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_SMBUS_MspInit(hsmbus);
}
-
+
hsmbus->State = HAL_SMBUS_STATE_BUSY;
-
+
/* Disable the selected SMBUS peripheral */
__HAL_SMBUS_DISABLE(hsmbus);
-
- /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/
+
+ /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/
/* Configure SMBUSx: Frequency range */
hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK;
-
- /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/
+
+ /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/
/* Configure SMBUSx: Bus Timeout */
hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN;
hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN;
@@ -274,10 +277,10 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
/*---------------------------- SMBUSx OAR1 Configuration -----------------------*/
/* Configure SMBUSx: Own Address1 and ack own address1 mode */
hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
-
- if(hsmbus->Init.OwnAddress1 != 0U)
+
+ if (hsmbus->Init.OwnAddress1 != 0U)
{
- if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
+ if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
{
hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1);
}
@@ -289,41 +292,41 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
/*---------------------------- SMBUSx CR2 Configuration ------------------------*/
/* Configure SMBUSx: Addressing Master mode */
- if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT)
+ if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT)
{
hsmbus->Instance->CR2 = (I2C_CR2_ADD10);
}
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */
/* AUTOEND and NACK bit will be manage during Transfer process */
hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
-
- /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/
+
+ /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/
/* Configure SMBUSx: Dual mode and Own Address2 */
hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8U));
/*---------------------------- SMBUSx CR1 Configuration ------------------------*/
/* Configure SMBUSx: Generalcall and NoStretch mode */
hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter);
-
+
/* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */
- if( (hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE)
- && ( (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP) ) )
+ if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE)
+ && ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)))
{
hsmbus->Instance->CR1 |= I2C_CR1_SBC;
}
/* Enable the selected SMBUS peripheral */
__HAL_SMBUS_ENABLE(hsmbus);
-
+
hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
hsmbus->State = HAL_SMBUS_STATE_READY;
-
+
return HAL_OK;
}
/**
- * @brief DeInitialize the SMBUS peripheral.
+ * @brief DeInitialize the SMBUS peripheral.
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @retval HAL status
@@ -331,29 +334,29 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
{
/* Check the SMBUS handle allocation */
- if(hsmbus == NULL)
+ if (hsmbus == NULL)
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
-
+
hsmbus->State = HAL_SMBUS_STATE_BUSY;
-
+
/* Disable the SMBUS Peripheral Clock */
__HAL_SMBUS_DISABLE(hsmbus);
-
+
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_SMBUS_MspDeInit(hsmbus);
-
+
hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
hsmbus->PreviousState = HAL_SMBUS_STATE_RESET;
hsmbus->State = HAL_SMBUS_STATE_RESET;
-
- /* Release Lock */
+
+ /* Release Lock */
__HAL_UNLOCK(hsmbus);
-
+
return HAL_OK;
}
@@ -370,7 +373,7 @@ __weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus)
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SMBUS_MspInit could be implemented in the user file
- */
+ */
}
/**
@@ -386,7 +389,105 @@ __weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SMBUS_MspDeInit could be implemented in the user file
- */
+ */
+}
+
+/**
+ * @brief Configure Analog noise filter.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param AnalogFilter This parameter can be one of the following values:
+ * @arg @ref SMBUS_ANALOGFILTER_ENABLE
+ * @arg @ref SMBUS_ANALOGFILTER_DISABLE
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
+{
+ /* Check the parameters */
+ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+ assert_param(IS_SMBUS_ANALOG_FILTER(AnalogFilter));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the selected SMBUS peripheral */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ /* Reset ANOFF bit */
+ hsmbus->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
+
+ /* Set analog filter bit*/
+ hsmbus->Instance->CR1 |= AnalogFilter;
+
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Configure Digital noise filter.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
+{
+ uint32_t tmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+ assert_param(IS_SMBUS_DIGITAL_FILTER(DigitalFilter));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the selected SMBUS peripheral */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ /* Get the old register value */
+ tmpreg = hsmbus->Instance->CR1;
+
+ /* Reset I2C DNF bits [11:8] */
+ tmpreg &= ~(I2C_CR1_DNF);
+
+ /* Set I2Cx DNF coefficient */
+ tmpreg |= DigitalFilter << I2C_CR1_DNF_Pos;
+
+ /* Store the new register value */
+ hsmbus->Instance->CR1 = tmpreg;
+
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
}
/**
@@ -394,14 +495,14 @@ __weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
*/
/** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
- * @brief Data transfers functions
+ * @brief Data transfers functions
*
-@verbatim
+@verbatim
===============================================================================
##### IO operation functions #####
- ===============================================================================
+ ===============================================================================
[..]
- This subsection provides a set of functions allowing to manage the SMBUS data
+ This subsection provides a set of functions allowing to manage the SMBUS data
transfers.
(#) Blocking mode function to check if device is ready for usage is :
@@ -410,7 +511,7 @@ __weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
(#) There is only one mode of transfer:
(++) Non-Blocking mode : The communication is performed using Interrupts.
These functions return the status of the transfer startup.
- The end of the data processing will be indicated through the
+ The end of the data processing will be indicated through the
dedicated SMBUS IRQ when using Interrupt mode.
(#) Non-Blocking mode functions with Interrupt are :
@@ -448,15 +549,15 @@ __weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
-{
+{
/* Check the parameters */
assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if(hsmbus->State == HAL_SMBUS_STATE_READY)
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hsmbus);
-
+
hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
/* Prepare transfer parameters */
@@ -466,12 +567,12 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint
/* In case of Quick command, remove autoend mode */
/* Manage the stop generation by software */
- if(hsmbus->pBuffPtr == NULL)
+ if (hsmbus->pBuffPtr == NULL)
{
hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
}
- if(Size > MAX_NBYTE_SIZE)
+ if (Size > MAX_NBYTE_SIZE)
{
hsmbus->XferSize = MAX_NBYTE_SIZE;
}
@@ -482,17 +583,17 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint
/* Send Slave Address */
/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
- if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
+ if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount))
{
- SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
+ SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
}
else
{
/* If transfer direction not change, do not generate Restart Condition */
/* Mean Previous state is same as current state */
- if((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0))
+ if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0))
{
- SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
}
/* Else transfer direction change, so generate Restart with new transfer direction */
else
@@ -501,32 +602,32 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint
SMBUS_ConvertOtherXferOptions(hsmbus);
/* Handle Transfer */
- SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
+ SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
}
/* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
- if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+ if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
{
hsmbus->XferSize--;
hsmbus->XferCount--;
}
}
-
+
/* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
+ __HAL_UNLOCK(hsmbus);
- /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
to avoid the risk of SMBUS interrupt handle execution before current
process unlock */
SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
-
+
return HAL_OK;
}
else
{
return HAL_BUSY;
- }
+ }
}
/**
@@ -545,27 +646,27 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1
/* Check the parameters */
assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if(hsmbus->State == HAL_SMBUS_STATE_READY)
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hsmbus);
-
+
hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
-
+
/* Prepare transfer parameters */
hsmbus->pBuffPtr = pData;
hsmbus->XferCount = Size;
hsmbus->XferOptions = XferOptions;
-
+
/* In case of Quick command, remove autoend mode */
/* Manage the stop generation by software */
- if(hsmbus->pBuffPtr == NULL)
+ if (hsmbus->pBuffPtr == NULL)
{
hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
}
-
- if(Size > MAX_NBYTE_SIZE)
+
+ if (Size > MAX_NBYTE_SIZE)
{
hsmbus->XferSize = MAX_NBYTE_SIZE;
}
@@ -573,20 +674,20 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1
{
hsmbus->XferSize = Size;
}
-
+
/* Send Slave Address */
/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
- if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
+ if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount))
{
- SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
+ SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
}
else
{
/* If transfer direction not change, do not generate Restart Condition */
/* Mean Previous state is same as current state */
- if((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0))
+ if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0))
{
- SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
}
/* Else transfer direction change, so generate Restart with new transfer direction */
else
@@ -595,24 +696,24 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1
SMBUS_ConvertOtherXferOptions(hsmbus);
/* Handle Transfer */
- SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
+ SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
}
}
-
+
/* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
+ __HAL_UNLOCK(hsmbus);
- /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
to avoid the risk of SMBUS interrupt handle execution before current
process unlock */
SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
-
+
return HAL_OK;
}
else
{
- return HAL_BUSY;
- }
+ return HAL_BUSY;
+ }
}
/**
@@ -626,18 +727,18 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1
*/
HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
{
- if(hsmbus->State == HAL_SMBUS_STATE_READY)
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hsmbus);
-
+
/* Keep the same state as previous */
/* to perform as well the call of the corresponding end of transfer callback */
- if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
{
hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
}
- else if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ else if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
{
hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
}
@@ -648,32 +749,32 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_
return HAL_ERROR;
}
hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
-
+
/* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */
/* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
SMBUS_TransferConfig(hsmbus, DevAddress, 1U, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP);
-
+
/* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
+ __HAL_UNLOCK(hsmbus);
- /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
to avoid the risk of SMBUS interrupt handle execution before current
process unlock */
- if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
{
SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
}
- else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
{
SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
}
-
+
return HAL_OK;
}
else
{
- return HAL_BUSY;
- }
+ return HAL_BUSY;
+ }
}
/**
@@ -690,11 +791,11 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8
/* Check the parameters */
assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+ if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
/* Disable Interrupts, to prevent preemption during treatment in case of multicall */
@@ -702,10 +803,10 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8
/* Process Locked */
__HAL_LOCK(hsmbus);
-
+
hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_TX;
hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
-
+
/* Set SBC bit to manage Acknowledge at each bit */
hsmbus->Instance->CR1 |= I2C_CR1_SBC;
@@ -720,7 +821,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8
/* Convert OTHER_xxx XferOptions if any */
SMBUS_ConvertOtherXferOptions(hsmbus);
- if(Size > MAX_NBYTE_SIZE)
+ if (Size > MAX_NBYTE_SIZE)
{
hsmbus->XferSize = MAX_NBYTE_SIZE;
}
@@ -730,32 +831,32 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8
}
/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
- if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
+ if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount))
{
- SMBUS_TransferConfig(hsmbus, 0U,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
}
else
{
/* Set NBYTE to transmit */
- SMBUS_TransferConfig(hsmbus, 0U,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
- if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+ if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
{
hsmbus->XferSize--;
hsmbus->XferCount--;
}
}
-
+
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the HOST */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
/* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
+ __HAL_UNLOCK(hsmbus);
- /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
to avoid the risk of SMBUS interrupt handle execution before current
process unlock */
/* REnable ADDR interrupt */
@@ -765,8 +866,8 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8
}
else
{
- return HAL_ERROR;
- }
+ return HAL_ERROR;
+ }
}
/**
@@ -783,22 +884,22 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_
/* Check the parameters */
assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+ if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
-
+
/* Disable Interrupts, to prevent preemption during treatment in case of multicall */
SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX);
/* Process Locked */
__HAL_LOCK(hsmbus);
-
+
hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_RX;
hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
-
+
/* Set SBC bit to manage Acknowledge at each bit */
hsmbus->Instance->CR1 |= I2C_CR1_SBC;
@@ -819,7 +920,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_
/* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */
/* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */
/* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
- if((hsmbus->XferSize == 1U) || ((hsmbus->XferSize == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET)))
+ if ((hsmbus->XferSize == 1U) || ((hsmbus->XferSize == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET)))
{
SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
}
@@ -830,12 +931,12 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the HOST */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
/* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
+ __HAL_UNLOCK(hsmbus);
- /* Note : The SMBUS interrupts must be enabled after unlocking current process
+ /* Note : The SMBUS interrupts must be enabled after unlocking current process
to avoid the risk of SMBUS interrupt handle execution before current
process unlock */
/* REnable ADDR interrupt */
@@ -845,7 +946,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_
}
else
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
}
@@ -858,10 +959,10 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_
HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus)
{
hsmbus->State = HAL_SMBUS_STATE_LISTEN;
-
+
/* Enable the Address Match interrupt */
SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR);
-
+
return HAL_OK;
}
@@ -874,13 +975,13 @@ HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus)
HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus)
{
/* Disable Address listen mode only if a transfer is not ongoing */
- if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+ if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
{
hsmbus->State = HAL_SMBUS_STATE_READY;
-
+
/* Disable the Address Match interrupt */
SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR);
-
+
return HAL_OK;
}
else
@@ -898,7 +999,7 @@ HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus)
HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
{
/* Enable SMBus alert */
- hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN;
+ hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN;
/* Clear ALERT flag */
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
@@ -906,7 +1007,7 @@ HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
/* Enable Alert Interrupt */
SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT);
- return HAL_OK;
+ return HAL_OK;
}
/**
* @brief Disable the SMBUS alert mode with Interrupt.
@@ -917,16 +1018,16 @@ HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
{
/* Enable SMBus alert */
- hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN;
-
+ hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN;
+
/* Disable Alert Interrupt */
SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT);
- return HAL_OK;
+ return HAL_OK;
}
/**
- * @brief Check if target device is ready for communication.
+ * @brief Check if target device is ready for communication.
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @param DevAddress Target device address: The device 7 bits address value
@@ -936,72 +1037,72 @@ HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
-{
+{
uint32_t tickstart = 0U;
-
+
__IO uint32_t SMBUS_Trials = 0U;
-
- if(hsmbus->State == HAL_SMBUS_STATE_READY)
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
{
- if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET)
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hsmbus);
-
+
hsmbus->State = HAL_SMBUS_STATE_BUSY;
hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
-
+
do
{
/* Generate Start */
- hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode,DevAddress);
-
+ hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode, DevAddress);
+
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is set or a NACK flag is set*/
tickstart = HAL_GetTick();
- while((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT))
+ while ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT))
{
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
/* Device is ready */
hsmbus->State = HAL_SMBUS_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
return HAL_TIMEOUT;
}
- }
+ }
}
-
+
/* Check if the NACKF flag has not been set */
if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET)
{
- /* Wait until STOPF flag is reset */
- if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ /* Wait until STOPF flag is reset */
+ if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
-
+
/* Clear STOP Flag */
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
/* Device is ready */
hsmbus->State = HAL_SMBUS_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
-
+
return HAL_OK;
}
else
{
- /* Wait until STOPF flag is reset */
- if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ /* Wait until STOPF flag is reset */
+ if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -1012,31 +1113,32 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t
/* Clear STOP Flag, auto generated with autoend*/
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
}
-
+
/* Check if the maximum allowed number of trials has been reached */
if (SMBUS_Trials++ == Trials)
{
/* Generate Stop */
hsmbus->Instance->CR2 |= I2C_CR2_STOP;
-
- /* Wait until STOPF flag is reset */
- if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+
+ /* Wait until STOPF flag is reset */
+ if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
-
+
/* Clear STOP Flag */
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
- }
- }while(SMBUS_Trials < Trials);
+ }
+ }
+ while (SMBUS_Trials < Trials);
hsmbus->State = HAL_SMBUS_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
-
+
return HAL_TIMEOUT;
- }
+ }
else
{
return HAL_BUSY;
@@ -1059,28 +1161,28 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t
void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
{
uint32_t tmpisrvalue = 0U;
-
+
/* Use a local variable to store the current ISR flags */
/* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
tmpisrvalue = SMBUS_GET_ISR_REG(hsmbus);
-
+
/* SMBUS in mode Transmitter ---------------------------------------------------*/
- if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET))
- {
+ if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET))
+ {
/* Slave mode selected */
if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
{
SMBUS_Slave_ISR(hsmbus);
}
/* Master mode selected */
- else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX)
{
SMBUS_Master_ISR(hsmbus);
}
}
-
+
/* SMBUS in mode Receiver ----------------------------------------------------*/
- if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET))
+ if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET))
{
/* Slave mode selected */
if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
@@ -1088,15 +1190,15 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
SMBUS_Slave_ISR(hsmbus);
}
/* Master mode selected */
- else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX)
{
SMBUS_Master_ISR(hsmbus);
}
- }
-
- /* SMBUS in mode Listener Only --------------------------------------------------*/
+ }
+
+ /* SMBUS in mode Listener Only --------------------------------------------------*/
if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))
- && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET)))
+ && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET)))
{
if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
{
@@ -1113,79 +1215,7 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
*/
void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
{
- /* SMBUS Bus error interrupt occurred ------------------------------------*/
- if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
- {
- hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
-
- /* Clear BERR flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR);
- }
-
- /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
- if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_OVR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
- {
- hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
-
- /* Clear OVR flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR);
- }
-
- /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
- if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ARLO) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
- {
- hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
-
- /* Clear ARLO flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO);
- }
-
- /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
- if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
- {
- hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
-
- /* Clear TIMEOUT flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT);
- }
-
- /* SMBUS Alert error interrupt occurred -----------------------------------------------*/
- if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ALERT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
- {
- hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
-
- /* Clear ALERT flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
- }
-
- /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
- if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_PECERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
- {
- hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
-
- /* Clear PEC error flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
- }
-
- /* Call the Error Callback in case of Error detected */
- if((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)&&(hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF))
- {
- /* Do not Reset the HAL state in case of ALERT error */
- if((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
- {
- if(((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
- || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX))
- {
- /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */
- /* keep HAL_SMBUS_STATE_LISTEN if set */
- hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
- hsmbus->State = HAL_SMBUS_STATE_LISTEN;
- }
- }
-
- /* Call the Error callback to prevent upper layer */
- HAL_SMBUS_ErrorCallback(hsmbus);
- }
+ SMBUS_ITErrorHandler(hsmbus);
}
/**
@@ -1201,7 +1231,7 @@ __weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SMBUS_MasterTxCpltCallback() could be implemented in the user file
- */
+ */
}
/**
@@ -1232,7 +1262,7 @@ __weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SMBUS_SlaveTxCpltCallback() could be implemented in the user file
- */
+ */
}
/**
@@ -1255,8 +1285,8 @@ __weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
* @brief Slave Address Match callback.
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
- * @param TransferDirection: Master request Transfer Direction (Write/Read)
- * @param AddrMatchCode: Address Match Code
+ * @param TransferDirection Master request Transfer Direction (Write/Read)
+ * @param AddrMatchCode Address Match Code
* @retval None
*/
__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
@@ -1300,22 +1330,22 @@ __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SMBUS_ErrorCallback() could be implemented in the user file
- */
+ */
}
/**
* @}
*/
-/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief Peripheral State and Errors functions
+/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief Peripheral State and Errors functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
- ===============================================================================
+ ===============================================================================
[..]
- This subsection permits to get in run-time the status of the peripheral
+ This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
@@ -1347,14 +1377,14 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
/**
* @}
- */
+ */
/**
* @}
- */
+ */
/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
- * @brief Data transfers Private functions
+ * @brief Data transfers Private functions
* @{
*/
@@ -1364,42 +1394,45 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
* the configuration information for the specified SMBUS.
* @retval HAL status
*/
-static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
+static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
{
uint16_t DevAddress;
/* Process Locked */
__HAL_LOCK(hsmbus);
-
- if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
+
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
{
/* Clear NACK Flag */
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
-
+
/* Set corresponding Error Code */
/* No need to generate STOP, it is automatically done */
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
-
- /* Call the Error callback to prevent upper layer */
+
+ /* Call the Error callback to inform upper layer */
HAL_SMBUS_ErrorCallback(hsmbus);
}
- else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
+ else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
{
+ /* Check and treat errors if errors occurs during STOP process */
+ SMBUS_ITErrorHandler(hsmbus);
+
/* Call the corresponding callback to inform upper layer of End of Transfer */
- if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
{
/* Disable Interrupt */
SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
/* Clear STOP Flag */
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
-
+
/* Clear Configuration Register 2 */
SMBUS_RESET_CR2(hsmbus);
-
+
/* Flush remaining data in Fifo register in case of error occurs before TXEmpty */
/* Disable the selected SMBUS peripheral */
__HAL_SMBUS_DISABLE(hsmbus);
@@ -1409,21 +1442,21 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
-
+
/* REenable the selected SMBUS peripheral */
__HAL_SMBUS_ENABLE(hsmbus);
HAL_SMBUS_MasterTxCpltCallback(hsmbus);
}
- else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
{
/* Store Last receive data if any */
- if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
{
/* Read data from RXDR */
(*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
- if((hsmbus->XferSize > 0U))
+ if ((hsmbus->XferSize > 0U))
{
hsmbus->XferSize--;
hsmbus->XferCount--;
@@ -1435,64 +1468,64 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
/* Clear STOP Flag */
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
-
+
/* Clear Configuration Register 2 */
SMBUS_RESET_CR2(hsmbus);
-
+
hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
hsmbus->State = HAL_SMBUS_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
-
+
HAL_SMBUS_MasterRxCpltCallback(hsmbus);
}
}
- else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
- {
+ else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
+ {
/* Read data from RXDR */
(*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
hsmbus->XferSize--;
hsmbus->XferCount--;
}
- else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
+ else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
{
/* Write data to TXDR */
hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
hsmbus->XferSize--;
- hsmbus->XferCount--;
+ hsmbus->XferCount--;
}
- else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)
+ else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)
{
- if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount != 0U))
+ if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U))
{
DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD);
-
- if(hsmbus->XferCount > MAX_NBYTE_SIZE)
- {
+
+ if (hsmbus->XferCount > MAX_NBYTE_SIZE)
+ {
SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
hsmbus->XferSize = MAX_NBYTE_SIZE;
}
else
{
hsmbus->XferSize = hsmbus->XferCount;
- SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
- if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+ if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
{
hsmbus->XferSize--;
hsmbus->XferCount--;
}
}
}
- else if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount == 0U))
+ else if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount == 0U))
{
/* Call TxCpltCallback() if no stop mode is set */
- if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
+ if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
- if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
{
/* Disable Interrupt */
SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
@@ -1501,10 +1534,10 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
-
+
HAL_SMBUS_MasterTxCpltCallback(hsmbus);
}
- else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
{
SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
hsmbus->PreviousState = hsmbus->State;
@@ -1512,30 +1545,30 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
-
+
HAL_SMBUS_MasterRxCpltCallback(hsmbus);
}
}
}
}
- else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET)
+ else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET)
{
- if(hsmbus->XferCount == 0U)
+ if (hsmbus->XferCount == 0U)
{
/* Specific use case for Quick command */
- if(hsmbus->pBuffPtr == NULL)
+ if (hsmbus->pBuffPtr == NULL)
{
/* Generate a Stop command */
hsmbus->Instance->CR2 |= I2C_CR2_STOP;
}
/* Call TxCpltCallback() if no stop mode is set */
- else if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
+ else if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
{
/* No Generate Stop, to permit restart mode */
/* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */
-
+
/* Call the corresponding callback to inform upper layer of End of Transfer */
- if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
{
/* Disable Interrupt */
SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
@@ -1544,10 +1577,10 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
-
+
HAL_SMBUS_MasterTxCpltCallback(hsmbus);
}
- else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
{
SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
hsmbus->PreviousState = hsmbus->State;
@@ -1555,39 +1588,39 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
-
+
HAL_SMBUS_MasterRxCpltCallback(hsmbus);
}
}
}
}
-
+
/* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- return HAL_OK;
-}
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+}
/**
* @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @retval HAL status
*/
-static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
+static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
{
uint8_t TransferDirection = 0U;
uint16_t SlaveAddrCode = 0U;
/* Process Locked */
__HAL_LOCK(hsmbus);
-
- if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
+
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
{
/* Check that SMBUS transfer finished */
/* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */
/* Mean XferCount == 0*/
/* So clear Flag NACKF only */
- if(hsmbus->XferCount == 0U)
+ if (hsmbus->XferCount == 0U)
{
/* Clear NACK Flag */
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
@@ -1609,58 +1642,58 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
/* Disable RX/TX Interrupts, keep only ADDR Interrupt */
SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX);
-
+
/* Set ErrorCode corresponding to a Non-Acknowledge */
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
-
- /* Call the Error callback to prevent upper layer */
+
+ /* Call the Error callback to inform upper layer */
HAL_SMBUS_ErrorCallback(hsmbus);
}
}
- else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET)
+ else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET)
{
TransferDirection = SMBUS_GET_DIR(hsmbus);
SlaveAddrCode = SMBUS_GET_ADDR_MATCH(hsmbus);
-
+
/* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
/* Other ADDRInterrupt will be treat in next Listen usecase */
__HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI);
-
+
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
/* Call Slave Addr callback */
HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
}
- else if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET))
+ else if ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET))
{
- if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
+ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
{
/* Read data from RXDR */
(*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
hsmbus->XferSize--;
hsmbus->XferCount--;
- if(hsmbus->XferCount == 1U)
+ if (hsmbus->XferCount == 1U)
{
/* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */
/* or only the last Byte of Transfer */
/* So reset the RELOAD bit mode */
hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE;
- SMBUS_TransferConfig(hsmbus, 0U ,1U , hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0U , 1U , hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
}
- else if(hsmbus->XferCount == 0U)
+ else if (hsmbus->XferCount == 0U)
{
/* Last Byte is received, disable Interrupt */
SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
-
+
/* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */
hsmbus->PreviousState = hsmbus->State;
hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX);
-
+
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
@@ -1675,13 +1708,13 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
/* Ack last Byte Read */
hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
}
- }
- else if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
+ }
+ else if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
{
- if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount != 0U))
+ if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U))
{
- if(hsmbus->XferCount > MAX_NBYTE_SIZE)
- {
+ if (hsmbus->XferCount > MAX_NBYTE_SIZE)
+ {
SMBUS_TransferConfig(hsmbus, 0U, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
hsmbus->XferSize = MAX_NBYTE_SIZE;
}
@@ -1691,7 +1724,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
- if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+ if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
{
hsmbus->XferSize--;
hsmbus->XferCount--;
@@ -1700,21 +1733,21 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
}
}
}
- else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
+ else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
{
/* Write data to TXDR only if XferCount not reach "0" */
/* A TXIS flag can be set, during STOP treatment */
/* Check if all Data have already been sent */
/* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
- if(hsmbus->XferCount > 0U)
+ if (hsmbus->XferCount > 0U)
{
/* Write data to TXDR */
hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
hsmbus->XferCount--;
hsmbus->XferSize--;
}
-
- if(hsmbus->XferCount == 0U)
+
+ if (hsmbus->XferCount == 0U)
{
/* Last Byte is Transmitted */
/* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */
@@ -1731,17 +1764,17 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
}
/* Check if STOPF is set */
- if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
{
- if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
+ if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
{
/* Store Last receive data if any */
- if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
{
/* Read data from RXDR */
(*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
- if((hsmbus->XferSize > 0U))
+ if ((hsmbus->XferSize > 0U))
{
hsmbus->XferSize--;
hsmbus->XferCount--;
@@ -1759,30 +1792,30 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
/* Clear Configuration Register 2 */
SMBUS_RESET_CR2(hsmbus);
-
+
/* Clear STOP Flag */
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
- /* Clear ADDR flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
+ /* Clear ADDR flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
hsmbus->XferOptions = 0U;
hsmbus->PreviousState = hsmbus->State;
hsmbus->State = HAL_SMBUS_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
- /* Call the Listen Complete callback, to prevent upper layer of the end of Listen usecase */
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
HAL_SMBUS_ListenCpltCallback(hsmbus);
}
}
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
-
- return HAL_OK;
-}
+
+ return HAL_OK;
+}
/**
* @brief Manage the enabling of Interrupts.
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
@@ -1790,40 +1823,40 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
* @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
* @retval HAL status
*/
-static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
+static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
{
uint32_t tmpisr = 0U;
- if((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
+ if ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
{
/* Enable ERR interrupt */
tmpisr |= SMBUS_IT_ERRI;
}
-
- if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
+
+ if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
{
/* Enable ADDR, STOP interrupt */
tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI;
}
-
- if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
+
+ if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
{
/* Enable ERR, TC, STOP, NACK, RXI interrupt */
tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI;
}
-
- if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
+
+ if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
{
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI;
}
-
+
/* Enable interrupts only at the end */
/* to avoid the risk of SMBUS interrupt handle execution before */
/* all interrupts requested done */
__HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr);
- return HAL_OK;
+ return HAL_OK;
}
/**
* @brief Manage the disabling of Interrupts.
@@ -1832,60 +1865,60 @@ static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t
* @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
* @retval HAL status
*/
-static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
+static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
{
uint32_t tmpisr = 0U;
- if( ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY) )
+ if (((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY))
{
/* Disable ERR interrupt */
tmpisr |= SMBUS_IT_ERRI;
}
-
- if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
+
+ if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
{
/* Disable TC, STOP, NACK, TXI interrupt */
tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI;
-
- if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
- && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
+
+ if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
+ && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
{
/* Disable ERR interrupt */
tmpisr |= SMBUS_IT_ERRI;
}
-
- if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
+
+ if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
{
/* Disable STOPI, NACKI */
tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
}
}
-
- if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
+
+ if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
{
/* Disable TC, STOP, NACK, RXI interrupt */
tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI;
-
- if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
- && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
+
+ if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
+ && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
{
/* Disable ERR interrupt */
tmpisr |= SMBUS_IT_ERRI;
}
- if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
+ if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
{
/* Disable STOPI, NACKI */
tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
}
}
-
- if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
+
+ if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
{
/* Enable ADDR, STOP interrupt */
tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI;
- if(SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
+ if (SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
{
/* Disable ERR interrupt */
tmpisr |= SMBUS_IT_ERRI;
@@ -1896,9 +1929,95 @@ static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t
/* to avoid a breaking situation like at "t" time */
/* all disable interrupts request are not done */
__HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr);
-
+
return HAL_OK;
}
+
+/**
+ * @brief SMBUS interrupts error handler.
+ * @param hsmbus SMBUS handle.
+ * @retval None
+ */
+static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
+{
+ uint32_t itflags = READ_REG(hsmbus->Instance->ISR);
+ uint32_t itsources = READ_REG(hsmbus->Instance->CR1);
+
+ /* SMBUS Bus error interrupt occurred ------------------------------------*/
+ if (((itflags & SMBUS_FLAG_BERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
+
+ /* Clear BERR flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR);
+ }
+
+ /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
+ if (((itflags & SMBUS_FLAG_OVR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
+
+ /* Clear OVR flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR);
+ }
+
+ /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
+ if (((itflags & SMBUS_FLAG_ARLO) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
+
+ /* Clear ARLO flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO);
+ }
+
+ /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
+ if (((itflags & SMBUS_FLAG_TIMEOUT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
+
+ /* Clear TIMEOUT flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT);
+ }
+
+ /* SMBUS Alert error interrupt occurred -----------------------------------------------*/
+ if (((itflags & SMBUS_FLAG_ALERT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
+
+ /* Clear ALERT flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
+ }
+
+ /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
+ if (((itflags & SMBUS_FLAG_PECERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
+
+ /* Clear PEC error flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
+ }
+
+ /* Call the Error Callback in case of Error detected */
+ if ((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE) && (hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF))
+ {
+ /* Do not Reset the HAL state in case of ALERT error */
+ if ((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
+ {
+ if (((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
+ || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX))
+ {
+ /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */
+ /* keep HAL_SMBUS_STATE_LISTEN if set */
+ hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+ hsmbus->State = HAL_SMBUS_STATE_LISTEN;
+ }
+ }
+
+ /* Call the Error callback to inform upper layer */
+ HAL_SMBUS_ErrorCallback(hsmbus);
+ }
+}
+
/**
* @brief Handle SMBUS Communication Timeout.
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
@@ -1908,26 +2027,26 @@ static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t
* @param Timeout Timeout duration
* @retval HAL status
*/
-static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
-{
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
uint32_t tickstart = HAL_GetTick();
-
+
/* Wait until flag is set */
- if(Status == RESET)
- {
- while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET)
+ if (Status == RESET)
+ {
+ while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET)
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
hsmbus->PreviousState = hsmbus->State;
- hsmbus->State= HAL_SMBUS_STATE_READY;
-
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
-
+
return HAL_TIMEOUT;
}
}
@@ -1935,25 +2054,25 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu
}
else
{
- while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET)
+ while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET)
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
hsmbus->PreviousState = hsmbus->State;
- hsmbus->State= HAL_SMBUS_STATE_READY;
-
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
-
+
return HAL_TIMEOUT;
}
}
}
}
- return HAL_OK;
+ return HAL_OK;
}
/**
@@ -1979,25 +2098,25 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu
static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
{
uint32_t tmpreg = 0U;
-
+
/* Check the parameters */
assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
assert_param(IS_SMBUS_TRANSFER_MODE(Mode));
assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
-
+
/* Get the CR2 register value */
tmpreg = hsmbus->Instance->CR2;
-
+
/* clear tmpreg specific bits */
tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE));
-
+
/* update tmpreg */
- tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16U ) & I2C_CR2_NBYTES) | \
- (uint32_t)Mode | (uint32_t)Request);
-
+ tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16U) & I2C_CR2_NBYTES) | \
+ (uint32_t)Mode | (uint32_t)Request);
+
/* update CR2 register */
- hsmbus->Instance->CR2 = tmpreg;
-}
+ hsmbus->Instance->CR2 = tmpreg;
+}
/**
* @brief Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions.
@@ -2009,14 +2128,14 @@ static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus)
/* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC */
/* it request implicitly to generate a restart condition */
/* set XferOptions to SMBUS_FIRST_FRAME */
- if(hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC)
+ if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC)
{
hsmbus->XferOptions = SMBUS_FIRST_FRAME;
}
/* else if user set XferOptions to SMBUS_OTHER_FRAME_WITH_PEC */
/* it request implicitly to generate a restart condition */
/* set XferOptions to SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE */
- else if(hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC)
+ else if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC)
{
hsmbus->XferOptions = SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE;
}
@@ -2024,7 +2143,7 @@ static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus)
/* it request implicitly to generate a restart condition */
/* then generate a stop condition at the end of transfer */
/* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_NO_PEC */
- else if(hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)
+ else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)
{
hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_NO_PEC;
}
@@ -2032,7 +2151,7 @@ static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus)
/* it request implicitly to generate a restart condition */
/* then generate a stop condition at the end of transfer */
/* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC */
- else if(hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)
+ else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)
{
hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC;
}
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c
index c49b5fe351..ee510ff24d 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_spi.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief SPI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Serial Peripheral Interface (SPI) peripheral:
@@ -65,6 +63,7 @@
maximum SPI frequency that can be reached with a data size of 8 or 16 bits, depending on
the APBx peripheral clock frequency (fPCLK) used by the SPI instance.
+
@endverbatim
Additional table :
@@ -266,7 +265,7 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_
/**
* @brief Initialize the SPI according to the specified parameters
* in the SPI_InitTypeDef and initialize the associated handle.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
*/
@@ -391,7 +390,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
/**
* @brief De-Initialize the SPI peripheral.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
*/
@@ -425,7 +424,7 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
/**
* @brief Initialize the SPI MSP.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -441,7 +440,7 @@ __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
/**
* @brief De-Initialize the SPI MSP.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -494,11 +493,11 @@ __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
/**
* @brief Transmit an amount of data in blocking mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
- * @param Timeout: Timeout duration
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
@@ -506,6 +505,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
uint32_t tickstart = 0U;
HAL_StatusTypeDef errorcode = HAL_OK;
+
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
@@ -673,11 +673,11 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
/**
* @brief Receive an amount of data in blocking mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be received
- * @param Timeout: Timeout duration
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be received
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
@@ -688,6 +688,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
uint32_t tickstart = 0U;
HAL_StatusTypeDef errorcode = HAL_OK;
+
if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
{
hspi->State = HAL_SPI_STATE_BUSY_RX;
@@ -737,7 +738,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
}
#endif /* USE_SPI_CRC */
- /* Set the Rx Fido threshold */
+ /* Set the Rx FiFo threshold */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
/* set fiforxthresold according the reception data length: 16bit */
@@ -903,12 +904,12 @@ error :
/**
* @brief Transmit and Receive an amount of data in blocking mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param pTxData: pointer to transmission data buffer
- * @param pRxData: pointer to reception data buffer
- * @param Size: amount of data to be sent and received
- * @param Timeout: Timeout duration
+ * @param pTxData pointer to transmission data buffer
+ * @param pRxData pointer to reception data buffer
+ * @param Size amount of data to be sent and received
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
@@ -923,6 +924,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
uint32_t txallowed = 1U;
HAL_StatusTypeDef errorcode = HAL_OK;
+
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
@@ -975,7 +977,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
}
#endif /* USE_SPI_CRC */
- /* Set the Rx Fido threshold */
+ /* Set the Rx Fifo threshold */
if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1U))
{
/* set fiforxthreshold according the reception data length: 16bit */
@@ -1195,16 +1197,17 @@ error :
/**
* @brief Transmit an amount of data in non-blocking mode with Interrupt.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
HAL_StatusTypeDef errorcode = HAL_OK;
+
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
@@ -1278,16 +1281,17 @@ error :
/**
* @brief Receive an amount of data in non-blocking mode with Interrupt.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
HAL_StatusTypeDef errorcode = HAL_OK;
+
if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
{
hspi->State = HAL_SPI_STATE_BUSY_RX;
@@ -1382,11 +1386,11 @@ error :
/**
* @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param pTxData: pointer to transmission data buffer
- * @param pRxData: pointer to reception data buffer
- * @param Size: amount of data to be sent and received
+ * @param pTxData pointer to transmission data buffer
+ * @param pRxData pointer to reception data buffer
+ * @param Size amount of data to be sent and received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
@@ -1394,6 +1398,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
uint32_t tmp = 0U, tmp1 = 0U;
HAL_StatusTypeDef errorcode = HAL_OK;
+
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
@@ -1490,16 +1495,16 @@ error :
/**
* @brief Transmit an amount of data in non-blocking mode with DMA.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
HAL_StatusTypeDef errorcode = HAL_OK;
-
+
/* check tx dma handle */
assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
@@ -1603,27 +1608,27 @@ error :
/**
* @brief Receive an amount of data in non-blocking mode with DMA.
* @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param pData: pointer to data buffer
+ * @param pData pointer to data buffer
* @note When the CRC feature is enabled the pData Length must be Size + 1.
- * @param Size: amount of data to be sent
+ * @param Size amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
HAL_StatusTypeDef errorcode = HAL_OK;
-
+
/* check rx dma handle */
assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
{
hspi->State = HAL_SPI_STATE_BUSY_RX;
-
+
/* check tx dma handle */
assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
-
+
/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
}
@@ -1745,12 +1750,12 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/**
* @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param pTxData: pointer to transmission data buffer
- * @param pRxData: pointer to reception data buffer
+ * @param pTxData pointer to transmission data buffer
+ * @param pRxData pointer to reception data buffer
* @note When the CRC feature is enabled the pRxData Length must be Size + 1
- * @param Size: amount of data to be sent
+ * @param Size amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
@@ -1758,7 +1763,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
{
uint32_t tmp = 0U, tmp1 = 0U;
HAL_StatusTypeDef errorcode = HAL_OK;
-
+
/* check rx & tx dma handles */
assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
@@ -2275,7 +2280,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
/**
* @brief Pause the DMA Transfer.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval HAL status
*/
@@ -2295,7 +2300,7 @@ HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
/**
* @brief Resume the DMA Transfer.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval HAL status
*/
@@ -2315,7 +2320,7 @@ HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
/**
* @brief Stop the DMA Transfer.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval HAL status
*/
@@ -2346,7 +2351,7 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
/**
* @brief Handle SPI interrupt request.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval None
*/
@@ -2442,7 +2447,7 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
/**
* @brief Tx Transfer completed callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2458,7 +2463,7 @@ __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
/**
* @brief Rx Transfer completed callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2474,7 +2479,7 @@ __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
/**
* @brief Tx and Rx Transfer completed callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2490,7 +2495,7 @@ __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
/**
* @brief Tx Half Transfer completed callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2506,7 +2511,7 @@ __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
/**
* @brief Rx Half Transfer completed callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2522,7 +2527,7 @@ __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
/**
* @brief Tx and Rx Half Transfer callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2538,7 +2543,7 @@ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
/**
* @brief SPI error callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2591,7 +2596,7 @@ __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
/**
* @brief Return the SPI handle state.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval SPI state
*/
@@ -2603,7 +2608,7 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
/**
* @brief Return the SPI error code.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval SPI error code in bitmap format
*/
@@ -2628,7 +2633,7 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
/**
* @brief DMA SPI transmit process complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -2675,7 +2680,7 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA SPI receive process complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -2766,7 +2771,7 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA SPI transmit receive process complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -2851,7 +2856,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA SPI half transmit process complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -2864,7 +2869,7 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA SPI half receive process complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -2877,7 +2882,7 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA SPI half transmit receive process complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -2890,7 +2895,7 @@ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA SPI communication error callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -3048,7 +3053,7 @@ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
/**
* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3098,7 +3103,7 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
#if (USE_SPI_CRC != 0U)
/**
* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3130,7 +3135,7 @@ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
/**
* @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3176,7 +3181,7 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
/**
* @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3210,7 +3215,7 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
#if (USE_SPI_CRC != 0U)
/**
* @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3234,7 +3239,7 @@ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
/**
* @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3272,7 +3277,7 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
#if (USE_SPI_CRC != 0U)
/**
* @brief Manage the CRC 8-bit receive in Interrupt context.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3297,7 +3302,7 @@ static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
/**
* @brief Manage the receive 8-bit in Interrupt context.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3330,7 +3335,7 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
#if (USE_SPI_CRC != 0U)
/**
* @brief Manage the CRC 16-bit receive in Interrupt context.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3353,7 +3358,7 @@ static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
/**
* @brief Manage the 16-bit receive in Interrupt context.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3386,7 +3391,7 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
/**
* @brief Handle the data 8-bit transmit in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3410,7 +3415,7 @@ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
/**
* @brief Handle the data 16-bit transmit in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3436,12 +3441,12 @@ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
/**
* @brief Handle SPI Communication Timeout.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param Flag: SPI flag to check
- * @param State: flag state to check
- * @param Timeout: Timeout duration
- * @param Tickstart: tick start value
+ * @param Flag SPI flag to check
+ * @param State flag state to check
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
@@ -3488,12 +3493,12 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi,
/**
* @brief Handle SPI FIFO Communication Timeout.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param Fifo: Fifo to check
- * @param State: Fifo state to check
- * @param Timeout: Timeout duration
- * @param Tickstart: tick start value
+ * @param Fifo Fifo to check
+ * @param State Fifo state to check
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
@@ -3549,10 +3554,10 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi,
/**
* @brief Handle the check of the RX transaction complete.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param Timeout: Timeout duration
- * @param Tickstart: tick start value
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
@@ -3586,9 +3591,9 @@ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t
/**
* @brief Handle the check of the RXTX or TX transaction complete.
- * @param hspi: SPI handle
- * @param Timeout: Timeout duration
- * @param Tickstart: tick start value
+ * @param hspi SPI handle
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
@@ -3599,18 +3604,26 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
return HAL_TIMEOUT;
}
+
/* Control the BSY flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
return HAL_TIMEOUT;
}
+
+ /* Control if the RX fifo is empty */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ return HAL_TIMEOUT;
+ }
return HAL_OK;
}
/**
* @brief Handle the end of the RXTX transaction.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3667,7 +3680,7 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
/**
* @brief Handle the end of the RX transaction.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3709,7 +3722,7 @@ static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
/**
* @brief Handle the end of the TX transaction.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3748,22 +3761,22 @@ static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
/**
* @brief Handle abort a Rx transaction.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
{
__IO uint32_t count;
-
+
/* Disable SPI Peripheral */
__HAL_SPI_DISABLE(hspi);
-
+
count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
/* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
-
+
/* Check RXNEIE is disabled */
do
{
@@ -3792,19 +3805,19 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
/**
* @brief Handle abort a Tx or Rx/Tx transaction.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
{
__IO uint32_t count;
-
+
count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
-
+
/* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
-
+
/* Check TXEIE is disabled */
do
{
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c
index 1dcfc672f6..f7607aa84b 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_spi_ex.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief Extended SPI HAL module driver.
* This file provides firmware functions to manage the following
* SPI peripheral extended functionalities :
@@ -91,7 +89,7 @@
/**
* @brief Flush the RX fifo.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval HAL status
*/
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_sram.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_sram.c
index a1fb0ad7d5..6b3610cfe1 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_sram.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_sram.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_sram.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief SRAM HAL module driver.
* This file provides a generic firmware to drive SRAM memories
* mounted as external device.
@@ -133,10 +131,10 @@
/**
* @brief Performs the SRAM device initialization sequence
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
- * @param Timing: Pointer to SRAM control timing structure
- * @param ExtTiming: Pointer to SRAM extended mode timing structure
+ * @param Timing Pointer to SRAM control timing structure
+ * @param ExtTiming Pointer to SRAM extended mode timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
@@ -173,7 +171,7 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTyp
/**
* @brief Performs the SRAM device De-initialization sequence.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval HAL status
*/
@@ -195,7 +193,7 @@ HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
/**
* @brief SRAM MSP Init.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval None
*/
@@ -211,7 +209,7 @@ __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
/**
* @brief SRAM MSP DeInit.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval None
*/
@@ -227,7 +225,7 @@ __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
/**
* @brief DMA transfer complete callback.
- * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval None
*/
@@ -243,7 +241,7 @@ __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
/**
* @brief DMA transfer complete error callback.
- * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval None
*/
@@ -277,11 +275,11 @@ __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
/**
* @brief Reads 8-bit buffer from SRAM memory.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
- * @param pAddress: Pointer to read start address
- * @param pDstBuffer: Pointer to destination buffer
- * @param BufferSize: Size of the buffer to read from memory
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
@@ -313,11 +311,11 @@ HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress
/**
* @brief Writes 8-bit buffer to SRAM memory.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
- * @param pAddress: Pointer to write start address
- * @param pSrcBuffer: Pointer to source buffer to write
- * @param BufferSize: Size of the buffer to write to memory
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
@@ -355,11 +353,11 @@ HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres
/**
* @brief Reads 16-bit buffer from SRAM memory.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
- * @param pAddress: Pointer to read start address
- * @param pDstBuffer: Pointer to destination buffer
- * @param BufferSize: Size of the buffer to read from memory
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
@@ -391,11 +389,11 @@ HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres
/**
* @brief Writes 16-bit buffer to SRAM memory.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
- * @param pAddress: Pointer to write start address
- * @param pSrcBuffer: Pointer to source buffer to write
- * @param BufferSize: Size of the buffer to write to memory
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
@@ -433,11 +431,11 @@ HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre
/**
* @brief Reads 32-bit buffer from SRAM memory.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
- * @param pAddress: Pointer to read start address
- * @param pDstBuffer: Pointer to destination buffer
- * @param BufferSize: Size of the buffer to read from memory
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
@@ -467,11 +465,11 @@ HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres
/**
* @brief Writes 32-bit buffer to SRAM memory.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
- * @param pAddress: Pointer to write start address
- * @param pSrcBuffer: Pointer to source buffer to write
- * @param BufferSize: Size of the buffer to write to memory
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
@@ -507,11 +505,11 @@ HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre
/**
* @brief Reads a Words data from the SRAM memory using DMA transfer.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
- * @param pAddress: Pointer to read start address
- * @param pDstBuffer: Pointer to destination buffer
- * @param BufferSize: Size of the buffer to read from memory
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
@@ -540,11 +538,11 @@ HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddres
/**
* @brief Writes a Words data buffer to SRAM memory using DMA transfer.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
- * @param pAddress: Pointer to write start address
- * @param pSrcBuffer: Pointer to source buffer to write
- * @param BufferSize: Size of the buffer to write to memory
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
@@ -598,7 +596,7 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre
/**
* @brief Enables dynamically SRAM write operation.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval HAL status
*/
@@ -621,7 +619,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
/**
* @brief Disables dynamically SRAM write operation.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval HAL status
*/
@@ -666,7 +664,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
/**
* @brief Returns the SRAM controller state
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval HAL state
*/
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c
index 6fa0ee753d..964139f6a2 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_tim.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer (TIM) peripheral:
@@ -196,7 +194,7 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
/**
* @brief Initializes the TIM Time base Unit according to the specified
* parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim: TIM Base handle
+ * @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
@@ -236,7 +234,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
/**
* @brief DeInitializes the TIM Base peripheral
- * @param htim: TIM Base handle
+ * @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
@@ -263,7 +261,7 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
/**
* @brief Initializes the TIM Base MSP.
- * @param htim: TIM handle
+ * @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
@@ -278,7 +276,7 @@ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
/**
* @brief DeInitializes TIM Base MSP.
- * @param htim: TIM handle
+ * @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
@@ -294,7 +292,7 @@ __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
/**
* @brief Starts the TIM Base generation.
- * @param htim: TIM handle
+ * @param htim TIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
@@ -317,7 +315,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
/**
* @brief Stops the TIM Base generation.
- * @param htim: TIM handle
+ * @param htim TIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
@@ -340,7 +338,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
/**
* @brief Starts the TIM Base generation in interrupt mode.
- * @param htim: TIM handle
+ * @param htim TIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
@@ -360,7 +358,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
/**
* @brief Stops the TIM Base generation in interrupt mode.
- * @param htim: TIM handle
+ * @param htim TIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
@@ -379,9 +377,9 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
/**
* @brief Starts the TIM Base generation in DMA mode.
- * @param htim: TIM handle
- * @param pData: The source Buffer address.
- * @param Length: The length of data to be transferred from memory to peripheral.
+ * @param htim TIM handle
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
@@ -425,7 +423,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat
/**
* @brief Stops the TIM Base generation in DMA mode.
- * @param htim: TIM handle
+ * @param htim TIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
@@ -474,7 +472,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
/**
* @brief Initializes the TIM Output Compare according to the specified
* parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim: TIM Output Compare handle
+ * @param htim TIM Output Compare handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
@@ -514,7 +512,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
/**
* @brief DeInitializes the TIM peripheral
- * @param htim: TIM Output Compare handle
+ * @param htim TIM Output Compare handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
@@ -541,7 +539,7 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
/**
* @brief Initializes the TIM Output Compare MSP.
- * @param htim: TIM handle
+ * @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
@@ -556,7 +554,7 @@ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
/**
* @brief DeInitializes TIM Output Compare MSP.
- * @param htim: TIM handle
+ * @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
@@ -571,8 +569,8 @@ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
/**
* @brief Starts the TIM Output Compare signal generation.
- * @param htim: TIM Output Compare handle
- * @param Channel: TIM Channel to be enabled
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -603,8 +601,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Stops the TIM Output Compare signal generation.
- * @param htim: TIM handle
- * @param Channel: TIM Channel to be disabled
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -635,8 +633,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Starts the TIM Output Compare signal generation in interrupt mode.
- * @param htim: TIM OC handle
- * @param Channel: TIM Channel to be enabled
+ * @param htim TIM OC handle
+ * @param Channel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -701,8 +699,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Stops the TIM Output Compare signal generation in interrupt mode.
- * @param htim: TIM Output Compare handle
- * @param Channel: TIM Channel to be disabled
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -767,15 +765,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Starts the TIM Output Compare signal generation in DMA mode.
- * @param htim: TIM Output Compare handle
- * @param Channel: TIM Channel to be enabled
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData: The source Buffer address.
- * @param Length: The length of data to be transferred from memory to TIM peripheral
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
@@ -886,8 +884,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
/**
* @brief Stops the TIM Output Compare signal generation in DMA mode.
- * @param htim: TIM Output Compare handle
- * @param Channel: TIM Channel to be disabled
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -981,7 +979,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Initializes the TIM PWM Time Base according to the specified
* parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim: TIM handle
+ * @param htim TIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
@@ -1021,7 +1019,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
/**
* @brief DeInitializes the TIM peripheral
- * @param htim: TIM handle
+ * @param htim TIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
@@ -1048,7 +1046,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
/**
* @brief Initializes the TIM PWM MSP.
- * @param htim: TIM handle
+ * @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
@@ -1063,7 +1061,7 @@ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
/**
* @brief DeInitializes TIM PWM MSP.
- * @param htim: TIM handle
+ * @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
@@ -1078,8 +1076,8 @@ __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
/**
* @brief Starts the PWM signal generation.
- * @param htim: TIM handle
- * @param Channel: TIM Channels to be enabled
+ * @param htim TIM handle
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1110,8 +1108,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Stops the PWM signal generation.
- * @param htim: TIM handle
- * @param Channel: TIM Channels to be disabled
+ * @param htim TIM handle
+ * @param Channel TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1145,8 +1143,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Starts the PWM signal generation in interrupt mode.
- * @param htim: TIM handle
- * @param Channel: TIM Channels to be enabled
+ * @param htim TIM handle
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1211,8 +1209,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel
/**
* @brief Stops the PWM signal generation in interrupt mode.
- * @param htim: TIM handle
- * @param Channel: TIM Channels to be disabled
+ * @param htim TIM handle
+ * @param Channel TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1277,15 +1275,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel
/**
* @brief Starts the TIM PWM signal generation in DMA mode.
- * @param htim: TIM handle
- * @param Channel: TIM Channels to be enabled
+ * @param htim TIM handle
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData: The source Buffer address.
- * @param Length: The length of data to be transferred from memory to TIM peripheral
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
@@ -1396,8 +1394,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
/**
* @brief Stops the TIM PWM signal generation in DMA mode.
- * @param htim: TIM handle
- * @param Channel: TIM Channels to be disabled
+ * @param htim TIM handle
+ * @param Channel TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1491,7 +1489,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
/**
* @brief Initializes the TIM Input Capture Time base according to the specified
* parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim: TIM Input Capture handle
+ * @param htim TIM Input Capture handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
@@ -1531,7 +1529,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
/**
* @brief DeInitializes the TIM peripheral
- * @param htim: TIM Input Capture handle
+ * @param htim TIM Input Capture handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
@@ -1558,7 +1556,7 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
/**
* @brief Initializes the TIM Input Capture MSP.
- * @param htim: TIM handle
+ * @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
@@ -1573,7 +1571,7 @@ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
/**
* @brief DeInitializes TIM Input Capture MSP.
- * @param htim: TIM handle
+ * @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
@@ -1588,8 +1586,8 @@ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
/**
* @brief Starts the TIM Input Capture measurement.
- * @param htim: TIM Input Capture handle
- * @param Channel: TIM Channels to be enabled
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1614,8 +1612,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Stops the TIM Input Capture measurement.
- * @param htim: TIM handle
- * @param Channel: TIM Channels to be disabled
+ * @param htim TIM handle
+ * @param Channel TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1640,8 +1638,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Starts the TIM Input Capture measurement in interrupt mode.
- * @param htim: TIM Input Capture handle
- * @param Channel: TIM Channels to be enabled
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1699,8 +1697,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel
/**
* @brief Stops the TIM Input Capture measurement in interrupt mode.
- * @param htim: TIM handle
- * @param Channel: TIM Channels to be disabled
+ * @param htim TIM handle
+ * @param Channel TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1759,15 +1757,15 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Starts the TIM Input Capture measurement in DMA mode.
- * @param htim: TIM Input Capture handle
- * @param Channel: TIM Channels to be enabled
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData: The destination Buffer address.
- * @param Length: The length of data to be transferred from TIM peripheral to memory.
+ * @param pData The destination Buffer address.
+ * @param Length The length of data to be transferred from TIM peripheral to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
@@ -1874,8 +1872,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
/**
* @brief Stops the TIM Input Capture measurement in DMA mode.
- * @param htim: TIM Input Capture handle
- * @param Channel: TIM Channels to be disabled
+ * @param htim TIM Input Capture handle
+ * @param Channel TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1963,8 +1961,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Initializes the TIM One Pulse Time Base according to the specified
* parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim: TIM OnePulse handle
- * @param OnePulseMode: Select the One pulse mode.
+ * @param htim TIM OnePulse handle
+ * @param OnePulseMode Select the One pulse mode.
* This parameter can be one of the following values:
* @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
* @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
@@ -2014,7 +2012,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul
/**
* @brief DeInitializes the TIM One Pulse
- * @param htim: TIM One Pulse handle
+ * @param htim TIM One Pulse handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
@@ -2041,7 +2039,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
/**
* @brief Initializes the TIM One Pulse MSP.
- * @param htim: TIM handle
+ * @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
@@ -2056,7 +2054,7 @@ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
/**
* @brief DeInitializes TIM One Pulse MSP.
- * @param htim: TIM handle
+ * @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
@@ -2071,8 +2069,8 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
/**
* @brief Starts the TIM One Pulse signal generation.
- * @param htim: TIM One Pulse handle
- * @param OutputChannel: TIM Channels to be enabled
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2104,8 +2102,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu
/**
* @brief Stops the TIM One Pulse signal generation.
- * @param htim: TIM One Pulse handle
- * @param OutputChannel: TIM Channels to be disable
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channels to be disable
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2137,8 +2135,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output
/**
* @brief Starts the TIM One Pulse signal generation in interrupt mode.
- * @param htim: TIM One Pulse handle
- * @param OutputChannel: TIM Channels to be enabled
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2176,8 +2174,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou
/**
* @brief Stops the TIM One Pulse signal generation in interrupt mode.
- * @param htim: TIM One Pulse handle
- * @param OutputChannel: TIM Channels to be enabled
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2239,8 +2237,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out
*/
/**
* @brief Initializes the TIM Encoder Interface and create the associated handle.
- * @param htim: TIM Encoder Interface handle
- * @param sConfig: TIM Encoder Interface configuration structure
+ * @param htim TIM Encoder Interface handle
+ * @param sConfig TIM Encoder Interface configuration structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
@@ -2333,7 +2331,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini
/**
* @brief DeInitializes the TIM Encoder interface
- * @param htim: TIM Encoder handle
+ * @param htim TIM Encoder handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
@@ -2360,7 +2358,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
/**
* @brief Initializes the TIM Encoder Interface MSP.
- * @param htim: TIM handle
+ * @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
@@ -2375,7 +2373,7 @@ __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
/**
* @brief DeInitializes TIM Encoder Interface MSP.
- * @param htim: TIM handle
+ * @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
@@ -2390,8 +2388,8 @@ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
/**
* @brief Starts the TIM Encoder Interface.
- * @param htim: TIM Encoder Interface handle
- * @param Channel: TIM Channels to be enabled
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2432,8 +2430,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe
/**
* @brief Stops the TIM Encoder Interface.
- * @param htim: TIM Encoder Interface handle
- * @param Channel: TIM Channels to be disabled
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2476,8 +2474,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel
/**
* @brief Starts the TIM Encoder Interface in interrupt mode.
- * @param htim: TIM Encoder Interface handle
- * @param Channel: TIM Channels to be enabled
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2524,8 +2522,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha
/**
* @brief Stops the TIM Encoder Interface in interrupt mode.
- * @param htim: TIM Encoder Interface handle
- * @param Channel: TIM Channels to be disabled
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2575,15 +2573,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan
/**
* @brief Starts the TIM Encoder Interface in DMA mode.
- * @param htim: TIM Encoder Interface handle
- * @param Channel: TIM Channels to be enabled
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @param pData1: The destination Buffer address for IC1.
* @param pData2: The destination Buffer address for IC2.
- * @param Length: The length of data to be transferred from TIM peripheral to memory.
+ * @param Length The length of data to be transferred from TIM peripheral to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
@@ -2695,8 +2693,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
/**
* @brief Stops the TIM Encoder Interface in DMA mode.
- * @param htim: TIM Encoder Interface handle
- * @param Channel: TIM Channels to be enabled
+ * @param htim TIM Encoder Interface handle
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2762,7 +2760,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
*/
/**
* @brief This function handles TIM interrupts requests.
- * @param htim: TIM handle
+ * @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
@@ -2773,7 +2771,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
{
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
/* Input capture event */
@@ -2796,7 +2794,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
/* Input capture event */
if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
@@ -2817,7 +2815,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
/* Input capture event */
if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
@@ -2838,7 +2836,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
/* Input capture event */
if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
@@ -2859,7 +2857,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
HAL_TIM_PeriodElapsedCallback(htim);
}
}
@@ -2868,16 +2866,29 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK);
HAL_TIMEx_BreakCallback(htim);
}
}
+
+#if defined(TIM_FLAG_BREAK2)
+ /* TIM Break input 2 event */
+ if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
+ {
+ if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
+ {
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
+ HAL_TIMEx_Break2Callback(htim);
+ }
+ }
+#endif
+
/* TIM Trigger detection event */
if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
{
if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
HAL_TIM_TriggerCallback(htim);
}
}
@@ -2886,7 +2897,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
{
- __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
HAL_TIMEx_CommutationCallback(htim);
}
}
@@ -2918,9 +2929,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
/**
* @brief Initializes the TIM Output Compare Channels according to the specified
* parameters in the TIM_OC_InitTypeDef.
- * @param htim: TIM Output Compare handle
- * @param sConfig: TIM Output Compare configuration structure
- * @param Channel: TIM Channels to be enabled
+ * @param htim TIM Output Compare handle
+ * @param sConfig TIM Output Compare configuration structure
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2987,9 +2998,9 @@ __weak HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
/**
* @brief Initializes the TIM Input Capture Channels according to the specified
* parameters in the TIM_IC_InitTypeDef.
- * @param htim: TIM IC handle
- * @param sConfig: TIM Input Capture configuration structure
- * @param Channel: TIM Channels to be enabled
+ * @param htim TIM IC handle
+ * @param sConfig TIM Input Capture configuration structure
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -3083,9 +3094,9 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT
/**
* @brief Initializes the TIM PWM channels according to the specified
* parameters in the TIM_OC_InitTypeDef.
- * @param htim: TIM handle
- * @param sConfig: TIM PWM configuration structure
- * @param Channel: TIM Channels to be enabled
+ * @param htim TIM handle
+ * @param sConfig TIM PWM configuration structure
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -3181,13 +3192,13 @@ __weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_
/**
* @brief Initializes the TIM One Pulse Channels according to the specified
* parameters in the TIM_OnePulse_InitTypeDef.
- * @param htim: TIM One Pulse handle
- * @param sConfig: TIM One Pulse configuration structure
- * @param OutputChannel: TIM Channels to be enabled
+ * @param htim TIM One Pulse handle
+ * @param sConfig TIM One Pulse configuration structure
+ * @param OutputChannel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @param InputChannel: TIM Channels to be enabled
+ * @param InputChannel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -3293,8 +3304,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
/**
* @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
- * @param htim: TIM handle
- * @param BurstBaseAddress: TIM Base address from where the DMA will start the Data write
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
* This parameter can be one of the following values:
* @arg TIM_DMABASE_CR1
* @arg TIM_DMABASE_CR2
@@ -3315,7 +3326,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
* @arg TIM_DMABASE_CCR4
* @arg TIM_DMABASE_BDTR
* @arg TIM_DMABASE_DCR
- * @param BurstRequestSrc: TIM DMA Request sources
+ * @param BurstRequestSrc TIM DMA Request sources
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
@@ -3324,20 +3335,67 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
* @arg TIM_DMA_COM: TIM Commutation DMA source
* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
- * @param BurstBuffer: The Buffer address.
- * @param BurstLength: DMA Burst length. This parameter can be one value
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
* between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
- uint32_t* BurstBuffer, uint32_t BurstLength)
+ uint32_t *BurstBuffer, uint32_t BurstLength)
+{
+return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U);
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_DCR
+ * @param BurstRequestSrc TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * @param DataLength Data length. This parameter can be one value
+ * between 1 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
+ uint32_t* BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
{
/* Check the parameters */
assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
-
+ assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+
if((htim->State == HAL_TIM_STATE_BUSY))
{
return HAL_BUSY;
@@ -3364,7 +3422,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
}
break;
case TIM_DMA_CC1:
@@ -3376,7 +3434,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
}
break;
case TIM_DMA_CC2:
@@ -3388,7 +3446,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
}
break;
case TIM_DMA_CC3:
@@ -3400,7 +3458,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
}
break;
case TIM_DMA_CC4:
@@ -3412,7 +3470,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
}
break;
case TIM_DMA_COM:
@@ -3424,7 +3482,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
}
break;
case TIM_DMA_TRIGGER:
@@ -3436,7 +3494,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
}
break;
default:
@@ -3456,8 +3514,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
/**
* @brief Stops the TIM DMA Burst mode
- * @param htim: TIM handle
- * @param BurstRequestSrc: TIM DMA Request sources to disable
+ * @param htim TIM handle
+ * @param BurstRequestSrc TIM DMA Request sources to disable
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
@@ -3516,8 +3574,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B
/**
* @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
- * @param htim: TIM handle
- * @param BurstBaseAddress: TIM Base address from where the DMA will starts the Data read
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will starts the Data read
* This parameter can be one of the following values:
* @arg TIM_DMABASE_CR1
* @arg TIM_DMABASE_CR2
@@ -3538,7 +3596,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B
* @arg TIM_DMABASE_CCR4
* @arg TIM_DMABASE_BDTR
* @arg TIM_DMABASE_DCR
- * @param BurstRequestSrc: TIM DMA Request sources
+ * @param BurstRequestSrc TIM DMA Request sources
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
@@ -3547,20 +3605,67 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B
* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
* @arg TIM_DMA_COM: TIM Commutation DMA source
* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
- * @param BurstBuffer: The Buffer address.
- * @param BurstLength: DMA Burst length. This parameter can be one value
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
* between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
uint32_t *BurstBuffer, uint32_t BurstLength)
+{
+return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U);
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer multiple Data from the TIM peripheral to the memory
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will starts the Data read
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_DCR
+ * @param BurstRequestSrc TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * @param DataLength Data length. This parameter can be one value
+ * between 1 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
+ uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
{
/* Check the parameters */
assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
-
+ assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
+
if((htim->State == HAL_TIM_STATE_BUSY))
{
return HAL_BUSY;
@@ -3587,7 +3692,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
}
break;
case TIM_DMA_CC1:
@@ -3599,7 +3704,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
}
break;
case TIM_DMA_CC2:
@@ -3611,7 +3716,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
}
break;
case TIM_DMA_CC3:
@@ -3623,7 +3728,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
}
break;
case TIM_DMA_CC4:
@@ -3635,7 +3740,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
}
break;
case TIM_DMA_COM:
@@ -3647,7 +3752,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
}
break;
case TIM_DMA_TRIGGER:
@@ -3659,7 +3764,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
}
break;
default:
@@ -3680,8 +3785,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
/**
* @brief Stop the DMA burst reading
- * @param htim: TIM handle
- * @param BurstRequestSrc: TIM DMA Request sources to disable.
+ * @param htim TIM handle
+ * @param BurstRequestSrc TIM DMA Request sources to disable.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
@@ -3740,8 +3845,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu
/**
* @brief Generate a software event
- * @param htim: TIM handle
- * @param EventSource: specifies the event source.
+ * @param htim TIM handle
+ * @param EventSource specifies the event source.
* This parameter can be one of the following values:
* @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
* @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
@@ -3783,10 +3888,10 @@ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventS
/**
* @brief Configures the OCRef clear feature
- * @param htim: TIM handle
- * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
+ * @param htim TIM handle
+ * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
* contains the OCREF clear feature and parameters for the TIM peripheral.
- * @param Channel: specifies the TIM Channel
+ * @param Channel specifies the TIM Channel
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1
* @arg TIM_CHANNEL_2: TIM Channel 2
@@ -3893,8 +3998,8 @@ __weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_C
/**
* @brief Configures the clock source to be used
- * @param htim: TIM handle
- * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
+ * @param htim TIM handle
+ * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
@@ -4063,7 +4168,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo
/**
* @brief Selects the signal connected to the TI1 input: direct from CH1_input
* or a XOR combination between CH1_input, CH2_input & CH3_input
- * @param htim: TIM handle.
+ * @param htim TIM handle.
* @param TI1_Selection: Indicate whether or not channel 1 is connected to the
* output of a XOR gate.
* This parameter can be one of the following values:
@@ -4097,8 +4202,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S
/**
* @brief Configures the TIM in Slave mode
- * @param htim: TIM handle.
- * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
+ * @param htim TIM handle.
+ * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
* contains the selected trigger (internal trigger input, filtered
* timer input or external trigger input) and the ) and the Slave
* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
@@ -4132,8 +4237,8 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TI
/**
* @brief Configures the TIM in Slave mode in interrupt mode
- * @param htim: TIM handle.
- * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
+ * @param htim TIM handle.
+ * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
* contains the selected trigger (internal trigger input, filtered
* timer input or external trigger input) and the ) and the Slave
* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
@@ -4168,8 +4273,8 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
/**
* @brief Read the captured value from Capture Compare unit
- * @param htim: TIM handle.
- * @param Channel: TIM Channels to be enabled
+ * @param htim TIM handle.
+ * @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -4261,7 +4366,7 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Period elapsed callback in non blocking mode
- * @param htim: TIM handle
+ * @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
@@ -4276,7 +4381,7 @@ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
}
/**
* @brief Output Compare callback in non blocking mode
- * @param htim: TIM OC handle
+ * @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
@@ -4290,7 +4395,7 @@ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
}
/**
* @brief Input Capture callback in non blocking mode
- * @param htim: TIM IC handle
+ * @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
@@ -4305,7 +4410,7 @@ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
/**
* @brief PWM Pulse finished callback in non blocking mode
- * @param htim: TIM handle
+ * @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
@@ -4320,7 +4425,7 @@ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
/**
* @brief Hall Trigger detection callback in non blocking mode
- * @param htim: TIM handle
+ * @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
@@ -4335,7 +4440,7 @@ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
/**
* @brief Timer error callback in non blocking mode
- * @param htim: TIM handle
+ * @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
@@ -4369,7 +4474,7 @@ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
/**
* @brief Return the TIM Base state
- * @param htim: TIM Base handle
+ * @param htim TIM Base handle
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
@@ -4379,7 +4484,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
/**
* @brief Return the TIM OC state
- * @param htim: TIM Ouput Compare handle
+ * @param htim TIM Ouput Compare handle
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
@@ -4389,7 +4494,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
/**
* @brief Return the TIM PWM state
- * @param htim: TIM handle
+ * @param htim TIM handle
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
@@ -4399,7 +4504,7 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
/**
* @brief Return the TIM Input Capture state
- * @param htim: TIM IC handle
+ * @param htim TIM IC handle
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
@@ -4409,7 +4514,7 @@ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
/**
* @brief Return the TIM One Pulse Mode state
- * @param htim: TIM OPM handle
+ * @param htim TIM OPM handle
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
@@ -4419,7 +4524,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
/**
* @brief Return the TIM Encoder Mode state
- * @param htim: TIM Encoder handle
+ * @param htim TIM Encoder handle
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
@@ -4441,7 +4546,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
/**
* @brief TIM DMA error callback
- * @param hdma : pointer to DMA handle.
+ * @param hdma pointer to DMA handle.
* @retval None
*/
void TIM_DMAError(DMA_HandleTypeDef *hdma)
@@ -4455,7 +4560,7 @@ void TIM_DMAError(DMA_HandleTypeDef *hdma)
/**
* @brief TIM DMA Delay Pulse complete callback.
- * @param hdma : pointer to DMA handle.
+ * @param hdma pointer to DMA handle.
* @retval None
*/
void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
@@ -4487,7 +4592,7 @@ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
}
/**
* @brief TIM DMA Capture complete callback.
- * @param hdma : pointer to DMA handle.
+ * @param hdma pointer to DMA handle.
* @retval None
*/
void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
@@ -4520,7 +4625,7 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
/**
* @brief TIM DMA Period Elapse complete callback.
- * @param hdma : pointer to DMA handle.
+ * @param hdma pointer to DMA handle.
* @retval None
*/
static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
@@ -4534,7 +4639,7 @@ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
/**
* @brief TIM DMA Trigger callback.
- * @param hdma : pointer to DMA handle.
+ * @param hdma pointer to DMA handle.
* @retval None
*/
static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
@@ -4548,8 +4653,8 @@ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
/**
* @brief Time Base configuration
- * @param TIMx: TIM periheral
- * @param Structure: TIM Base configuration structure
+ * @param TIMx TIM periheral
+ * @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
@@ -4597,7 +4702,7 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
/**
* @brief Time Ouput Compare 1 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config: The ouput configuration structure
+ * @param OC_Config The ouput configuration structure
* @retval None
*/
void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -4671,7 +4776,7 @@ void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
/**
* @brief Time Ouput Compare 2 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config: The ouput configuration structure
+ * @param OC_Config The ouput configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -4751,7 +4856,7 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
/**
* @brief Time Ouput Compare 3 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config: The ouput configuration structure
+ * @param OC_Config The ouput configuration structure
* @retval None
*/
void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -4828,7 +4933,7 @@ void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
/**
* @brief Time Ouput Compare 4 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config: The ouput configuration structure
+ * @param OC_Config The ouput configuration structure
* @retval None
*/
void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -5013,17 +5118,17 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
/**
* @brief Configure the TI1 as Input.
* @param TIMx to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
+ * @param TIM_ICPolarity The Input Polarity.
* This parameter can be one of the following values:
* @arg TIM_ICPOLARITY_RISING
* @arg TIM_ICPOLARITY_FALLING
* @arg TIM_ICPOLARITY_BOTHEDGE
- * @param TIM_ICSelection: specifies the input to be used.
+ * @param TIM_ICSelection specifies the input to be used.
* This parameter can be one of the following values:
* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
* @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
@@ -5068,12 +5173,12 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_
/**
* @brief Configure the Polarity and Filter for TI1.
* @param TIMx to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
+ * @param TIM_ICPolarity The Input Polarity.
* This parameter can be one of the following values:
* @arg TIM_ICPOLARITY_RISING
* @arg TIM_ICPOLARITY_FALLING
* @arg TIM_ICPOLARITY_BOTHEDGE
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
@@ -5103,17 +5208,17 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
/**
* @brief Configure the TI2 as Input.
* @param TIMx to select the TIM peripheral
- * @param TIM_ICPolarity : The Input Polarity.
+ * @param TIM_ICPolarity The Input Polarity.
* This parameter can be one of the following values:
* @arg TIM_ICPOLARITY_RISING
* @arg TIM_ICPOLARITY_FALLING
* @arg TIM_ICPOLARITY_BOTHEDGE
- * @param TIM_ICSelection: specifies the input to be used.
+ * @param TIM_ICSelection specifies the input to be used.
* This parameter can be one of the following values:
* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
* @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
@@ -5151,12 +5256,12 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
/**
* @brief Configure the Polarity and Filter for TI2.
* @param TIMx to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
+ * @param TIM_ICPolarity The Input Polarity.
* This parameter can be one of the following values:
* @arg TIM_ICPOLARITY_RISING
* @arg TIM_ICPOLARITY_FALLING
* @arg TIM_ICPOLARITY_BOTHEDGE
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
@@ -5186,17 +5291,17 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
/**
* @brief Configure the TI3 as Input.
* @param TIMx to select the TIM peripheral
- * @param TIM_ICPolarity : The Input Polarity.
+ * @param TIM_ICPolarity The Input Polarity.
* This parameter can be one of the following values:
* @arg TIM_ICPOLARITY_RISING
* @arg TIM_ICPOLARITY_FALLING
* @arg TIM_ICPOLARITY_BOTHEDGE
- * @param TIM_ICSelection: specifies the input to be used.
+ * @param TIM_ICSelection specifies the input to be used.
* This parameter can be one of the following values:
* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
* @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
@@ -5234,17 +5339,17 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
/**
* @brief Configure the TI4 as Input.
* @param TIMx to select the TIM peripheral
- * @param TIM_ICPolarity : The Input Polarity.
+ * @param TIM_ICPolarity The Input Polarity.
* This parameter can be one of the following values:
* @arg TIM_ICPOLARITY_RISING
* @arg TIM_ICPOLARITY_FALLING
* @arg TIM_ICPOLARITY_BOTHEDGE
- * @param TIM_ICSelection: specifies the input to be used.
+ * @param TIM_ICSelection specifies the input to be used.
* This parameter can be one of the following values:
* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
* @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
* @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
@@ -5282,7 +5387,7 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
/**
* @brief Selects the Input Trigger source
* @param TIMx to select the TIM peripheral
- * @param InputTriggerSource: The Input Trigger source.
+ * @param InputTriggerSource The Input Trigger source.
* This parameter can be one of the following values:
* @arg TIM_TS_ITR0: Internal Trigger 0
* @arg TIM_TS_ITR1: Internal Trigger 1
@@ -5310,17 +5415,17 @@ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
/**
* @brief Configures the TIMx External Trigger (ETR).
* @param TIMx to select the TIM peripheral
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+ * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
* This parameter can be one of the following values:
* @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
* @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
* @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
* @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
+ * @param TIM_ExtTRGPolarity The external Trigger Polarity.
* This parameter can be one of the following values:
* @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
* @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
- * @param ExtTRGFilter: External Trigger Filter.
+ * @param ExtTRGFilter External Trigger Filter.
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
@@ -5344,13 +5449,13 @@ void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
/**
* @brief Enables or disables the TIM Capture Compare Channel x.
* @param TIMx to select the TIM peripheral
- * @param Channel: specifies the TIM Channel
+ * @param Channel specifies the TIM Channel
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1
* @arg TIM_CHANNEL_2: TIM Channel 2
* @arg TIM_CHANNEL_3: TIM Channel 3
* @arg TIM_CHANNEL_4: TIM Channel 4
- * @param ChannelState: specifies the TIM Channel CCxE bit new state.
+ * @param ChannelState specifies the TIM Channel CCxE bit new state.
* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
* @retval None
*/
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c
index 6e7abbb8fd..cbdfce1745 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_tim_ex.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer Extended peripheral:
@@ -182,8 +180,8 @@ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
*/
/**
* @brief Initializes the TIM Hall Sensor Interface and create the associated handle.
- * @param htim: TIM Encoder Interface handle
- * @param sConfig: TIM Hall Sensor configuration structure
+ * @param htim TIM Encoder Interface handle
+ * @param sConfig TIM Hall Sensor configuration structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
@@ -262,7 +260,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen
/**
* @brief DeInitializes the TIM Hall Sensor interface
- * @param htim: TIM Hall Sensor handle
+ * @param htim TIM Hall Sensor handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
@@ -289,7 +287,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
/**
* @brief Initializes the TIM Hall Sensor MSP.
- * @param htim: TIM handle
+ * @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
@@ -304,7 +302,7 @@ __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
/**
* @brief DeInitializes TIM Hall Sensor MSP.
- * @param htim: TIM handle
+ * @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
@@ -319,7 +317,7 @@ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
/**
* @brief Starts the TIM Hall Sensor Interface.
- * @param htim: TIM Hall Sensor handle
+ * @param htim TIM Hall Sensor handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
@@ -340,7 +338,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
/**
* @brief Stops the TIM Hall sensor Interface.
- * @param htim: TIM Hall Sensor handle
+ * @param htim TIM Hall Sensor handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
@@ -361,7 +359,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
/**
* @brief Starts the TIM Hall Sensor Interface in interrupt mode.
- * @param htim: TIM Hall Sensor handle
+ * @param htim TIM Hall Sensor handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
@@ -385,7 +383,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
/**
* @brief Stops the TIM Hall Sensor Interface in interrupt mode.
- * @param htim: TIM handle
+ * @param htim TIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
@@ -409,9 +407,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
/**
* @brief Starts the TIM Hall Sensor Interface in DMA mode.
- * @param htim: TIM Hall Sensor handle
- * @param pData: The destination Buffer address.
- * @param Length: The length of data to be transferred from TIM peripheral to memory.
+ * @param htim TIM Hall Sensor handle
+ * @param pData The destination Buffer address.
+ * @param Length The length of data to be transferred from TIM peripheral to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
@@ -458,7 +456,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32
/**
* @brief Stops the TIM Hall Sensor Interface in DMA mode.
- * @param htim: TIM handle
+ * @param htim TIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
@@ -508,8 +506,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
/**
* @brief Starts the TIM Output Compare signal generation on the complementary
* output.
- * @param htim: TIM Output Compare handle
- * @param Channel: TIM Channel to be enabled
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -538,8 +536,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Stops the TIM Output Compare signal generation on the complementary
* output.
- * @param htim: TIM handle
- * @param Channel: TIM Channel to be disabled
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -568,8 +566,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Starts the TIM Output Compare signal generation in interrupt mode
* on the complementary output.
- * @param htim: TIM OC handle
- * @param Channel: TIM Channel to be enabled
+ * @param htim TIM OC handle
+ * @param Channel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -635,8 +633,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann
/**
* @brief Stops the TIM Output Compare signal generation in interrupt mode
* on the complementary output.
- * @param htim: TIM Output Compare handle
- * @param Channel: TIM Channel to be disabled
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -708,15 +706,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
/**
* @brief Starts the TIM Output Compare signal generation in DMA mode
* on the complementary output.
- * @param htim: TIM Output Compare handle
- * @param Channel: TIM Channel to be enabled
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData: The source Buffer address.
- * @param Length: The length of data to be transferred from memory to TIM peripheral
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
@@ -825,8 +823,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
/**
* @brief Stops the TIM Output Compare signal generation in DMA mode
* on the complementary output.
- * @param htim: TIM Output Compare handle
- * @param Channel: TIM Channel to be disabled
+ * @param htim TIM Output Compare handle
+ * @param Channel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -925,8 +923,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
/**
* @brief Starts the PWM signal generation on the complementary output.
- * @param htim: TIM handle
- * @param Channel: TIM Channel to be enabled
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -954,8 +952,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel
/**
* @brief Stops the PWM signal generation on the complementary output.
- * @param htim: TIM handle
- * @param Channel: TIM Channel to be disabled
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -984,8 +982,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
/**
* @brief Starts the PWM signal generation in interrupt mode on the
* complementary output.
- * @param htim: TIM handle
- * @param Channel: TIM Channel to be disabled
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1051,8 +1049,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan
/**
* @brief Stops the PWM signal generation in interrupt mode on the
* complementary output.
- * @param htim: TIM handle
- * @param Channel: TIM Channel to be disabled
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1124,15 +1122,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Chan
/**
* @brief Starts the TIM PWM signal generation in DMA mode on the
* complementary output
- * @param htim: TIM handle
- * @param Channel: TIM Channel to be enabled
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData: The source Buffer address.
- * @param Length: The length of data to be transferred from memory to TIM peripheral
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
@@ -1241,8 +1239,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
/**
* @brief Stops the TIM PWM signal generation in DMA mode on the complementary
* output
- * @param htim: TIM handle
- * @param Channel: TIM Channel to be disabled
+ * @param htim TIM handle
+ * @param Channel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1330,8 +1328,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
/**
* @brief Starts the TIM One Pulse signal generation on the complemetary
* output.
- * @param htim: TIM One Pulse handle
- * @param OutputChannel: TIM Channel to be enabled
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1355,8 +1353,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou
/**
* @brief Stops the TIM One Pulse signal generation on the complementary
* output.
- * @param htim: TIM One Pulse handle
- * @param OutputChannel: TIM Channel to be disabled
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1384,8 +1382,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out
/**
* @brief Starts the TIM One Pulse signal generation in interrupt mode on the
* complementary channel.
- * @param htim: TIM One Pulse handle
- * @param OutputChannel: TIM Channel to be enabled
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1415,8 +1413,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t
/**
* @brief Stops the TIM One Pulse signal generation in interrupt mode on the
* complementary channel.
- * @param htim: TIM One Pulse handle
- * @param OutputChannel: TIM Channel to be disabled
+ * @param htim TIM One Pulse handle
+ * @param OutputChannel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1481,15 +1479,15 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
* configured in Hall sensor interface, this interface Timer will generate the
* commutation at its TRGO output (connected to Timer used in this function) each time
* the TI1 of the Interface Timer detect a commutation at its input TI1.
- * @param htim: TIM handle
- * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+ * @param htim TIM handle
+ * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
* This parameter can be one of the following values:
* @arg TIM_TS_ITR0: Internal trigger 0 selected
* @arg TIM_TS_ITR1: Internal trigger 1 selected
* @arg TIM_TS_ITR2: Internal trigger 2 selected
* @arg TIM_TS_ITR3: Internal trigger 3 selected
* @arg TIM_TS_NONE: No trigger is needed
- * @param CommutationSource: the Commutation Event source
+ * @param CommutationSource the Commutation Event source
* This parameter can be one of the following values:
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
@@ -1530,15 +1528,15 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint
* configured in Hall sensor interface, this interface Timer will generate the
* commutation at its TRGO output (connected to Timer used in this function) each time
* the TI1 of the Interface Timer detect a commutation at its input TI1.
- * @param htim: TIM handle
- * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+ * @param htim TIM handle
+ * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
* This parameter can be one of the following values:
* @arg TIM_TS_ITR0: Internal trigger 0 selected
* @arg TIM_TS_ITR1: Internal trigger 1 selected
* @arg TIM_TS_ITR2: Internal trigger 2 selected
* @arg TIM_TS_ITR3: Internal trigger 3 selected
* @arg TIM_TS_NONE: No trigger is needed
- * @param CommutationSource: the Commutation Event source
+ * @param CommutationSource the Commutation Event source
* This parameter can be one of the following values:
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
@@ -1583,15 +1581,15 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, u
* commutation at its TRGO output (connected to Timer used in this function) each time
* the TI1 of the Interface Timer detect a commutation at its input TI1.
* @note The user should configure the DMA in his own software, in This function only the COMDE bit is set
- * @param htim: TIM handle
- * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
+ * @param htim TIM handle
+ * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
* This parameter can be one of the following values:
* @arg TIM_TS_ITR0: Internal trigger 0 selected
* @arg TIM_TS_ITR1: Internal trigger 1 selected
* @arg TIM_TS_ITR2: Internal trigger 2 selected
* @arg TIM_TS_ITR3: Internal trigger 3 selected
* @arg TIM_TS_NONE: No trigger is needed
- * @param CommutationSource: the Commutation Event source
+ * @param CommutationSource the Commutation Event source
* This parameter can be one of the following values:
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
@@ -1636,9 +1634,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim,
/**
* @brief Initializes the TIM Output Compare Channels according to the specified
* parameters in the TIM_OC_InitTypeDef.
- * @param htim: TIM Output Compare handle
- * @param sConfig: TIM Output Compare configuration structure
- * @param Channel: TIM Channels to configure
+ * @param htim TIM Output Compare handle
+ * @param sConfig TIM Output Compare configuration structure
+ * @param Channel TIM Channels to configure
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1740,9 +1738,9 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
/**
* @brief Initializes the TIM PWM channels according to the specified
* parameters in the TIM_OC_InitTypeDef.
- * @param htim: TIM PWM handle
- * @param sConfig: TIM PWM configuration structure
- * @param Channel: TIM Channels to be configured
+ * @param htim TIM PWM handle
+ * @param sConfig TIM PWM configuration structure
+ * @param Channel TIM Channels to be configured
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1887,8 +1885,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
/**
* @brief Configures the TIM in master mode.
- * @param htim: TIM handle.
- * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
+ * @param htim TIM handle.
+ * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
* contains the selected trigger output (TRGO) and the Master/Slave
* mode.
* @retval HAL status
@@ -1953,8 +1951,8 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
#if defined(STM32F373xC) || defined(STM32F378xx)
/**
* @brief Configures the TIM in master mode.
- * @param htim: TIM handle.
- * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
+ * @param htim TIM handle.
+ * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
* contains the selected trigger output (TRGO) and the Master/Slave
* mode.
* @retval HAL status
@@ -1995,8 +1993,8 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
/**
* @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
* and the AOE(automatic output enable).
- * @param htim: TIM handle
- * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfigTypeDef
+ * @param htim TIM handle
+ * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef
structure that contains the BDTR Register configuration information
for the TIM peripheral.
* @note For STM32F302xC, STM32F302xE, STM32F303xC, STM32F358xx, STM32F303xE,
@@ -2064,8 +2062,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
/**
* @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
* and the AOE(automatic output enable).
- * @param htim: TIM handle
- * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
+ * @param htim TIM handle
+ * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
* contains the BDTR Register configuration information for the TIM peripheral.
* @retval HAL status
*/
@@ -2119,7 +2117,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
#if defined(STM32F303xE) || defined(STM32F398xx)
/**
* @brief Configures the TIM1, TIM8, TIM16 and TIM20 Remapping input capabilities.
- * @param htim: TIM handle.
+ * @param htim TIM handle.
* @param Remap1: specifies the first TIM remapping source.
* This parameter can be one of the following values:
* @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)
@@ -2158,7 +2156,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
#elif defined(STM32F303xC) || defined(STM32F358xx)
/**
* @brief Configures the TIM1, TIM8 and TIM16 Remapping input capabilities.
- * @param htim: TIM handle.
+ * @param htim TIM handle.
* @param Remap1: specifies the first TIM remapping source.
* This parameter can be one of the following values:
* @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
@@ -2188,7 +2186,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
#else /* STM32F334x8 */
/**
* @brief Configures the TIM1, TIM8 and TIM16 Remapping input capabilities.
- * @param htim: TIM handle.
+ * @param htim TIM handle.
* @param Remap1: specifies the first TIM remapping source.
* This parameter can be one of the following values:
* @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
@@ -2241,8 +2239,8 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap1
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
/**
* @brief Configures the TIM1 and TIM16 Remapping input capabilities.
- * @param htim: TIM handle.
- * @param Remap: specifies the TIM remapping source.
+ * @param htim TIM handle.
+ * @param Remap specifies the TIM remapping source.
* This parameter can be one of the following values:
* @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
* @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
@@ -2257,8 +2255,8 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap1
#else /* STM32F373xC || STM32F378xx */
/**
* @brief Configures the TIM2 and TIM14 Remapping input capabilities.
- * @param htim: TIM handle.
- * @param Remap: specifies the TIM remapping source.
+ * @param htim TIM handle.
+ * @param Remap specifies the TIM remapping source.
* This parameter can be one of the following values:
* STM32F373xC, STM32F378xx:
* @arg TIM_TIM2_TIM8_TRGO: TIM8 TRGOUT is connected to TIM2_ITR1
@@ -2305,8 +2303,8 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
/**
* @brief Group channel 5 and channel 1, 2 or 3
- * @param htim: TIM handle.
- * @param Channels: specifies the reference signal(s) the OC5REF is combined with.
+ * @param htim TIM handle.
+ * @param Channels specifies the reference signal(s) the OC5REF is combined with.
* This parameter can be any combination of the following values:
* TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
* TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
@@ -2355,10 +2353,10 @@ HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Chan
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
/**
* @brief Configures the OCRef clear feature
- * @param htim: TIM handle
- * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
+ * @param htim TIM handle
+ * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
* contains the OCREF clear feature and parameters for the TIM peripheral.
- * @param Channel: specifies the TIM Channel
+ * @param Channel specifies the TIM Channel
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1
* @arg TIM_CHANNEL_2: TIM Channel 2
@@ -2552,7 +2550,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
/**
* @brief Hall commutation changed callback in non blocking mode
- * @param htim: TIM handle
+ * @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
@@ -2567,7 +2565,7 @@ __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
/**
* @brief Hall Break detection callback in non blocking mode
- * @param htim: TIM handle
+ * @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
@@ -2580,6 +2578,21 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
*/
}
+/**
+ * @brief Hall Break2 detection callback in non blocking mode
+ * @param htim: TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_TIMEx_Break2Callback could be implemented in the user file
+ */
+}
+
/**
* @}
*/
@@ -2601,7 +2614,7 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
/**
* @brief Return the TIM Hall Sensor interface state
- * @param htim: TIM Hall Sensor handle
+ * @param htim TIM Hall Sensor handle
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
@@ -2622,7 +2635,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
*/
/**
* @brief TIM DMA Commutation callback.
- * @param hdma : pointer to DMA handle.
+ * @param hdma pointer to DMA handle.
* @retval None
*/
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
@@ -2637,12 +2650,12 @@ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
/**
* @brief Enables or disables the TIM Capture Compare Channel xN.
* @param TIMx to select the TIM peripheral
- * @param Channel: specifies the TIM Channel
+ * @param Channel specifies the TIM Channel
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1
* @arg TIM_CHANNEL_2: TIM Channel 2
* @arg TIM_CHANNEL_3: TIM Channel 3
- * @param ChannelNState: specifies the TIM Channel CCxNE bit new state.
+ * @param ChannelNState specifies the TIM Channel CCxNE bit new state.
* This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
* @retval None
*/
@@ -2666,7 +2679,7 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t Cha
/**
* @brief Timer Ouput Compare 5 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config: The ouput configuration structure
+ * @param OC_Config The ouput configuration structure
* @retval None
*/
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
@@ -2719,7 +2732,7 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
/**
* @brief Timer Ouput Compare 6 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config: The ouput configuration structure
+ * @param OC_Config The ouput configuration structure
* @retval None
*/
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_timebase_rtc_alarm_template.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_timebase_rtc_alarm_template.c
index b82461d4ad..dfd4072b3b 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_timebase_rtc_alarm_template.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_timebase_rtc_alarm_template.c
@@ -1,8 +1,6 @@
/**
******************************************************************************
* @file stm32f3xx_hal_timebase_rtc_alarm_template.c
- * @version V1.4.0
- * @date 16-December-2016
* @brief HAL time base based on the hardware RTC_ALARM Template.
*
* This file override the native HAL time base functions (defined as weak)
@@ -84,12 +82,15 @@
/* #define RTC_CLOCK_SOURCE_LSE */
/* #define RTC_CLOCK_SOURCE_LSI */
-#ifdef RTC_CLOCK_SOURCE_HSE
+#if defined(RTC_CLOCK_SOURCE_HSE)
#define RTC_ASYNCH_PREDIV 49U
#define RTC_SYNCH_PREDIV 4U
-#else /* RTC_CLOCK_SOURCE_LSE || RTC_CLOCK_SOURCE_LSI */
+#elif defined(RTC_CLOCK_SOURCE_LSE)
#define RTC_ASYNCH_PREDIV 0U
#define RTC_SYNCH_PREDIV 31U
+#else /*RTC_CLOCK_SOURCE_LSI */
+ #define RTC_ASYNCH_PREDIV 0U
+ #define RTC_SYNCH_PREDIV 39U
#endif /* RTC_CLOCK_SOURCE_HSE */
/* Private macro -------------------------------------------------------------*/
@@ -105,7 +106,7 @@ void RTC_Alarm_IRQHandler(void);
* Tick interrupt priority.
* @note This function is called automatically at the beginning of program after
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
- * @param TickPriority: Tick interrupt priority.
+ * @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
@@ -153,7 +154,7 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
Time base = ((31U + 1U) * (0U + 1U)) / 32.768KHz
= ~1ms
LSI as RTC clock
- Time base = ((31U + 1U) * (0U + 1U)) / 32KHz
+ Time base = ((39U + 1U) * (0U + 1U)) / 40KHz
= 1ms
*/
hRTC_Handle.Instance = RTC;
@@ -262,7 +263,7 @@ void HAL_ResumeTick(void)
* @note This function is called when RTC_ALARM interrupt took place, inside
* RTC_Alarm_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
* a global variable "uwTick" used as application time base.
- * @param hrtc : RTC handle
+ * @param hrtc RTC handle
* @retval None
*/
void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_timebase_rtc_wakeup_template.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_timebase_rtc_wakeup_template.c
index 85cfa4ec1a..465fa6c7b0 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_timebase_rtc_wakeup_template.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_timebase_rtc_wakeup_template.c
@@ -1,8 +1,6 @@
/**
******************************************************************************
* @file stm32f3xx_hal_timebase_rtc_wakeup_template.c
- * @version V1.4.0
- * @date 16-December-2016
* @brief HAL time base based on the hardware RTC_WAKEUP Template.
*
* This file overrides the native HAL time base functions (defined as weak)
@@ -85,12 +83,15 @@
/* #define RTC_CLOCK_SOURCE_LSE */
/* #define RTC_CLOCK_SOURCE_LSI */
-#ifdef RTC_CLOCK_SOURCE_HSE
+#if defined(RTC_CLOCK_SOURCE_HSE)
#define RTC_ASYNCH_PREDIV 49U
#define RTC_SYNCH_PREDIV 4U
-#else /* RTC_CLOCK_SOURCE_LSE || RTC_CLOCK_SOURCE_LSI */
+#elif define(RTC_CLOCK_SOURCE_LSE)
#define RTC_ASYNCH_PREDIV 0U
#define RTC_SYNCH_PREDIV 31U
+#else /* RTC_CLOCK_SOURCE_LSI */
+ #define RTC_ASYNCH_PREDIV 0U
+ #define RTC_SYNCH_PREDIV 39U
#endif /* RTC_CLOCK_SOURCE_HSE */
/* Private macro -------------------------------------------------------------*/
@@ -112,7 +113,7 @@ void RTC_WKUP_IRQHandler(void);
= 1 ms
* @note This function is called automatically at the beginning of program after
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
- * @param TickPriority: Tick interrupt priority.
+ * @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
@@ -160,7 +161,7 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
Time base = ((31U + 1U) * (0U + 1U)) / 32.768Khz
= ~1ms
LSI as RTC clock
- Time base = ((31U + 1U) * (0U + 1U)) / 32Khz
+ Time base = ((39U + 1U) * (0U + 1U)) / 40Khz
= 1ms
*/
hRTC_Handle.Instance = RTC;
@@ -264,7 +265,7 @@ void HAL_ResumeTick(void)
* @note This function is called when RTC_WKUP interrupt took place, inside
* RTC_WKUP_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
* a global variable "uwTick" used as application time base.
- * @param hrtc : RTC handle
+ * @param hrtc RTC handle
* @retval None
*/
void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_timebase_tim_template.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_timebase_tim_template.c
index 27ce7a8935..fd69e91bfa 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_timebase_tim_template.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_timebase_tim_template.c
@@ -1,8 +1,6 @@
/**
******************************************************************************
* @file stm32f3xx_hal_timebase_tim_template.c
- * @version V1.4.0
- * @date 16-December-2016
* @brief HAL time base based on the hardware TIM Template.
*
* This file override the native HAL time base functions (defined as weak)
@@ -66,7 +64,7 @@ void TIM6_DAC_IRQHandler(void);
* Tick interrupt priority.
* @note This function is called automatically at the beginning of program after
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
- * @param TickPriority: Tick interrupt priority.
+ * @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
@@ -157,7 +155,7 @@ void HAL_ResumeTick(void)
* @note This function is called when TIM6 interrupt took place, inside
* HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
* a global variable "uwTick" used as application time base.
- * @param htim : TIM handle
+ * @param htim TIM handle
* @retval None
*/
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tsc.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tsc.c
index 389a2c0d64..f93bcab7ac 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tsc.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tsc.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_tsc.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Touch Sensing Controller (TSC) peripheral:
* + Initialization and De-initialization
@@ -207,7 +205,7 @@ static uint32_t TSC_extract_groups(uint32_t iomask);
/**
* @brief Initialize the TSC peripheral according to the specified parameters
* in the TSC_InitTypeDef structure and initialize the associated handle.
- * @param htsc: TSC handle
+ * @param htsc TSC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc)
@@ -295,7 +293,7 @@ HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc)
/**
* @brief Deinitialize the TSC peripheral registers to their default reset values.
- * @param htsc: TSC handle
+ * @param htsc TSC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef* htsc)
@@ -327,7 +325,7 @@ HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef* htsc)
/**
* @brief Initialize the TSC MSP.
- * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * @param htsc pointer to a TSC_HandleTypeDef structure that contains
* the configuration information for the specified TSC.
* @retval None
*/
@@ -343,7 +341,7 @@ __weak void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc)
/**
* @brief DeInitialize the TSC MSP.
- * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * @param htsc pointer to a TSC_HandleTypeDef structure that contains
* the configuration information for the specified TSC.
* @retval None
*/
@@ -382,7 +380,7 @@ __weak void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc)
/**
* @brief Start the acquisition.
- * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * @param htsc pointer to a TSC_HandleTypeDef structure that contains
* the configuration information for the specified TSC.
* @retval HAL status
*/
@@ -425,7 +423,7 @@ HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc)
/**
* @brief Start the acquisition in interrupt mode.
- * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * @param htsc pointer to a TSC_HandleTypeDef structure that contains
* the configuration information for the specified TSC.
* @retval HAL status.
*/
@@ -479,7 +477,7 @@ HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc)
/**
* @brief Stop the acquisition previously launched in polling mode.
- * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * @param htsc pointer to a TSC_HandleTypeDef structure that contains
* the configuration information for the specified TSC.
* @retval HAL status
*/
@@ -512,7 +510,7 @@ HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc)
/**
* @brief Stop the acquisition previously launched in interrupt mode.
- * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * @param htsc pointer to a TSC_HandleTypeDef structure that contains
* the configuration information for the specified TSC.
* @retval HAL status
*/
@@ -550,7 +548,7 @@ HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc)
* @brief Start acquisition and wait until completion.
* @note There is no need of a timeout parameter as the max count error is already
* managed by the TSC peripheral.
- * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * @param htsc pointer to a TSC_HandleTypeDef structure that contains
* the configuration information for the specified TSC.
* @retval HAL state
*/
@@ -576,9 +574,9 @@ HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc)
/**
* @brief Get the acquisition status for a group.
- * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * @param htsc pointer to a TSC_HandleTypeDef structure that contains
* the configuration information for the specified TSC.
- * @param gx_index: Index of the group
+ * @param gx_index Index of the group
* @retval Group status
*/
TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index)
@@ -593,9 +591,9 @@ TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t
/**
* @brief Get the acquisition measure for a group.
- * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * @param htsc pointer to a TSC_HandleTypeDef structure that contains
* the configuration information for the specified TSC.
- * @param gx_index: Index of the group
+ * @param gx_index Index of the group
* @retval Acquisition measure
*/
uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index)
@@ -628,9 +626,9 @@ uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index)
/**
* @brief Configure TSC IOs.
- * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * @param htsc pointer to a TSC_HandleTypeDef structure that contains
* the configuration information for the specified TSC.
- * @param config: pointer to the configuration structure.
+ * @param config pointer to the configuration structure.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config)
@@ -665,9 +663,9 @@ HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef*
/**
* @brief Discharge TSC IOs.
- * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * @param htsc pointer to a TSC_HandleTypeDef structure that contains
* the configuration information for the specified TSC.
- * @param choice: enable or disable
+ * @param choice enable or disable
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice)
@@ -715,7 +713,7 @@ HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice)
/**
* @brief Return the TSC handle state.
- * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * @param htsc pointer to a TSC_HandleTypeDef structure that contains
* the configuration information for the specified TSC.
* @retval HAL state
*/
@@ -757,7 +755,7 @@ HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc)
/**
* @brief Handle TSC interrupt request.
- * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * @param htsc pointer to a TSC_HandleTypeDef structure that contains
* the configuration information for the specified TSC.
* @retval None
*/
@@ -794,7 +792,7 @@ void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc)
/**
* @brief Acquisition completed callback in non-blocking mode.
- * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * @param htsc pointer to a TSC_HandleTypeDef structure that contains
* the configuration information for the specified TSC.
* @retval None
*/
@@ -810,7 +808,7 @@ __weak void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc)
/**
* @brief Error callback in non-blocking mode.
- * @param htsc: pointer to a TSC_HandleTypeDef structure that contains
+ * @param htsc pointer to a TSC_HandleTypeDef structure that contains
* the configuration information for the specified TSC.
* @retval None
*/
@@ -839,7 +837,7 @@ __weak void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc)
/**
* @brief Utility function used to set the acquired groups mask.
- * @param iomask: Channels IOs mask
+ * @param iomask Channels IOs mask
* @retval Acquired groups mask
*/
static uint32_t TSC_extract_groups(uint32_t iomask)
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c
index 3142744d3f..fd56fbca49 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_uart.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief UART HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
@@ -290,7 +288,7 @@ HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
/**
* @brief Initialize the UART mode according to the specified
* parameters in the UART_InitTypeDef and initialize the associated handle.
- * @param huart: UART handle.
+ * @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
@@ -353,7 +351,7 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
/**
* @brief Initialize the half-duplex mode according to the specified
* parameters in the UART_InitTypeDef and creates the associated handle.
- * @param huart: UART handle.
+ * @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
@@ -412,8 +410,8 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
/**
* @brief Initialize the LIN mode according to the specified
* parameters in the UART_InitTypeDef and creates the associated handle .
- * @param huart: UART handle.
- * @param BreakDetectLength: specifies the LIN break detection length.
+ * @param huart UART handle.
+ * @param BreakDetectLength specifies the LIN break detection length.
* This parameter can be one of the following values:
* @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
* @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
@@ -491,9 +489,9 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe
/**
* @brief Initialize the multiprocessor mode according to the specified
* parameters in the UART_InitTypeDef and initialize the associated handle.
- * @param huart: UART handle.
- * @param Address: UART node address (4-, 6-, 7- or 8-bit long).
- * @param WakeUpMethod: specifies the UART wakeup method.
+ * @param huart UART handle.
+ * @param Address UART node address (4-, 6-, 7- or 8-bit long).
+ * @param WakeUpMethod specifies the UART wakeup method.
* This parameter can be one of the following values:
* @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
* @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
@@ -567,7 +565,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add
/**
* @brief DeInitialize the UART peripheral.
- * @param huart: UART handle.
+ * @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
@@ -605,7 +603,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
/**
* @brief Initialize the UART MSP.
- * @param huart: UART handle.
+ * @param huart UART handle.
* @retval None
*/
__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
@@ -620,7 +618,7 @@ __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
/**
* @brief DeInitialize the UART MSP.
- * @param huart: UART handle.
+ * @param huart UART handle.
* @retval None
*/
__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
@@ -716,10 +714,10 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
/**
* @brief Send an amount of data in blocking mode.
- * @param huart: UART handle.
- * @param pData: Pointer to data buffer.
- * @param Size: Amount of data to be sent.
- * @param Timeout: Timeout duration.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer.
+ * @param Size Amount of data to be sent.
+ * @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
@@ -785,10 +783,10 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
/**
* @brief Receive an amount of data in blocking mode.
- * @param huart: UART handle.
- * @param pData: pointer to data buffer.
- * @param Size: amount of data to be received.
- * @param Timeout: Timeout duration.
+ * @param huart UART handle.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be received.
+ * @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
@@ -857,9 +855,9 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
/**
* @brief Send an amount of data in interrupt mode.
- * @param huart: UART handle.
- * @param pData: pointer to data buffer.
- * @param Size: amount of data to be sent.
+ * @param huart UART handle.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
@@ -898,9 +896,9 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData
/**
* @brief Receive an amount of data in interrupt mode.
- * @param huart: UART handle.
- * @param pData: pointer to data buffer.
- * @param Size: amount of data to be received.
+ * @param huart UART handle.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
@@ -945,9 +943,9 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData,
/**
* @brief Send an amount of data in DMA mode.
- * @param huart: UART handle.
- * @param pData: pointer to data buffer.
- * @param Size: amount of data to be sent.
+ * @param huart UART handle.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be sent.
* @note This function starts a DMA transfer in interrupt mode meaning that
* DMA half transfer complete, DMA transfer complete and DMA transfer
* error interrupts are enabled
@@ -1011,9 +1009,9 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat
/**
* @brief Receive an amount of data in DMA mode.
- * @param huart: UART handle.
- * @param pData: pointer to data buffer.
- * @param Size: amount of data to be received.
+ * @param huart UART handle.
+ * @param pData pointer to data buffer.
+ * @param Size amount of data to be received.
* @note When the UART parity is enabled (PCE = 1), the received data contain
* the parity bit (MSB position).
* @note This function starts a DMA transfer in interrupt mode meaning that
@@ -1081,7 +1079,7 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
/**
* @brief Pause the DMA Transfer.
- * @param huart: UART handle.
+ * @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
@@ -1114,7 +1112,7 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
/**
* @brief Resume the DMA Transfer.
- * @param huart: UART handle.
+ * @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
@@ -1148,7 +1146,7 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
/**
* @brief Stop the DMA Transfer.
- * @param huart: UART handle.
+ * @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
@@ -1612,7 +1610,7 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
/**
* @brief Handle UART interrupt request.
- * @param huart: UART handle.
+ * @param huart UART handle.
* @retval None
*/
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
@@ -1764,7 +1762,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
/**
* @brief Tx Transfer completed callback.
- * @param huart: UART handle.
+ * @param huart UART handle.
* @retval None
*/
__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
@@ -1779,7 +1777,7 @@ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
/**
* @brief Tx Half Transfer completed callback.
- * @param huart: UART handle.
+ * @param huart UART handle.
* @retval None
*/
__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
@@ -1794,7 +1792,7 @@ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
/**
* @brief Rx Transfer completed callback.
- * @param huart: UART handle.
+ * @param huart UART handle.
* @retval None
*/
__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
@@ -1809,7 +1807,7 @@ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
/**
* @brief Rx Half Transfer completed callback.
- * @param huart: UART handle.
+ * @param huart UART handle.
* @retval None
*/
__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
@@ -1824,7 +1822,7 @@ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
/**
* @brief UART error callback.
- * @param huart: UART handle.
+ * @param huart UART handle.
* @retval None
*/
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
@@ -1908,7 +1906,7 @@ __weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
/**
* @brief Enable UART in mute mode (does not mean UART enters mute mode;
* to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
- * @param huart: UART handle.
+ * @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
@@ -1929,7 +1927,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
/**
* @brief Disable UART mute mode (does not mean the UART actually exits mute mode
* as it may not have been in mute mode at this very moment).
- * @param huart: UART handle.
+ * @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
@@ -1950,7 +1948,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
/**
* @brief Enter UART mute mode (means UART actually enters mute mode).
* @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
- * @param huart: UART handle.
+ * @param huart UART handle.
* @retval None
*/
void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
@@ -1960,7 +1958,7 @@ void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
/**
* @brief Enable the UART transmitter and disable the UART receiver.
- * @param huart: UART handle.
+ * @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
@@ -1984,7 +1982,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
/**
* @brief Enable the UART receiver and disable the UART transmitter.
- * @param huart: UART handle.
+ * @param huart UART handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
@@ -2008,7 +2006,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
/**
* @brief Transmit break characters.
- * @param huart: UART handle.
+ * @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
@@ -2092,7 +2090,7 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
/**
* @brief Configure the UART peripheral.
- * @param huart: UART handle.
+ * @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
@@ -2203,7 +2201,7 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
/**
* @brief Configure the UART peripheral advanced features.
- * @param huart: UART handle.
+ * @param huart UART handle.
* @retval None
*/
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
@@ -2766,8 +2764,8 @@ HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
/**
* @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
- * @param huart: UART handle.
- * @param WakeUpSelection: UART wake up from stop mode parameters.
+ * @param huart UART handle.
+ * @param WakeUpSelection UART wake up from stop mode parameters.
* @retval None
*/
void UART_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c
index 79057491ad..0c90d45346 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_uart_ex.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_uart_ex.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief Extended UART HAL module driver.
* This file provides firmware functions to manage the following extended
* functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
@@ -153,16 +151,16 @@
/**
* @brief Initialize the RS485 Driver enable feature according to the specified
* parameters in the UART_InitTypeDef and creates the associated handle.
- * @param huart: UART handle.
- * @param Polarity: select the driver enable polarity.
+ * @param huart UART handle.
+ * @param Polarity select the driver enable polarity.
* This parameter can be one of the following values:
* @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
* @arg @ref UART_DE_POLARITY_LOW DE signal is active low
- * @param AssertionTime: Driver Enable assertion time:
+ * @param AssertionTime Driver Enable assertion time:
* 5-bit value defining the time between the activation of the DE (Driver Enable)
* signal and the beginning of the start bit. It is expressed in sample time
* units (1/8 or 1/16 bit time, depending on the oversampling rate)
- * @param DeassertionTime: Driver Enable deassertion time:
+ * @param DeassertionTime Driver Enable deassertion time:
* 5-bit value defining the time between the end of the last stop bit, in a
* transmitted message, and the de-activation of the DE (Driver Enable) signal.
* It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
@@ -259,7 +257,7 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity,
/**
* @brief UART wakeup from Stop mode callback.
- * @param huart: UART handle.
+ * @param huart UART handle.
* @retval None
*/
__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
@@ -298,8 +296,8 @@ __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
/**
* @brief Set Wakeup from Stop mode interrupt flag selection.
- * @param huart: UART handle.
- * @param WakeUpSelection: address match, Start Bit detection or RXNE bit status.
+ * @param huart UART handle.
+ * @param WakeUpSelection address match, Start Bit detection or RXNE bit status.
* This parameter can be one of the following values:
* @arg @ref UART_WAKEUP_ON_ADDRESS
* @arg @ref UART_WAKEUP_ON_STARTBIT
@@ -359,7 +357,7 @@ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huar
/**
* @brief Enable UART Stop Mode.
* @note The UART is able to wake up the MCU from Stop mode as long as UART clock is HSI or LSE.
- * @param huart: UART handle.
+ * @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
@@ -385,7 +383,7 @@ HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
/**
* @brief Disable UART Stop Mode.
- * @param huart: UART handle.
+ * @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
@@ -416,8 +414,8 @@ HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
* long).
* @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
* 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
- * @param huart: UART handle.
- * @param AddressLength: this parameter can be one of the following values:
+ * @param huart UART handle.
+ * @param AddressLength this parameter can be one of the following values:
* @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
* @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
* @retval HAL status
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_usart.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_usart.c
index 19984de29e..e5e2a8ebab 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_usart.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_usart.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_usart.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief USART HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Universal Synchronous Asynchronous Receiver Transmitter
@@ -355,7 +353,7 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
/**
* @brief Initialize the USART MSP.
- * @param husart: USART handle.
+ * @param husart USART handle.
* @retval None
*/
__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
@@ -370,7 +368,7 @@ __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
/**
* @brief DeInitialize the USART MSP.
- * @param husart: USART handle.
+ * @param husart USART handle.
* @retval None
*/
__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
@@ -1582,7 +1580,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
/**
* @brief Tx Transfer completed callback.
- * @param husart: USART handle.
+ * @param husart USART handle.
* @retval None
*/
__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
@@ -1597,7 +1595,7 @@ __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
/**
* @brief Tx Half Transfer completed callback.
- * @param husart: USART handle.
+ * @param husart USART handle.
* @retval None
*/
__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
@@ -1612,7 +1610,7 @@ __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
/**
* @brief Rx Transfer completed callback.
- * @param husart: USART handle.
+ * @param husart USART handle.
* @retval None
*/
__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
@@ -1627,7 +1625,7 @@ __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
/**
* @brief Rx Half Transfer completed callback.
- * @param husart: USART handle.
+ * @param husart USART handle.
* @retval None
*/
__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
@@ -1642,7 +1640,7 @@ __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
/**
* @brief Tx/Rx Transfers completed callback for the non-blocking process.
- * @param husart: USART handle.
+ * @param husart USART handle.
* @retval None
*/
__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
@@ -1657,7 +1655,7 @@ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
/**
* @brief USART error callback.
- * @param husart: USART handle.
+ * @param husart USART handle.
* @retval None
*/
__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
@@ -1708,7 +1706,7 @@ __weak void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
/**
* @brief Return the USART handle state.
- * @param husart : pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART.
* @retval USART handle state
*/
@@ -1719,7 +1717,7 @@ HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
/**
* @brief Return the USART error code.
- * @param husart : pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART.
* @retval USART handle Error Code
*/
@@ -1876,7 +1874,7 @@ static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
/**
* @brief DMA USART communication error callback.
- * @param hdma: DMA handle.
+ * @param hdma DMA handle.
* @retval None
*/
static void USART_DMAError(DMA_HandleTypeDef *hdma)
@@ -2028,7 +2026,7 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar
/**
* @brief Configure the USART peripheral.
- * @param husart: USART handle.
+ * @param husart USART handle.
* @retval HAL status
*/
static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
@@ -2109,7 +2107,7 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
/**
* @brief Check the USART Idle State.
- * @param husart: USART handle.
+ * @param husart USART handle.
* @retval HAL status
*/
static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
@@ -2291,7 +2289,7 @@ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
* @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
* @note Function called under interruption only, once
* interruptions have been enabled by HAL_USART_TransmitReceive_IT().
- * @param husart: USART handle.
+ * @param husart USART handle.
* @retval HAL status
*/
static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_wwdg.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_wwdg.c
index 46afec7d38..4a70e7f314 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_wwdg.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_wwdg.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_hal_wwdg.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief WWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Window Watchdog (WWDG) peripheral:
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_adc.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_adc.c
index 62fcc9732d..c96a45330e 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_adc.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_adc.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_ll_adc.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief ADC LL module driver
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_comp.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_comp.c
index ea8fa70c01..4e04504fb2 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_comp.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_comp.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_ll_comp.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief COMP LL module driver
******************************************************************************
* @attention
@@ -722,7 +720,7 @@ ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStru
/**
* @brief Set each @ref LL_COMP_InitTypeDef field to default value.
- * @param COMP_InitStruct: pointer to a @ref LL_COMP_InitTypeDef structure
+ * @param COMP_InitStruct pointer to a @ref LL_COMP_InitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
@@ -1012,7 +1010,7 @@ ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStru
/**
* @brief Set each @ref LL_COMP_InitTypeDef field to default value.
- * @param COMP_InitStruct: pointer to a @ref LL_COMP_InitTypeDef structure
+ * @param COMP_InitStruct pointer to a @ref LL_COMP_InitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_crc.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_crc.c
index bd8590173c..cf30ff3e72 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_crc.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_crc.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_ll_crc.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief CRC LL module driver.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dac.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dac.c
index 49d9b872bd..68ad01363f 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dac.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dac.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_ll_dac.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief DAC LL module driver
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dma.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dma.c
index f29189aed9..2e03385a70 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dma.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dma.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_ll_dma.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief DMA LL module driver.
******************************************************************************
* @attention
@@ -83,7 +81,7 @@
((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
-#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= (uint32_t)0x0000FFFFU)
+#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
@@ -319,15 +317,15 @@ uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DM
void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
{
/* Set DMA_InitStruct fields to default values */
- DMA_InitStruct->PeriphOrM2MSrcAddress = (uint32_t)0x00000000U;
- DMA_InitStruct->MemoryOrM2MDstAddress = (uint32_t)0x00000000U;
+ DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
+ DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
- DMA_InitStruct->NbData = (uint32_t)0x00000000U;
+ DMA_InitStruct->NbData = 0x00000000U;
DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
}
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_exti.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_exti.c
index f97e9ab7fc..47c9f22721 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_exti.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_exti.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_ll_exti.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief EXTI LL module driver.
******************************************************************************
* @attention
@@ -110,7 +108,7 @@ uint32_t LL_EXTI_DeInit(void)
LL_EXTI_WriteReg(FTSR, 0x00000000U);
/* Software interrupt event register set to default reset values */
LL_EXTI_WriteReg(SWIER, 0x00000000U);
- /* Pending register set to default reset values */
+ /* Pending register clear */
LL_EXTI_WriteReg(PR, 0x007FFFFFU);
#if defined(EXTI_32_63_SUPPORT)
@@ -128,7 +126,7 @@ uint32_t LL_EXTI_DeInit(void)
LL_EXTI_WriteReg(FTSR2, 0x00000000U);
/* Software interrupt event register 2 set to default reset values */
LL_EXTI_WriteReg(SWIER2, 0x00000000U);
- /* Pending register 2 set to default reset values */
+ /* Pending register 2 clear */
LL_EXTI_WriteReg(PR2, 0x00000003U);
#endif
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_fmc.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_fmc.c
index d01176ebae..1cfcf2f0e7 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_fmc.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_fmc.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_ll_fmc.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief FMC Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_gpio.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_gpio.c
index 3d8d4b5a08..dea7d7b231 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_gpio.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_gpio.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_ll_gpio.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief GPIO LL module driver.
******************************************************************************
* @attention
@@ -62,7 +60,7 @@
/** @addtogroup GPIO_LL_Private_Macros
* @{
*/
-#define IS_LL_GPIO_PIN(__VALUE__) ((((uint32_t)0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
+#define IS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\
((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\
@@ -187,7 +185,7 @@ ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
/**
* @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
* @param GPIOx GPIO Port
- * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
+ * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
* that contains the configuration information for the specified GPIO peripheral.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
@@ -264,7 +262,7 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru
/**
* @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
- * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
+ * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
@@ -301,4 +299,3 @@ void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_hrtim.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_hrtim.c
index 1b7016c422..178955b988 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_hrtim.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_hrtim.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_ll_hrtim.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief HRTIM LL module driver.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_i2c.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_i2c.c
index c792eb2b0a..95c23b94bd 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_i2c.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_i2c.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_ll_i2c.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief I2C LL module driver.
******************************************************************************
* @attention
@@ -73,7 +71,7 @@
#define IS_LL_I2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU)
-#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= (uint32_t)0x000003FFU)
+#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU)
#define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__) (((__VALUE__) == LL_I2C_ACK) || \
((__VALUE__) == LL_I2C_NACK))
@@ -194,7 +192,12 @@ uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
*/
LL_I2C_DisableOwnAddress1(I2Cx);
LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
- LL_I2C_EnableOwnAddress1(I2Cx);
+
+ /* OwnAdress1 == 0 is reserved for General Call address */
+ if (I2C_InitStruct->OwnAddress1 != 0U)
+ {
+ LL_I2C_EnableOwnAddress1(I2Cx);
+ }
/*---------------------------- I2Cx MODE Configuration -----------------------
* Configure I2Cx peripheral mode with parameter :
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_opamp.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_opamp.c
index f8eb5f630e..d024c4637e 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_opamp.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_opamp.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_ll_opamp.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief OPAMP LL module driver
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_pwr.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_pwr.c
index 84386f2104..bee886d354 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_pwr.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_pwr.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_ll_pwr.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief PWR LL module driver.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rcc.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rcc.c
index d7f13104d4..5872914535 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rcc.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rcc.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_ll_rcc.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief RCC LL module driver.
******************************************************************************
* @attention
@@ -59,7 +57,7 @@
* @{
*/
#if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
-const uint16_t aADCPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
+const uint16_t aADCPrescTable[16] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U, 256U, 256U, 256U, 256U};
#endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
#if defined(RCC_CFGR_SDPRE)
const uint8_t aSDADCPrescTable[16] = {2U, 4U, 6U, 8U, 10U, 12U, 14U, 16U, 20U, 24U, 28U, 32U, 36U, 40U, 44U, 48U};
@@ -621,7 +619,7 @@ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
* @param I2SxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_I2S_CLKSOURCE
* @retval I2S clock frequency (in Hz)
- * @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used */
+ * @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used */
uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
{
uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
@@ -675,7 +673,7 @@ uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
default:
if (LL_RCC_PLL_IsReady())
{
- usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 3) / 2;
+ usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 3U) / 2U;
}
break;
}
@@ -969,7 +967,7 @@ uint32_t LL_RCC_GetHRTIMClockFreq(uint32_t HRTIMxSource)
assert_param(IS_LL_RCC_HRTIM_CLKSOURCE(HRTIMxSource));
/* HRTIM1CLK clock frequency */
- if (LL_RCC_GetTIMClockSource(LL_RCC_HRTIM1_CLKSOURCE) == LL_RCC_HRTIM1_CLKSOURCE_PCLK2)
+ if (LL_RCC_GetHRTIMClockSource(LL_RCC_HRTIM1_CLKSOURCE) == LL_RCC_HRTIM1_CLKSOURCE_PCLK2)
{
/* PCLK2 used as HRTIM1 clock source */
hrtim_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
@@ -1080,7 +1078,7 @@ uint32_t RCC_PLL_GetFreqDomain_SYS(void)
pllinputfreq = HSI_VALUE;
#else
case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */
- pllinputfreq = HSI_VALUE / 2;
+ pllinputfreq = HSI_VALUE / 2U;
#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
break;
@@ -1092,7 +1090,7 @@ uint32_t RCC_PLL_GetFreqDomain_SYS(void)
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
pllinputfreq = HSI_VALUE;
#else
- pllinputfreq = HSI_VALUE / 2;
+ pllinputfreq = HSI_VALUE / 2U;
#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
break;
}
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rtc.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rtc.c
index e461598b84..93fe96dd5c 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rtc.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_rtc.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_ll_rtc.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief RTC LL module driver.
******************************************************************************
* @attention
@@ -62,12 +60,12 @@
* @{
*/
/* Default values used for prescaler */
-#define RTC_ASYNCH_PRESC_DEFAULT ((uint32_t) 0x0000007FU)
-#define RTC_SYNCH_PRESC_DEFAULT ((uint32_t) 0x000000FFU)
+#define RTC_ASYNCH_PRESC_DEFAULT 0x0000007FU
+#define RTC_SYNCH_PRESC_DEFAULT 0x000000FFU
/* Values used for timeout */
-#define RTC_INITMODE_TIMEOUT ((uint32_t) 1000U) /* 1s when tick set to 1ms */
-#define RTC_SYNCHRO_TIMEOUT ((uint32_t) 1000U) /* 1s when tick set to 1ms */
+#define RTC_INITMODE_TIMEOUT 1000U /* 1s when tick set to 1ms */
+#define RTC_SYNCHRO_TIMEOUT 1000U /* 1s when tick set to 1ms */
/**
* @}
*/
@@ -80,9 +78,9 @@
#define IS_LL_RTC_HOURFORMAT(__VALUE__) (((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \
|| ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM))
-#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= (uint32_t)0x7FU)
+#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FU)
-#define IS_LL_RTC_SYNCH_PREDIV(__VALUE__) ((__VALUE__) <= (uint32_t)0x7FFFU)
+#define IS_LL_RTC_SYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FFFU)
#define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \
|| ((__VALUE__) == LL_RTC_FORMAT_BCD))
@@ -103,7 +101,7 @@
|| ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \
|| ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY))
-#define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= (uint32_t)1U) && ((__DAY__) <= (uint32_t)31U))
+#define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= 1U) && ((__DAY__) <= 31U))
#define IS_LL_RTC_MONTH(__VALUE__) (((__VALUE__) == LL_RTC_MONTH_JANUARY) \
|| ((__VALUE__) == LL_RTC_MONTH_FEBRUARY) \
@@ -381,7 +379,7 @@ void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct)
* @param RTC_Format This parameter can be one of the following values:
* @arg @ref LL_RTC_FORMAT_BIN
* @arg @ref LL_RTC_FORMAT_BCD
- * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains
+ * @param RTC_DateStruct pointer to a RTC_DateTypeDef structure that contains
* the date configuration information for the RTC.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: RTC Day register is configured
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_spi.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_spi.c
index 387e8955fc..25dbfcb514 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_spi.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_spi.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_ll_spi.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief SPI LL module driver.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_tim.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_tim.c
index 83b7ab4aba..fbd4fa41e6 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_tim.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_tim.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_ll_tim.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief TIM LL module driver.
******************************************************************************
* @attention
@@ -186,24 +184,24 @@
|| ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
#define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
- || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
+ || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
#define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
- || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
+ || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
#endif /* TIM_BDTR_BK2E */
#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
@@ -397,7 +395,7 @@ void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
/* Set the default configuration */
TIM_InitStruct->Prescaler = (uint16_t)0x0000U;
TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
- TIM_InitStruct->Autoreload = (uint32_t)0xFFFFFFFFU;
+ TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U;
}
@@ -467,7 +465,7 @@ void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
- TIM_OC_InitStruct->CompareValue = (uint32_t)0x00000000U;
+ TIM_OC_InitStruct->CompareValue = 0x00000000U;
TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
@@ -672,7 +670,7 @@ void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorI
TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
- TIM_HallSensorInitStruct->CommutationDelay = (uint32_t)0U;
+ TIM_HallSensorInitStruct->CommutationDelay = 0U;
}
/**
@@ -790,14 +788,14 @@ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
- TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
#endif /* TIM_BDTR_BK2E */
+ TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
}
/**
* @brief Configure the Break and Dead Time feature of the timer instance.
* @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
- * and DTG[7:0] can be write-locked depending on the LOCK configuration, it
+ * and DTG[7:0] can be write-locked depending on the LOCK configuration, it
* can be necessary to configure all of them during the first write access to
* the TIMx_BDTR register.
* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
@@ -805,7 +803,7 @@ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a second break input.
* @param TIMx Timer Instance
- * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
+ * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure(Break and Dead Time configuration data structure)
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Break and Dead Time is initialized
* - ERROR: not applicable
@@ -813,7 +811,7 @@ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
{
uint32_t tmpbdtr = 0;
-
+
/* Check the parameters */
assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
@@ -822,10 +820,10 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT
assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
-
+
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
-
+
/* Set the BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
@@ -849,17 +847,17 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT
assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
-
+
/* Set the BREAK2 input related BDTR bit-fields */
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
}
#endif /* TIM_BDTR_BK2E */
-
+
/* Set TIMx_BDTR */
LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
-
+
return SUCCESS;
}
/**
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_usart.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_usart.c
index 73d201b164..7809ccb915 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_usart.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_usart.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_ll_usart.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief USART LL module driver.
******************************************************************************
* @attention
@@ -77,6 +75,12 @@
* divided by the smallest oversampling used on the USART (i.e. 8) */
#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 9000000U)
+/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
+#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
+
+/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */
+#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
+
#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
|| ((__VALUE__) == LL_USART_DIRECTION_RX) \
|| ((__VALUE__) == LL_USART_DIRECTION_TX) \
@@ -208,7 +212,7 @@ ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
* USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
* @param USARTx USART Instance
- * @param USART_InitStruct: pointer to a LL_USART_InitTypeDef structure
+ * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure
* that contains the configuration information for the specified USART peripheral.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: USART registers are initialized according to USART_InitStruct content
@@ -236,7 +240,7 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini
CRx registers */
if (LL_USART_IsEnabled(USARTx) == 0U)
{
- /*---------------------------- USART CR1 Configuration -----------------------
+ /*---------------------------- USART CR1 Configuration ---------------------
* Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
* - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value
* - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
@@ -249,20 +253,20 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini
(USART_InitStruct->DataWidth | USART_InitStruct->Parity |
USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
- /*---------------------------- USART CR2 Configuration -----------------------
+ /*---------------------------- USART CR2 Configuration ---------------------
* Configure USARTx CR2 (Stop bits) with parameters:
* - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
* - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
*/
LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
- /*---------------------------- USART CR3 Configuration -----------------------
+ /*---------------------------- USART CR3 Configuration ---------------------
* Configure USARTx CR3 (Hardware Flow Control) with parameters:
* - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
*/
LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
- /*---------------------------- USART BRR Configuration -----------------------
+ /*---------------------------- USART BRR Configuration ---------------------
* Retrieve Clock frequency used for USART Peripheral
*/
if (USARTx == USART1)
@@ -318,6 +322,12 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini
periphclk,
USART_InitStruct->OverSampling,
USART_InitStruct->BaudRate);
+
+ /* Check BRR is greater than or equal to 16d */
+ assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
+
+ /* Check BRR is greater than or equal to 16d */
+ assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR));
}
}
/* Endif (=> USART not in Disabled state => return ERROR) */
@@ -327,7 +337,7 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini
/**
* @brief Set each @ref LL_USART_InitTypeDef field to default value.
- * @param USART_InitStruct: pointer to a @ref LL_USART_InitTypeDef structure
+ * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
@@ -350,7 +360,7 @@ void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
* @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
* USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @param USARTx USART Instance
- * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
+ * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
* that contains the Clock configuration information for the specified USART peripheral.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
@@ -411,7 +421,7 @@ ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef
/**
* @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
- * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
+ * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
diff --git a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_utils.c b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_utils.c
index d18ff57502..33e72c200c 100644
--- a/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_utils.c
+++ b/system/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_utils.c
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f3xx_ll_utils.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 16-December-2016
* @brief UTILS LL module driver.
******************************************************************************
* @attention
@@ -61,15 +59,15 @@
*/
/* Defines used for PLL range */
-#define UTILS_PLL_OUTPUT_MAX ((uint32_t)72000000U) /*!< Frequency max for PLL output, in Hz */
+#define UTILS_PLL_OUTPUT_MAX 72000000U /*!< Frequency max for PLL output, in Hz */
/* Defines used for HSE range */
-#define UTILS_HSE_FREQUENCY_MIN ((uint32_t)4000000U) /*!< Frequency min for HSE frequency, in Hz */
-#define UTILS_HSE_FREQUENCY_MAX ((uint32_t)32000000U) /*!< Frequency max for HSE frequency, in Hz */
+#define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
+#define UTILS_HSE_FREQUENCY_MAX 32000000U /*!< Frequency max for HSE frequency, in Hz */
/* Defines used for FLASH latency according to SYSCLK Frequency */
-#define UTILS_LATENCY1_FREQ ((uint32_t)24000000U) /*!< SYSCLK frequency to set FLASH latency 1 */
-#define UTILS_LATENCY2_FREQ ((uint32_t)48000000U) /*!< SYSCLK frequency to set FLASH latency 2 */
+#define UTILS_LATENCY1_FREQ 24000000U /*!< SYSCLK frequency to set FLASH latency 1 */
+#define UTILS_LATENCY2_FREQ 48000000U /*!< SYSCLK frequency to set FLASH latency 2 */
/**
* @}
*/
@@ -140,7 +138,9 @@
*/
static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
+#if defined(FLASH_ACR_LATENCY)
static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency);
+#endif /* FLASH_ACR_LATENCY */
static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
static ErrorStatus UTILS_PLL_IsBusy(void);
/**
@@ -277,7 +277,6 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS
/* Force PREDIV value to 2 */
UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2;
#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
-
/* Calculate the new PLL output frequency */
pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
@@ -317,7 +316,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS
* - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
* - PREDIV: Set to 2 for few devices
* - PLLMUL: The application software must set correctly the PLL multiplication factor to
- * not exceed 72MHz
+ * not exceed @ref UTILS_PLL_OUTPUT_MAX
* @note FLASH latency can be modified through this function.
* @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 32000000
* @param HSEBypass This parameter can be one of the following values:
@@ -379,7 +378,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
#else
- LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC_HSE_PREDIV | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul);
+ LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC_HSE_PREDIV | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul);
#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
/* Enable PLL and switch system clock to PLL */
@@ -413,6 +412,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa
* - SUCCESS: Latency has been modified
* - ERROR: Latency cannot be modified
*/
+#if defined(FLASH_ACR_LATENCY)
static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency)
{
ErrorStatus status = SUCCESS;
@@ -452,6 +452,7 @@ static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency)
}
return status;
}
+#endif /* FLASH_ACR_LATENCY */
/**
* @brief Function to check that PLL can be modified
@@ -469,7 +470,7 @@ static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTIL
/* Check different PLL parameters according to RM */
/* The application software must set correctly the PLL multiplication factor to
- not exceed 72MHz */
+ not exceed @ref UTILS_PLL_OUTPUT_MAX */
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
#else
@@ -497,7 +498,6 @@ static ErrorStatus UTILS_PLL_IsBusy(void)
status = ERROR;
}
-
return status;
}
@@ -520,7 +520,7 @@ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_
assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
/* Calculate current SYSCLK frequency */
- sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[(UTILS_ClkInitStruct->AHBCLKDivider & RCC_CFGR_HPRE) >> RCC_POSITION_HPRE]);
+ sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[LL_RCC_GetAHBPrescaler() >> RCC_POSITION_HPRE]);
/* Increasing the number of wait states because of higher CPU frequency */
if (sysclk_frequency_current < SYSCLK_Frequency)
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
index 12696eb54e..08e8923748 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32_hal_legacy.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief This file contains aliases definition for the STM32Cube HAL constants
* macros and functions maintained for legacy purpose.
******************************************************************************
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32_assert_template.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32_assert_template.h
index c8d7d79135..1bd66f9b77 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32_assert_template.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32_assert_template.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32_assert.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief STM32 assert template file.
* This file should be copied to the application folder and renamed
* to stm32_assert.h.
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h
index d09244ad1e..2e6d2ea9ea 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h
index 5c73403920..60973f717b 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_adc.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of ADC HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h
index 950ff8959c..c909deef3d 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_adc_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_adc_ex.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of ADC HAL extended module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_can.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_can.h
index a7dd7601b5..6d097d23e2 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_can.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_can.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_can.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of CAN HAL module.
******************************************************************************
* @attention
@@ -258,6 +258,8 @@ typedef struct
#define HAL_CAN_ERROR_BR ((uint32_t)0x00000040) /*!< Bit recessive */
#define HAL_CAN_ERROR_BD ((uint32_t)0x00000080) /*!< LEC dominant */
#define HAL_CAN_ERROR_CRC ((uint32_t)0x00000100) /*!< LEC transfer error */
+#define HAL_CAN_ERROR_FOV0 ((uint32_t)0x00000200) /*!< FIFO0 overrun error */
+#define HAL_CAN_ERROR_FOV1 ((uint32_t)0x00000400) /*!< FIFO1 overrun error */
/**
* @}
*/
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_comp.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_comp.h
index 34929fea53..f29a5971a1 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_comp.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_comp.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_comp.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of COMP HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_conf_template.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_conf_template.h
index 3fd84da0ff..fe1a6ddd09 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_conf_template.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_conf_template.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_conf.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief HAL configuration template file.
* This file should be copied to the application folder and renamed
* to stm32l4xx_hal_conf.h.
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h
index a75cc8b1d9..93e8efb3f4 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_cortex.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc.h
index 0b33ad0282..1e29ddbefe 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_crc.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc_ex.h
index cd436a983f..5526c64846 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc_ex.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_crc_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_crc_ex.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of CRC HAL extended module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cryp.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cryp.h
index a36fdad63c..d81de012b6 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cryp.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cryp.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_cryp.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of CRYP HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cryp_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cryp_ex.h
index d4dedad99f..f44e303d57 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cryp_ex.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cryp_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_cryp_ex.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of CRYPEx HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dac.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dac.h
index 8a7bf372e8..cb75963928 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dac.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dac.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_dac.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dac_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dac_ex.h
index dc2a1a63ca..d83705c2d3 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dac_ex.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dac_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_dac_ex.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of DAC HAL Extended module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dcmi.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dcmi.h
index c925d8cd39..f471267f13 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dcmi.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dcmi.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_dcmi.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of DCMI HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h
index a751e90711..817962db49 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_def.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dfsdm.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dfsdm.h
index 4edeb9ed81..eb29d40256 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dfsdm.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dfsdm.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_dfsdm.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of DFSDM HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h
index 209e551390..b62814cd41 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_dma.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma2d.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma2d.h
index 2f64e43242..1b83440961 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma2d.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma2d.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_dma2d.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of DMA2D HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_firewall.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_firewall.h
index 0e1a938cf2..b0e23983b9 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_firewall.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_firewall.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_firewall.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of FIREWALL HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h
index 19e8ba6e76..f6a7ae5a9c 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_flash.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of FLASH HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h
index ad7e59596d..098adc0b1c 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_flash_ex.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of FLASH HAL Extended module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h
index efad8491b5..6419a267b7 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_flash_ramfunc.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of FLASH RAMFUNC driver.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h
index 504a05c32e..07a36894f5 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_gpio.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h
index 5e8b16d1dd..19e269bea9 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_gpio_ex.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of GPIO HAL Extended module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hash.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hash.h
index cd96e60006..63a652e35b 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hash.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hash.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_hash.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of HASH HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hash_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hash_ex.h
index 8cd6245a18..83c47f5f32 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hash_ex.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hash_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_hash_ex.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of HASH HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hcd.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hcd.h
index 8dc284d42b..31fafa7517 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hcd.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_hcd.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_hcd.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of HCD HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h
index c074115dd4..0ac5504f1a 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_i2c.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h
index 804c4564c3..d7498f4dec 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_i2c_ex.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of I2C HAL Extended module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_irda.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_irda.h
index 0505ad6e22..502ef502e0 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_irda.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_irda.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_irda.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of IRDA HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_irda_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_irda_ex.h
index df3d7e375b..89cee3242a 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_irda_ex.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_irda_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_irda_ex.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of IRDA HAL Extended module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_iwdg.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_iwdg.h
index d8897d16e7..12b720ac73 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_iwdg.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_iwdg.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_iwdg.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of IWDG HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_lcd.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_lcd.h
index 81f39051ad..5114e5f624 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_lcd.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_lcd.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_lcd.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of LCD Controller HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_lptim.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_lptim.h
index c2cbc9e1d9..5206dee441 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_lptim.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_lptim.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_lptim.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of LPTIM HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_nand.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_nand.h
index 87c1a285fd..5265a93683 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_nand.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_nand.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_nand.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of NAND HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_nor.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_nor.h
index a83665e3d9..5de11e7699 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_nor.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_nor.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_nor.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of NOR HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_opamp.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_opamp.h
index 0621bbc1f5..0c200406c1 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_opamp.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_opamp.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_opamp.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of OPAMP HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_opamp_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_opamp_ex.h
index b89fd157c6..70042aea19 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_opamp_ex.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_opamp_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_opamp_ex.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of OPAMP HAL Extended module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h
index 6032db9e2a..585dcf0060 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_pcd.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h
index 4b94f33e91..137f0dafea 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_pcd_ex.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h
index 1b444c4cf4..99d118cbe5 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_pwr.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h
index 8500c8b302..2923ce47f6 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_pwr_ex.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of PWR HAL Extended module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_qspi.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_qspi.h
index 2437210e4e..4c531d0ea4 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_qspi.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_qspi.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_qspi.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of QSPI HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h
index 157576fed6..c5e10dd59e 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_rcc.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of RCC HAL module.
******************************************************************************
* @attention
@@ -545,34 +545,34 @@ typedef struct
* @{
*/
/* Flags in the CR register */
-#define RCC_FLAG_MSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_MSIRDY))) /*!< MSI Ready flag */
-#define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< HSI Ready flag */
-#define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY))) /*!< HSE Ready flag */
-#define RCC_FLAG_PLLRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL Ready flag */
-#define RCC_FLAG_PLLSAI1RDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLSAI1RDY))) /*!< PLLSAI1 Ready flag */
+#define RCC_FLAG_MSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos)) /*!< MSI Ready flag */
+#define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< HSI Ready flag */
+#define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< HSE Ready flag */
+#define RCC_FLAG_PLLRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL Ready flag */
+#define RCC_FLAG_PLLSAI1RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI1RDY_Pos)) /*!< PLLSAI1 Ready flag */
#if defined(RCC_PLLSAI2_SUPPORT)
-#define RCC_FLAG_PLLSAI2RDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLSAI2RDY))) /*!< PLLSAI2 Ready flag */
+#define RCC_FLAG_PLLSAI2RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLSAI2RDY_Pos)) /*!< PLLSAI2 Ready flag */
#endif /* RCC_PLLSAI2_SUPPORT */
/* Flags in the BDCR register */
-#define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< LSE Ready flag */
-#define RCC_FLAG_LSECSSD ((uint32_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSECSSD))) /*!< LSE Clock Security System Interrupt flag */
+#define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< LSE Ready flag */
+#define RCC_FLAG_LSECSSD ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos)) /*!< LSE Clock Security System Interrupt flag */
/* Flags in the CSR register */
-#define RCC_FLAG_LSIRDY ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< LSI Ready flag */
-#define RCC_FLAG_RMVF ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_RMVF))) /*!< Remove reset flag */
-#define RCC_FLAG_FWRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_FWRSTF))) /*!< Firewall reset flag */
-#define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF))) /*!< Option Byte Loader reset flag */
-#define RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */
-#define RCC_FLAG_BORRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_BORRSTF))) /*!< BOR reset flag */
-#define RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */
-#define RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */
-#define RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */
-#define RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */
+#define RCC_FLAG_LSIRDY ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)) /*!< LSI Ready flag */
+#define RCC_FLAG_RMVF ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_RMVF_Pos)) /*!< Remove reset flag */
+#define RCC_FLAG_FWRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_FWRSTF_Pos)) /*!< Firewall reset flag */
+#define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)) /*!< Option Byte Loader reset flag */
+#define RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */
+#define RCC_FLAG_BORRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos)) /*!< BOR reset flag */
+#define RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */
+#define RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */
+#define RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */
+#define RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */
#if defined(RCC_HSI48_SUPPORT)
/* Flags in the CRRCR register */
-#define RCC_FLAG_HSI48RDY ((uint32_t)((CRRCR_REG_INDEX << 5U) | POSITION_VAL(RCC_CRRCR_HSI48RDY))) /*!< HSI48 Ready flag */
+#define RCC_FLAG_HSI48RDY ((uint32_t)((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos)) /*!< HSI48 Ready flag */
#endif /* RCC_HSI48_SUPPORT */
/**
* @}
@@ -3348,7 +3348,7 @@ typedef struct
* @retval None
*/
#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
- MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_ICSCR_HSITRIM))
+ MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos)
/**
* @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI)
@@ -4055,7 +4055,7 @@ typedef struct
#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
-#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)( RCC_ICSCR_HSITRIM >> POSITION_VAL(RCC_ICSCR_HSITRIM)))
+#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)( RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos))
#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h
index ea359a5118..e8050fc488 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_rcc_ex.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of RCC HAL Extended module.
******************************************************************************
* @attention
@@ -772,18 +772,18 @@ typedef struct
#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
- WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | \
- ((((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) | \
- ((((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)) | \
- ((__PLLSAI1P__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV)))
+ WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \
+ ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \
+ ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \
+ ((__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))
#else
#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
- WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | \
- (((__PLLSAI1P__) >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)) | \
- ((((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) | \
- ((((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)))
+ WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \
+ (((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) | \
+ ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \
+ ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos))
#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
@@ -803,7 +803,7 @@ typedef struct
* @retval None
*/
#define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) \
- MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N))
+ MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
/** @brief Macro to configure the PLLSAI1 clock division factor P.
*
@@ -821,12 +821,12 @@ typedef struct
#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
#define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \
- MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV))
+ MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)
#else
#define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \
- MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P))
+ MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)
#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
@@ -843,7 +843,7 @@ typedef struct
* @retval None
*/
#define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) \
- MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q))
+ MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)
/** @brief Macro to configure the PLLSAI1 clock division factor R.
*
@@ -858,7 +858,7 @@ typedef struct
* @retval None
*/
#define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) \
- MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R))
+ MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)
/**
* @brief Macros to enable or disable the PLLSAI1.
@@ -929,16 +929,16 @@ typedef struct
#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
- WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) | \
- ((((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)) | \
- ((__PLLSAI2P__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2PDIV)))
+ WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \
+ ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) | \
+ ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))
#else
#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
- WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) | \
- (((__PLLSAI2P__) >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)) | \
- ((((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)))
+ WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \
+ (((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) | \
+ ((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos))
#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
@@ -959,7 +959,7 @@ typedef struct
* @retval None
*/
#define __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) \
- MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N))
+ MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
/** @brief Macro to configure the PLLSAI2 clock division factor P.
*
@@ -974,7 +974,7 @@ typedef struct
* @retval None
*/
#define __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) \
- MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P))
+ MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos)
/** @brief Macro to configure the PLLSAI2 clock division factor R.
*
@@ -989,7 +989,7 @@ typedef struct
* @retval None
*/
#define __HAL_RCC_PLLSAI2_DIVR_CONFIG(__PLLSAI2R__) \
- MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R))
+ MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)
/**
* @brief Macros to enable or disable the PLLSAI2.
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rng.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rng.h
index 1c23674d24..3c3008f830 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rng.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rng.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_rng.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of RNG HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc.h
index 993ff6a978..9f24aec53e 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_rtc.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of RTC HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h
index 0f6509951c..aab74b910d 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_rtc_ex.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of RTC HAL Extended module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai.h
index 70afe935ba..8e1ac0570e 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sai.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_sai.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of SAI HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sd.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sd.h
index c78440f668..b3af962d78 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sd.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sd.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_sd.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of SD HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smartcard.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smartcard.h
index b87bf1119e..c0cf21a78c 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smartcard.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smartcard.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_smartcard.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of SMARTCARD HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smartcard_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smartcard_ex.h
index 265f36fefc..014eb6e28d 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smartcard_ex.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smartcard_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_smartcard_ex.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of SMARTCARD HAL Extended module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smbus.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smbus.h
index b62a026f9c..10e2d0ab72 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smbus.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_smbus.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_smbus.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of SMBUS HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h
index 1b7f62ae5a..d0bad1956a 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_spi.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of SPI HAL module.
******************************************************************************
* @attention
@@ -611,6 +611,8 @@ typedef struct __SPI_HandleTypeDef
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1U) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0U))
+#define IS_SPI_DMA_HANDLE(HANDLE) ((HANDLE) != NULL)
+
/**
* @}
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h
index 23e64be655..a33dce672d 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_spi_ex.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of SPI HAL Extended module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sram.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sram.h
index f686e55d7e..5c73d92814 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sram.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sram.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_sram.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of SRAM HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_swpmi.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_swpmi.h
index c9aabca690..e6584194f8 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_swpmi.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_swpmi.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_swpmi.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of SWPMI HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h
index 804a8a5b11..073865387d 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_tim.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of TIM HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h
index 957557e2f5..92dffe3520 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_tim_ex.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of TIM HAL Extended module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tsc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tsc.h
index 77ed20fb7a..9694ce4d97 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tsc.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tsc.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_tsc.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of TSC HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h
index 9a66da8f21..8b8c4e5307 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_uart.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of UART HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h
index a9ea06d7bc..a4708c0ab5 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_uart_ex.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of UART HAL Extended module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_usart.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_usart.h
index f08ecfb729..640b662eef 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_usart.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_usart.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_usart.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of USART HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_usart_ex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_usart_ex.h
index 6d3211ea18..44491cdaef 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_usart_ex.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_usart_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_usart_ex.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of USART HAL Extended module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_wwdg.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_wwdg.h
index 9a2ee07a09..647af9e245 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_wwdg.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_wwdg.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_wwdg.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of WWDG HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h
index 3910c3843d..b6bfc30c20 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_adc.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_adc.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of ADC LL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h
index 725e527ff9..c4a023fc02 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_bus.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_bus.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of BUS LL module.
@verbatim
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_comp.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_comp.h
index 7703d0aaba..d5d7a2d644 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_comp.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_comp.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_comp.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of COMP LL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h
index 06c38b52c9..d450207304 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_cortex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_cortex.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of CORTEX LL module.
@verbatim
==============================================================================
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crc.h
index 9c48b753b6..252a5a95d4 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crc.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crc.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_crc.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of CRC LL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crs.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crs.h
index 8736ec6d6b..ccb894e39c 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crs.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_crs.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_crs.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of CRS LL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dac.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dac.h
index 63f61abed1..070118c337 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dac.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dac.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_dac.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of DAC LL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma.h
index 28a08fbe4d..553778f721 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_dma.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of DMA LL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma2d.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma2d.h
index 5b687f5995..e4b3dba468 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma2d.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_dma2d.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_dma2d.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of DMA2D LL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_exti.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_exti.h
index f7412d238f..7677111023 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_exti.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_exti.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_exti.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of EXTI LL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_fmc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_fmc.h
index c578ec5663..590abe7e7f 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_fmc.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_fmc.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_fmc.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of FMC HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_gpio.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_gpio.h
index 0ca5fff0ae..f96ebb9c7c 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_gpio.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_gpio.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_gpio.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of GPIO LL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_i2c.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_i2c.h
index e80fcb9b06..f0eac30e5c 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_i2c.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_i2c.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_i2c.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of I2C LL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_iwdg.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_iwdg.h
index 65d0f880cc..461e5e4ad9 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_iwdg.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_iwdg.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_iwdg.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of IWDG LL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_lptim.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_lptim.h
index 5e868eaf4e..6f18e9be57 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_lptim.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_lptim.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_lptim.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of LPTIM LL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_lpuart.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_lpuart.h
index 3365a15f1b..63503e83f4 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_lpuart.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_lpuart.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_lpuart.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of LPUART LL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_opamp.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_opamp.h
index c96410b08e..c0367d8e31 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_opamp.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_opamp.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_opamp.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of OPAMP LL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_pwr.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_pwr.h
index c3b527a369..6145e57028 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_pwr.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_pwr.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_pwr.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of PWR LL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h
index df9afb0d8a..8664961e84 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rcc.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_rcc.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of RCC LL module.
******************************************************************************
* @attention
@@ -62,8 +62,6 @@ extern "C" {
* @{
*/
-static const uint8_t aRCC_APBAHBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
-
/**
* @}
*/
@@ -1295,7 +1293,7 @@ typedef struct
* @arg @ref LL_RCC_APB1_DIV_16
* @retval PCLK1 clock frequency (in Hz)
*/
-#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> aRCC_APBAHBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
+#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
/**
* @brief Helper macro to calculate the PCLK2 frequency (ABP2)
@@ -1308,7 +1306,7 @@ typedef struct
* @arg @ref LL_RCC_APB2_DIV_16
* @retval PCLK2 clock frequency (in Hz)
*/
-#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> aRCC_APBAHBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
+#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
/**
* @brief Helper macro to calculate the MSI frequency (in Hz)
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rng.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rng.h
index 66cb558953..41447b7542 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rng.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rng.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_rng.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of RNG LL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rtc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rtc.h
index 4ee5e984c3..796452731b 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rtc.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_rtc.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_rtc.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of RTC LL module.
******************************************************************************
* @attention
@@ -614,8 +614,8 @@ typedef struct
* @{
*/
#define LL_RTC_CALIB_OUTPUT_NONE 0x00000000U /*!< Calibration output disabled */
-#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 512 Hz */
-#define LL_RTC_CALIB_OUTPUT_512HZ (RTC_CR_COE) /*!< Calibration output is 1 Hz */
+#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 1 Hz */
+#define LL_RTC_CALIB_OUTPUT_512HZ (RTC_CR_COE) /*!< Calibration output is 512 Hz */
/**
* @}
*/
@@ -1293,7 +1293,12 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24,
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)
{
- return (uint32_t)((LL_RTC_TIME_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_TIME_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_TIME_GetSecond(RTCx));
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU));
+ return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) | \
+ (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \
+ ((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos)));
}
/**
@@ -1627,7 +1632,13 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin
*/
__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx)
{
- return (uint32_t)((LL_RTC_DATE_GetWeekDay(RTCx) << RTC_OFFSET_WEEKDAY) | (LL_RTC_DATE_GetDay(RTCx) << RTC_OFFSET_DAY) | (LL_RTC_DATE_GetMonth(RTCx) << RTC_OFFSET_MONTH) | LL_RTC_DATE_GetYear(RTCx));
+ register uint32_t temp = 0U;
+
+ temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU));
+ return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \
+ (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY) | \
+ (((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \
+ ((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos)));
}
/**
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_sdmmc.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_sdmmc.h
index dc74179eb5..cf3f83e0af 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_sdmmc.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_sdmmc.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_sdmmc.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of low layer SDMMC HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_spi.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_spi.h
index 29aad2d395..54f6db7e8a 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_spi.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_spi.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_spi.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of SPI LL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_swpmi.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_swpmi.h
index 8f5d1dd8ba..34dc8482fc 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_swpmi.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_swpmi.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_swpmi.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of SWPMI LL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_system.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_system.h
index ff8b09b50f..58b2388994 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_system.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_system.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_system.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of SYSTEM LL module.
@verbatim
==============================================================================
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_tim.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_tim.h
index f1d5616423..9e7bb55244 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_tim.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_tim.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_tim.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of TIM LL module.
******************************************************************************
* @attention
@@ -1482,7 +1482,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
{
- SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
}
/**
@@ -1493,18 +1493,18 @@ __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
{
- CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
+ SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
}
/**
* @brief Indicates whether update event generation is enabled.
* @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
* @param TIMx Timer instance
- * @retval State of bit (1 or 0).
+ * @retval Inverted state of bit (0 or 1).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS));
+ return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == RESET);
}
/**
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usart.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usart.h
index 9794695cc6..f622a7424f 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usart.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usart.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_usart.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of USART LL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h
index 8666a03a52..307fa3f00e 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_usb.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of USB Core HAL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h
index 001e7cbb97..9c04998a40 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_utils.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_utils.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of UTILS LL module.
@verbatim
==============================================================================
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_wwdg.h b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_wwdg.h
index b1cff27b4f..101a6a10f8 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_wwdg.h
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_wwdg.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_wwdg.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Header file of WWDG LL module.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32L4xx_HAL_Driver/Release_Notes.html
index ea57521b9d..a7aa386828 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Release_Notes.html
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Release_Notes.html
@@ -665,7 +665,14 @@
Update History
-V1.7.1
+V1.7.2
+/ 16-June-2017
+Main
+Changes
+- Maintenance Release of HAL and Low Layer drivers
+HAL Drivers changes
+- HAL CAN driver
- Add overrun error management by the error callback
- HAL CRC driver
- Update of HAL_CRCEx_Polynomial_Set() to return an error when a non-supported polynomial length is passed as parameter
- HAL CRYP driver
- Update zero padding management with respect to data type
- Phase setting and comments correction in case of payload phase suspension
- Correct input parameters tests in HAL_CRYPEx_AES_Auth() and HAL_CRYPEx_AES_Auth_DMA() APIs
- Correct interruptions and IP enabling flags setting for key derivation in IT mode
- HAL DCMI driver
- Comments correction to describe image size management when larger than maximum authorized DMA transfer size
- HAL FLASH driver
- Add software work-around in HAL_FLASH_Unlock() to clear OPTVERR flag on STM32L45x/L46x parts when initially improperly raised
- Correct timeout issue in FLASH_WaitForLastOperation()
- HAL HASH driver
- Update of context swap mechanism implemented in HAL_HASH_DMAFeed_ProcessSuspend() when input data are fed to the IP by DMA
LL Drivers changes
+- LL RCC
- Correct duplication of aRCC_APBAHBPrescTable
- LL RTC
- Simplication of implementation of function LL_RTC_DATE_Get()
- LL TIM
- Fix LL_TIM_EnableUpdateEvent(), LL_TIM_DisableUpdateEvent() and LL_TIM_IsEnabledUpdateEvent()
V1.7.1
/ 21-April-2017
Main
Changes
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c
index bde63b0858..061a64e995 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@@ -67,11 +67,11 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/**
- * @brief STM32L4xx HAL Driver version number V1.7.1
+ * @brief STM32L4xx HAL Driver version number V1.7.2
*/
#define __STM32L4xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L4xx_HAL_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
-#define __STM32L4xx_HAL_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
+#define __STM32L4xx_HAL_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32L4xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L4xx_HAL_VERSION ((__STM32L4xx_HAL_VERSION_MAIN << 24)\
|(__STM32L4xx_HAL_VERSION_SUB1 << 16)\
@@ -579,7 +579,7 @@ void HAL_SYSCFG_DisableMemorySwappingBank(void)
* This parameter can be one of the following values:
* @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V.
* This requires VDDA equal to or higher than 2.4 V.
- * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT1 around 2.5 V.
+ * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.5 V.
* This requires VDDA equal to or higher than 2.8 V.
* @retval None
*/
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c
index 0030b19990..15572df96f 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_adc.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC)
* peripheral:
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c
index d350b0a02c..b9df9a9cef 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_adc_ex.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC)
* peripheral:
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_can.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_can.c
index bee80d1306..2f8bf443f6 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_can.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_can.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_can.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief CAN HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Controller Area Network (CAN) peripheral:
@@ -922,13 +922,13 @@ HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber
if(FIFONumber == CAN_FIFO0)
{
- /* Enable FIFO 0 message pending Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0);
+ /* Enable FIFO 0 overrun and message pending Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
}
else
{
- /* Enable FIFO 1 message pending Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1);
+ /* Enable FIFO 1 overrun and message pending Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
}
}
@@ -1056,6 +1056,30 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
*/
void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
{
+ uint32_t errorcode = HAL_CAN_ERROR_NONE;
+
+ /* Check Overrun flag for FIFO0 */
+ if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0)))
+ {
+ /* Set CAN error code to FOV0 error */
+ errorcode |= HAL_CAN_ERROR_FOV0;
+
+ /* Clear FIFO0 Overrun Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
+ }
+
+ /* Check Overrun flag for FIFO1 */
+ if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1)) &&
+ (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1)))
+ {
+ /* Set CAN error code to FOV1 error */
+ errorcode |= HAL_CAN_ERROR_FOV1;
+
+ /* Clear FIFO1 Overrun Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
+ }
+
/* Check End of transmission flag */
if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
{
@@ -1084,6 +1108,9 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
CAN_Receive_IT(hcan, CAN_FIFO1);
}
+ /* Set error code in handle */
+ hcan->ErrorCode |= errorcode;
+
/* Check Error Warning Flag */
if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG)) &&
(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG)) &&
@@ -1158,8 +1185,32 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
{
/* Clear ERRI bit */
SET_BIT(hcan->Instance->MSR, CAN_MSR_ERRI);
+
/* Set the CAN state ready to be able to start again the process */
hcan->State = HAL_CAN_STATE_READY;
+
+ /* Disable interrupts: */
+ /* - Disable Error warning Interrupt */
+ /* - Disable Error passive Interrupt */
+ /* - Disable Bus-off Interrupt */
+ /* - Disable Last error code Interrupt */
+ /* - Disable Error Interrupt */
+ /* - Disable FIFO 0 message pending Interrupt */
+ /* - Disable FIFO 0 Overrun Interrupt */
+ /* - Disable FIFO 1 message pending Interrupt */
+ /* - Disable FIFO 1 Overrun Interrupt */
+ /* - Disable Transmit mailbox empty Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR |
+ CAN_IT_FMP0|
+ CAN_IT_FOV0|
+ CAN_IT_FMP1|
+ CAN_IT_FOV1|
+ CAN_IT_TME );
+
/* Call Error callback function */
HAL_CAN_ErrorCallback(hcan);
}
@@ -1350,16 +1401,16 @@ static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONum
{
__HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
- /* Disable FIFO 0 message pending Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0);
+ /* Disable FIFO 0 overrun and message pending Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
}
/* Release FIFO1 */
else /* FIFONumber == CAN_FIFO1 */
{
__HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
- /* Disable FIFO 1 message pending Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1);
+ /* Disable FIFO 1 overrun and message pending Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
}
if(hcan->State == HAL_CAN_STATE_BUSY_RX)
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_comp.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_comp.c
index 53a0993cfb..2d93640031 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_comp.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_comp.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_comp.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief COMP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the COMP peripheral:
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c
index 475c564f3f..d6f12e930a 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_cortex.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc.c
index a27668de94..82e6b8a251 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_crc.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief CRC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CRC peripheral:
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc_ex.c
index 3ba25900bb..a8570a5d45 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc_ex.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_crc_ex.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Extended CRC HAL module driver.
* This file provides firmware functions to manage the extended
* functionalities of the CRC peripheral.
@@ -144,7 +144,7 @@ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol
/* no polynomial definition vs. polynomial length issue possible */
break;
default:
- break;
+ return HAL_ERROR;
}
/* set generating polynomial */
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp.c
index 5bafd1af68..8c7368411f 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_cryp.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief CRYP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cryptography (CRYP) peripheral:
@@ -372,8 +372,12 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
+ if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION)
+ {
/* Enable the Peripheral */
__HAL_CRYP_ENABLE(hcryp);
+ }
+ /* else, enable IP in processing function */
/* Return function status */
return HAL_OK;
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp_ex.c
index a92140a609..6dd1b8183a 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp_ex.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_cryp_ex.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief CRYPEx HAL module driver.
* This file provides firmware functions to manage the extended
* functionalities of the Cryptography (CRYP) peripheral.
@@ -189,6 +189,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData,
/* Check parameters setting */
if (hcryp->Init.OperatingMode == CRYP_ALGOMODE_KEYDERIVATION)
{
+ /* Enable IP at this point, since not enabled in HAL_CRYP_Init() */
+ __HAL_CRYP_ENABLE(hcryp);
if (pOutputData == NULL)
{
return HAL_ERROR;
@@ -308,8 +310,16 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pInputD
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
+ if (hcryp->Init.OperatingMode != CRYP_ALGOMODE_KEYDERIVATION)
+ {
/* Enable Computation Complete Flag and Error Interrupts */
__HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE);
+ }
+ else
+ {
+ /* In the case of Key derivation, enable the IP at the same time as the interruptions */
+ SET_BIT(hcryp->Instance->CR, CRYP_IT_CCFIE|CRYP_IT_ERRIE|AES_CR_EN);
+ }
/* If operating mode is key derivation only, the input data have
@@ -484,7 +494,9 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth(CRYP_HandleTypeDef *hcryp, uint8_t *pInput
}
else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)
{
- if ((pInputData == NULL) || (pOutputData == NULL) || (Size == 0))
+ if (((pInputData == NULL) && (Size != 0)) || \
+ ((pInputData != NULL) && (Size == 0)) || \
+ ((pInputData != NULL) && (Size != 0) && (pOutputData == NULL)))
{
return HAL_ERROR;
}
@@ -950,7 +962,11 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn
uint32_t addhoc_process = 0;
uint32_t difflength = 0;
uint32_t difflengthmod4 = 0;
- uint32_t mask[3] = {0x0FF, 0x0FFFF, 0x0FFFFFF};
+ uint32_t mask[4][3] = { {0xFF000000, 0xFFFF0000, 0xFFFFFF00}, /* 32-bit data */
+ {0x0000FF00, 0x0000FFFF, 0xFF00FFFF}, /* 16-bit data */
+ {0x000000FF, 0x0000FFFF, 0x00FFFFFF}, /* 8-bit data */
+ {0x000000FF, 0x0000FFFF, 0x00FFFFFF}}; /* Bit data */
+ uint32_t mask_index = hcryp->Init.DataType >> AES_CR_DATATYPE_Pos;
if (hcryp->State == HAL_CRYP_STATE_READY)
@@ -1141,7 +1157,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn
(case of header length not a multiple of 32-bits) */
if (difflengthmod4 != 0)
{
- hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]);
+ hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1]);
}
/* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */
for(index=0; index < (4 - ((difflength+3)/4)); index ++)
@@ -1230,7 +1246,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pIn
/* If required, manage input data size not multiple of 32 bits */
if (difflengthmod4 != 0)
{
- hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]);
+ hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1]);
}
/* Wrap-up in padding with zero-words if applicable */
for(index=0; index < (4 - ((difflength+3)/4)); index ++)
@@ -1404,15 +1420,22 @@ HAL_StatusTypeDef HAL_CRYPEx_AES_Auth_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pI
}
#if defined(AES_CR_NPBLB)
if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CCM)
+ {
+ /* In case of CMAC or CCM header phase resumption, we can have pInputData = NULL and Size = 0 */
+ if (((pInputData != NULL) && (Size == 0)) || ((pInputData == NULL) && (Size != 0)))
+ {
+ return HAL_ERROR;
+ }
+ }
#else
if (hcryp->Init.ChainingMode == CRYP_CHAINMODE_AES_CMAC)
-#endif
{
if ((pInputData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
}
+#endif
}
else if (hcryp->Init.GCMCMACPhase == CRYP_PAYLOAD_PHASE)
{
@@ -2186,7 +2209,11 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp)
uint32_t addhoc_process = 0;
uint32_t difflength = 0;
uint32_t difflengthmod4 = 0;
- uint32_t mask[3] = {0x0FF, 0x0FFFF, 0x0FFFFFF};
+ uint32_t mask[4][3] = { {0xFF000000, 0xFFFF0000, 0xFFFFFF00}, /* 32-bit data */
+ {0x0000FF00, 0x0000FFFF, 0xFF00FFFF}, /* 16-bit data */
+ {0x000000FF, 0x0000FFFF, 0x00FFFFFF}, /* 8-bit data */
+ {0x000000FF, 0x0000FFFF, 0x00FFFFFF}}; /* Bit data */
+ uint32_t mask_index = hcryp->Init.DataType >> AES_CR_DATATYPE_Pos;
uint32_t intermediate_data[4] = {0};
if(hcryp->State == HAL_CRYP_STATE_BUSY)
@@ -2249,7 +2276,7 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp)
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE);
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_SUSPENDED;
- /* Mark that the header phase is over */
+ /* Mark that the header phase is suspended */
hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED;
/* Process Unlocked */
@@ -2318,7 +2345,7 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp)
(case of header length not a multiple of 32-bits) */
if (difflengthmod4 != 0)
{
- hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]);
+ hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1]);
}
/* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */
for(index=0; index < (4 - ((difflength+3)/4)); index ++)
@@ -2372,7 +2399,7 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp)
applied to the last block of payload */
if (difflengthmod4 != 0)
{
- intermediate_data[difflength/4] &= mask[difflengthmod4-1];
+ intermediate_data[difflength/4] &= mask[mask_index][difflengthmod4-1];
*(uint32_t*)(outputaddr) = intermediate_data[difflength/4];
}
@@ -2484,8 +2511,8 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp)
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE|CRYP_IT_ERRIE);
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_SUSPENDED;
- /* Mark that the header phase is over */
- hcryp->Phase = HAL_CRYP_PHASE_HEADER_SUSPENDED;
+ /* Mark that the payload phase is suspended */
+ hcryp->Phase = HAL_CRYP_PHASE_PAYLOAD_SUSPENDED;
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
@@ -2539,7 +2566,7 @@ HAL_StatusTypeDef CRYP_AES_Auth_IT(CRYP_HandleTypeDef *hcryp)
/* If required, manage input data size not multiple of 32 bits */
if (difflengthmod4 != 0)
{
- hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]);
+ hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1]);
}
/* Wrap-up in padding with zero-words if applicable */
for(index=0; index < (4 - ((difflength+3)/4)); index ++)
@@ -2964,7 +2991,12 @@ static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_
uint32_t difflengthmod4 = difflength%4;
uint32_t inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
uint32_t outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
- uint32_t mask[3] = {0x0FF, 0x0FFFF, 0x0FFFFFF};
+ uint32_t mask[4][3] = { {0xFF000000, 0xFFFF0000, 0xFFFFFF00}, /* 32-bit data */
+ {0x0000FF00, 0x0000FFFF, 0xFF00FFFF}, /* 16-bit data */
+ {0x000000FF, 0x0000FFFF, 0x00FFFFFF}, /* 8-bit data */
+ {0x000000FF, 0x0000FFFF, 0x00FFFFFF}}; /* Bit data */
+ uint32_t mask_index = hcryp->Init.DataType >> AES_CR_DATATYPE_Pos;
+
uint32_t intermediate_data[4] = {0};
#if defined(AES_CR_NPBLB)
@@ -3004,7 +3036,7 @@ static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_
(case of header length not a multiple of 32-bits) */
if (difflengthmod4 != 0)
{
- hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[difflengthmod4-1]);
+ hcryp->Instance->DINR = ((*(uint32_t*)(inputaddr)) & mask[mask_index][difflengthmod4-1]);
}
/* Pad with zero-words to reach 128-bit long block and wrap-up header feeding to the IP */
for(index=0; index < (4 - ((difflength+3)/4)); index ++)
@@ -3047,7 +3079,7 @@ static void CRYP_Padding(CRYP_HandleTypeDef *hcryp, uint32_t difflength, uint32_
applied to the last block of payload */
if (difflengthmod4 != 0)
{
- intermediate_data[difflength/4] &= mask[difflengthmod4-1];
+ intermediate_data[difflength/4] &= mask[mask_index][difflengthmod4-1];
*(uint32_t*)(outputaddr) = intermediate_data[difflength/4];
}
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac.c
index 605d97d6db..0a6308fef1 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_dac.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Digital to Analog Converter (DAC) peripheral:
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac_ex.c
index 07a743d00a..422a0253ad 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac_ex.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_dac_ex.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the extended
* functionalities of the DAC peripheral.
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dcmi.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dcmi.c
index 850568b014..79ad05720b 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dcmi.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dcmi.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_dcmi.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief DCMI HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the Digital Camera Interface (DCMI) peripheral:
@@ -51,12 +51,10 @@
be large enough to ensure the capture of a frame.
(#) If the frame size is larger than the maximum DMA transfer length (i.e. 65535),
- (++) resort to a user-defined work buffer and associate it to the DCMI handle with
- the function HAL_DCMIEx_WorkBuffer_Associate(),
(++) the DMA must be configured in circular mode, either for snapshot or continuous
capture mode,
(++) during capture, the driver copies the image data samples from DCMI DR register
- to the work buffer,
+ at the end of the final destination buffer used as a work buffer,
(++) at each DMA half (respectively complete) transfer interrupt, the first
(resp. second) half of the work buffer is copied to the final destination thru
a second DMA channel.
@@ -417,9 +415,8 @@ __weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)
* @param pData: The destination memory buffer address.
* @param Length: The length of capture to be transferred (in 32-bit words).
* @note In case of length larger than 65535 (0xFFFF is the DMA maximum transfer length),
- * user must beforehand associate a work buffer to the DCMI handle thru the API
- * HAL_DCMIEx_WorkBuffer_Associate(). Then, HAL_DCMI_Start_DMA()
- * initiates a circular DMA transfer from DCMI DR to the work buffer and each
+ * the API uses the end of the destination buffer as a work area: HAL_DCMI_Start_DMA()
+ * initiates a circular DMA transfer from DCMI DR to the ad-hoc work buffer and each
* half and complete transfer interrupt triggers a copy from the work buffer to
* the final destination pData thru a second DMA channel.
* @note Following HAL_DCMI_Init() call, all interruptions are enabled (line end,
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm.c
index dd5dcf19a6..e6ce0d0492 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_dfsdm.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief This file provides firmware functions to manage the following
* functionalities of the Digital Filter for Sigma-Delta Modulators
* (DFSDM) peripherals:
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c
index 67ee062427..068f2cc467 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_dma.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief DMA HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Direct Memory Access (DMA) peripheral:
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma2d.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma2d.c
index 18430aac0a..401e61c0ef 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma2d.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma2d.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_dma2d.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief DMA2D HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the DMA2D peripheral:
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_firewall.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_firewall.c
index 4db28f34e1..57737a9f7c 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_firewall.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_firewall.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_firewall.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief FIREWALL HAL module driver.
* This file provides firmware functions to manage the Firewall
* Peripheral initialization and enabling.
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c
index a3fc9b3218..fbd30ebbe7 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_flash.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
@@ -500,6 +500,12 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
*/
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
{
+
+#if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
+ /* Clear OPTVERR bit when initially improperly raised */
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
+#endif
+
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
{
/* Authorize the FLASH Registers access */
@@ -642,13 +648,13 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
Even if the FLASH operation fails, the BUSY flag will be reset and an error
flag will be set */
- uint32_t timeout = HAL_GetTick() + Timeout;
+ uint32_t tickstart = HAL_GetTick();
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
{
if(Timeout != HAL_MAX_DELAY)
{
- if(HAL_GetTick() >= timeout)
+ if((HAL_GetTick() - tickstart) >= Timeout)
{
return HAL_TIMEOUT;
}
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c
index 3fb9f96d78..2827b45abd 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_flash_ex.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Extended FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the FLASH extended peripheral:
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c
index 94405bedb6..b289b62e66 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_flash_ramfunc.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief FLASH RAMFUNC driver.
* This file provides a Flash firmware functions which should be
* executed from internal SRAM
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c
index 0a6896419f..a46b865a37 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_gpio.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash.c
index 241a327694..473df1f21a 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_hash.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief HASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the HASH peripheral:
@@ -182,6 +182,14 @@
* @}
*/
+/** @defgroup HASH_DMA_Suspension_Words_Limit HASH DMA suspension words limit
+ * @{
+ */
+#define HASH_DMA_SUSPENSION_WORDS_LIMIT 20 /*!< Number of words below which DMA suspension is aborted */
+/**
+ * @}
+ */
+
/**
* @}
*/
@@ -1083,9 +1091,32 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
}
else
{
- /* Set State as suspended (it may be required to update it if suspension failed).
- The context saving operations must be carried out to be able to resume later on. */
- hhash->State = HAL_HASH_STATE_SUSPENDED;
+
+ /* Make sure there is enough time to suspend the processing */
+ tmp_remaining_DMATransferSize_inWords = hhash->hdmain->Instance->CNDTR;
+ if (tmp_remaining_DMATransferSize_inWords <= HASH_DMA_SUSPENSION_WORDS_LIMIT)
+ {
+ /* No suspension attempted since almost to the end of the transferred data. */
+ /* Best option for user code is to wrap up low priority message hashing */
+ return HAL_ERROR;
+ }
+
+ /* Wait for DMAS to be reset */
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS) != RESET)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Wait for DMAS to be set */
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, RESET, HASH_TIMEOUTVALUE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
/* Disable DMA channel */
HAL_DMA_Abort(hhash->hdmain);
@@ -1093,6 +1124,16 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
/* Clear DMAE bit */
CLEAR_BIT(HASH->CR,HASH_CR_DMAE);
+ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+
+ if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS) != RESET)
+ {
+ return HAL_ERROR;
+ }
+
/* At this point, DMA interface is disabled and no transfer is on-going */
/* Retrieve from the DMA handle how many words remain to be written */
tmp_remaining_DMATransferSize_inWords = hhash->hdmain->Instance->CNDTR;
@@ -1108,7 +1149,6 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
priority block processing (HASH case)
- re-attempt a new suspension (HMAC case)
*/
- hhash->State = HAL_HASH_STATE_READY;
return HAL_ERROR;
}
else
@@ -1126,6 +1166,7 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
{
tmp_remaining_DMATransferSize_inWords--; /* one less word to be transferred again */
}
+
/* Accordingly, update the input pointer that points at the next word to be transferred to the IP by DMA */
hhash->pHashInBuffPtr += 4 * (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ;
@@ -1134,6 +1175,9 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
}
+ /* Set State as suspended */
+ hhash->State = HAL_HASH_STATE_SUSPENDED;
+
return HAL_OK;
}
@@ -2250,6 +2294,7 @@ HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer,
processing was suspended */
inputaddr = (uint32_t)hhash->pHashInBuffPtr; /* DMA transfer start address */
inputSize = hhash->HashInCount; /* DMA transfer size (in bytes) */
+
}
/* Set the HASH DMA transfert complete callback */
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash_ex.c
index 7bbbe6c1ca..8ef188d381 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash_ex.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_hash_ex.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Extended HASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the HASH peripheral for SHA-224 and SHA-256
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hcd.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hcd.c
index c1f094329e..51df52a7b4 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hcd.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hcd.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_hcd.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief HCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c
index df2c8ebac9..966c56f2e7 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_i2c.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief I2C HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Inter Integrated Circuit (I2C) peripheral:
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c
index c4432eaf37..0468909f03 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_i2c_ex.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief I2C Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2C Extended peripheral:
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_irda.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_irda.c
index 09c719ad24..9a943a7455 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_irda.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_irda.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_irda.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief IRDA HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the IrDA (Infrared Data Association) Peripheral
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c
index a5051a3048..886021a540 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_iwdg.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief IWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Independent Watchdog (IWDG) peripheral:
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lcd.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lcd.c
index 5d138939f2..ff653b349f 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lcd.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lcd.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_lcd.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief LCD Controller HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the LCD Controller (LCD) peripheral:
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lptim.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lptim.c
index 33ae36b4e1..7892c2e3a4 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lptim.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lptim.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_lptim.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief LPTIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Low Power Timer (LPTIM) peripheral:
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_msp_template.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_msp_template.c
index 8c3418faf9..6748abfbc2 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_msp_template.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_msp_template.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_msp_template.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief HAL MSP module.
* This file template is located in the HAL folder and should be copied
* to the user folder.
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_nand.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_nand.c
index 72add9df4a..8075b23c8e 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_nand.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_nand.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_nand.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief NAND HAL module driver.
* This file provides a generic firmware to drive NAND memories mounted
* as external device.
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_nor.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_nor.c
index bced324dd0..9a3836b159 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_nor.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_nor.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_nor.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief NOR HAL module driver.
* This file provides a generic firmware to drive NOR memories mounted
* as external device.
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_opamp.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_opamp.c
index 8567220183..bb2215911d 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_opamp.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_opamp.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_opamp.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief OPAMP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the operational amplifier(s) peripheral:
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_opamp_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_opamp_ex.c
index 39fb8dfbb4..98ee4096e2 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_opamp_ex.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_opamp_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_opamp_ex.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Extended OPAMP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc)
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c
index b4af31c6b6..02d920787f 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_pcd.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c
index 11ed8945f4..5151c502ea 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_pcd_ex.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief PCD Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c
index 6283c13f9d..64472b82a0 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_pwr.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c
index 4d0de77150..996df7eced 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_pwr_ex.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Extended PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c
index 33bf7cf9e7..6f83efd237 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_qspi.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief QSPI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the QuadSPI interface (QSPI).
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c
index a639ddafa3..6faa041c26 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_rcc.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Reset and Clock Control (RCC) peripheral:
@@ -382,7 +382,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
/* Update the SystemCoreClock global variable */
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
+ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (TICK_INT_PRIORITY);
@@ -997,7 +997,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
}
/* Update the SystemCoreClock global variable */
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
+ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (TICK_INT_PRIORITY);
@@ -1123,11 +1123,11 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
/* Get SYSCLK source */
if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == RESET)
{ /* MSISRANGE from RCC_CSR applies */
- msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> POSITION_VAL(RCC_CSR_MSISRANGE);
+ msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos;
}
else
{ /* MSIRANGE from RCC_CR applies */
- msirange = (RCC->CR & RCC_CR_MSIRANGE) >> POSITION_VAL(RCC_CR_MSIRANGE);
+ msirange = (RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos;
}
/*MSI frequency range in HZ*/
msirange = MSIRangeTable[msirange];
@@ -1157,24 +1157,24 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
SYSCLK = PLL_VCO / PLLR
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
- pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U ;
+ pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
switch (pllsource)
{
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
- pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
+ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
break;
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
- pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
+ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
break;
case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
default:
- pllvco = (msirange / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
+ pllvco = (msirange / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
break;
}
- pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR)) + 1U ) * 2U;
+ pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
sysclockfreq = pllvco/pllr;
}
@@ -1203,7 +1203,7 @@ uint32_t HAL_RCC_GetHCLKFreq(void)
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
+ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
}
/**
@@ -1215,7 +1215,7 @@ uint32_t HAL_RCC_GetPCLK1Freq(void)
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
+ return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
}
/**
@@ -1263,7 +1263,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_OscInitStruct->MSIState = RCC_MSI_OFF;
}
- RCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_MSITRIM) >> POSITION_VAL(RCC_ICSCR_MSITRIM));
+ RCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos);
RCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->CR & RCC_CR_MSIRANGE) );
/* Get the HSI configuration -----------------------------------------------*/
@@ -1276,7 +1276,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
}
- RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_HSITRIM) >> POSITION_VAL(RCC_ICSCR_HSITRIM));
+ RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
/* Get the LSE configuration -----------------------------------------------*/
if((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
@@ -1326,12 +1326,12 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
}
RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
- RCC_OscInitStruct->PLL.PLLM = (uint32_t)(((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U);
- RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
- RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ)) + 1U) << 1U);
- RCC_OscInitStruct->PLL.PLLR = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR)) + 1U) << 1U);
+ RCC_OscInitStruct->PLL.PLLM = (uint32_t)(((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U);
+ RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+ RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U);
+ RCC_OscInitStruct->PLL.PLLR = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U) << 1U);
#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
- RCC_OscInitStruct->PLL.PLLP = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLPDIV) >> POSITION_VAL(RCC_PLLCFGR_PLLPDIV));
+ RCC_OscInitStruct->PLL.PLLP = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos);
#else
if((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) != RESET)
{
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c
index 1ce897d370..2c0fdabfa4 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_rcc_ex.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Extended RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities RCC extended peripheral:
@@ -754,12 +754,12 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
/* Get the PLLSAI1 Clock configuration -----------------------------------------------*/
- PeriphClkInit->PLLSAI1.PLLSAI1Source = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC));
- PeriphClkInit->PLLSAI1.PLLSAI1M = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U;
- PeriphClkInit->PLLSAI1.PLLSAI1N = (uint32_t)((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N));
- PeriphClkInit->PLLSAI1.PLLSAI1P = (uint32_t)(((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1P) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)) << 4U) + 7U;
- PeriphClkInit->PLLSAI1.PLLSAI1Q = (uint32_t)(((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1Q) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q))+1U) * 2U;
- PeriphClkInit->PLLSAI1.PLLSAI1R = (uint32_t)(((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1R) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R))+1U) * 2U;
+ PeriphClkInit->PLLSAI1.PLLSAI1Source = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> RCC_PLLCFGR_PLLSRC_Pos);
+ PeriphClkInit->PLLSAI1.PLLSAI1M = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U;
+ PeriphClkInit->PLLSAI1.PLLSAI1N = (uint32_t)((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos);
+ PeriphClkInit->PLLSAI1.PLLSAI1P = (uint32_t)(((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1P) >> RCC_PLLSAI1CFGR_PLLSAI1P_Pos) << 4U) + 7U;
+ PeriphClkInit->PLLSAI1.PLLSAI1Q = (uint32_t)(((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)+1U) * 2U;
+ PeriphClkInit->PLLSAI1.PLLSAI1R = (uint32_t)(((RCC->PLLSAI1CFGR & RCC_PLLSAI1CFGR_PLLSAI1R) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos)+1U) * 2U;
#if defined(RCC_PLLSAI2_SUPPORT)
@@ -767,9 +767,9 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
PeriphClkInit->PLLSAI2.PLLSAI2Source = PeriphClkInit->PLLSAI1.PLLSAI1Source;
PeriphClkInit->PLLSAI2.PLLSAI2M = PeriphClkInit->PLLSAI1.PLLSAI1M;
- PeriphClkInit->PLLSAI2.PLLSAI2N = (uint32_t)((RCC->PLLSAI2CFGR & RCC_PLLSAI2CFGR_PLLSAI2N) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N));
- PeriphClkInit->PLLSAI2.PLLSAI2P = (uint32_t)(((RCC->PLLSAI2CFGR & RCC_PLLSAI2CFGR_PLLSAI2P) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)) << 4U) + 7U;
- PeriphClkInit->PLLSAI2.PLLSAI2R = (uint32_t)(((RCC->PLLSAI2CFGR & RCC_PLLSAI2CFGR_PLLSAI2R)>> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R))+1U) * 2U;
+PeriphClkInit->PLLSAI2.PLLSAI2N = (uint32_t)((RCC->PLLSAI2CFGR & RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos);
+ PeriphClkInit->PLLSAI2.PLLSAI2P = (uint32_t)(((RCC->PLLSAI2CFGR & RCC_PLLSAI2CFGR_PLLSAI2P) >> RCC_PLLSAI2CFGR_PLLSAI2P_Pos) << 4U) + 7U;
+ PeriphClkInit->PLLSAI2.PLLSAI2R = (uint32_t)(((RCC->PLLSAI2CFGR & RCC_PLLSAI2CFGR_PLLSAI2R)>> RCC_PLLSAI2CFGR_PLLSAI2R_Pos)+1U) * 2U;
#endif /* RCC_PLLSAI2_SUPPORT */
@@ -999,7 +999,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
}
/* f(PLL Source) / PLLM */
- pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U));
+ pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U));
switch(PeriphClk)
{
@@ -1054,9 +1054,9 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI3CLK) != RESET)
{
/* f(PLLSAI3CLK) = f(VCO input) * PLLN / PLLP */
- plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN);
+ plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
- pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> POSITION_VAL(RCC_PLLCFGR_PLLPDIV);
+ pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;
#endif
if(pllp == 0U)
{
@@ -1077,9 +1077,9 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != RESET)
{
/* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */
- plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N);
+ plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;
#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
- pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV);
+ pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos;
#endif
if(pllp == 0U)
{
@@ -1101,9 +1101,9 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
if(__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL_SAI2CLK) != RESET)
{
/* f(PLLSAI2CLK) = f(VCO input) * PLLN / PLLP */
- plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN);
+ plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
- pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> POSITION_VAL(RCC_PLLCFGR_PLLPDIV);
+ pllp = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) >> RCC_PLLCFGR_PLLPDIV_Pos;
#endif
if(pllp == 0U)
{
@@ -1135,9 +1135,9 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_SAI1CLK) != RESET)
{
/* f(PLLSAI1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1P */
- plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N);
+ plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;
#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
- pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV);
+ pllp = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos;
#endif
if(pllp == 0U)
{
@@ -1173,7 +1173,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_SAI2CLK) != RESET)
{
/* f(PLLSAI2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2P */
- plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N);
+ plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos;
if(pllp == 0U)
{
if(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P) != RESET)
@@ -1232,8 +1232,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY) && HAL_IS_BIT_SET(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN))
{
/* f(PLL48M1CLK) = f(VCO input) * PLLN / PLLQ */
- plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN);
- frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ)) + 1U) << 1U);
+ plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos;
+ frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U);
}
else
{
@@ -1245,8 +1245,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
if(HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLSAI1RDY) && HAL_IS_BIT_SET(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN))
{
/* f(PLL48M2CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1Q */
- plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N);
- frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)) + 1U) << 1U);
+ plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;
+ frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U);
}
else
{
@@ -1457,8 +1457,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
if(__HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(RCC_PLLSAI1_ADC1CLK) != RESET)
{
/* f(PLLADC1CLK) = f(VCOSAI1 input) * PLLSAI1N / PLLSAI1R */
- plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N);
- frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)) + 1U) << 1U);
+ plln = READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos;
+ frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U);
}
}
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
@@ -1467,8 +1467,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
if(__HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(RCC_PLLSAI2_ADC2CLK) != RESET)
{
/* f(PLLADC2CLK) = f(VCOSAI2 input) * PLLSAI2N / PLLSAI2R */
- plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N);
- frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R) >> POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)) + 1U) << 1U);
+ plln = READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos;
+ frequency = (pllvco * plln) / (((READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos) + 1U) << 1U);
}
}
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || STM32L496xx || STM32L4A6xx */
@@ -2228,12 +2228,12 @@ void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
/* Set the RELOAD[15:0] bits according to ReloadValue value */
value |= pInit->ReloadValue;
/* Set the FELIM[7:0] bits according to ErrorLimitValue value */
- value |= (pInit->ErrorLimitValue << POSITION_VAL(CRS_CFGR_FELIM));
+ value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);
WRITE_REG(CRS->CFGR, value);
/* Adjust HSI48 oscillator smooth trimming */
/* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
- MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << POSITION_VAL(CRS_CR_TRIM)));
+ MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));
/* START AUTOMATIC SYNCHRONIZATION*/
@@ -2264,10 +2264,10 @@ void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo
pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
/* Get HSI48 oscillator smooth trimming */
- pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> POSITION_VAL(CRS_CR_TRIM));
+ pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
/* Get Frequency error capture */
- pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> POSITION_VAL(CRS_ISR_FECAP));
+ pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
/* Get Frequency error direction */
pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
@@ -2528,7 +2528,7 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, u
||
(PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE)
||
- (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U) != PllSai1->PLLSAI1M)
+ (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai1->PLLSAI1M)
)
{
status = HAL_ERROR;
@@ -2565,7 +2565,7 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, u
if(status == HAL_OK)
{
/* Set PLLSAI1 clock source and divider M */
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << POSITION_VAL(RCC_PLLCFGR_PLLM));
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << RCC_PLLCFGR_PLLM_Pos);
}
}
@@ -2596,13 +2596,13 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, u
#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
MODIFY_REG(RCC->PLLSAI1CFGR,
RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
- (PllSai1->PLLSAI1N << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) |
- (PllSai1->PLLSAI1P << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1PDIV)));
+ (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
+ (PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos));
#else
MODIFY_REG(RCC->PLLSAI1CFGR,
RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P,
- (PllSai1->PLLSAI1N << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) |
- ((PllSai1->PLLSAI1P >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P)));
+ (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
+ ((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos));
#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
}
else if(Divider == DIVIDER_Q_UPDATE)
@@ -2611,8 +2611,8 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, u
/* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/
MODIFY_REG(RCC->PLLSAI1CFGR,
RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1Q,
- (PllSai1->PLLSAI1N << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) |
- (((PllSai1->PLLSAI1Q >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1Q)));
+ (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
+ (((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos));
}
else
{
@@ -2620,8 +2620,8 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, u
/* Configure the PLLSAI1 Division factor R and Multiplication factor N*/
MODIFY_REG(RCC->PLLSAI1CFGR,
RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1R,
- (PllSai1->PLLSAI1N << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) |
- (((PllSai1->PLLSAI1R >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R)));
+ (PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
+ (((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos));
}
/* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
@@ -2683,7 +2683,7 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u
||
(PllSai2->PLLSAI2Source == RCC_PLLSOURCE_NONE)
||
- (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U) != PllSai2->PLLSAI2M)
+ (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai2->PLLSAI2M)
)
{
status = HAL_ERROR;
@@ -2720,7 +2720,7 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u
if(status == HAL_OK)
{
/* Set PLLSAI2 clock source and divider M */
- MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai2->PLLSAI2Source | (PllSai2->PLLSAI2M - 1U) << POSITION_VAL(RCC_PLLCFGR_PLLM));
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai2->PLLSAI2Source | (PllSai2->PLLSAI2M - 1U) << RCC_PLLCFGR_PLLM_Pos);
}
}
@@ -2750,8 +2750,8 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u
/* Configure the PLLSAI2 Division factor P and Multiplication factor N*/
MODIFY_REG(RCC->PLLSAI2CFGR,
RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2P,
- (PllSai2->PLLSAI2N << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) |
- ((PllSai2->PLLSAI2P >> 4U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2P)));
+ (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
+ ((PllSai2->PLLSAI2P >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos));
}
else
{
@@ -2759,8 +2759,8 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, u
/* Configure the PLLSAI2 Division factor R and Multiplication factor N*/
MODIFY_REG(RCC->PLLSAI2CFGR,
RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2R,
- (PllSai2->PLLSAI2N << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)) |
- (((PllSai2->PLLSAI2R >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2R)));
+ (PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
+ (((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos));
}
/* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.c
index b5b4ef9b48..082c829100 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_rng.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief RNG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Random Number Generator (RNG) peripheral:
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c
index 31639be862..d7425e9aa9 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_rtc.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real-Time Clock (RTC) peripheral:
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c
index f9bf4a7055..3d146419bc 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_rtc_ex.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Extended RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) Extended peripheral:
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c
index a4f9a885bc..14572d440d 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_sai.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief SAI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Serial Audio Interface (SAI) peripheral:
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c
index bd68f49ad7..d51bcf8b30 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_sd.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief SD card HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Secure Digital (SD) peripheral:
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard.c
index d08920a73e..d80062896b 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_smartcard.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief SMARTCARD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the SMARTCARD peripheral:
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard_ex.c
index 6a4a8eb7d3..94f4c1297e 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard_ex.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_smartcard_ex.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief SMARTCARD HAL module driver.
* This file provides extended firmware functions to manage the following
* functionalities of the SmartCard.
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smbus.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smbus.c
index 39efe88cbf..8350969d85 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smbus.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smbus.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_smbus.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief SMBUS HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the System Management Bus (SMBus) peripheral,
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c
index fc59d4675b..39ff61f423 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_spi.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief SPI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Serial Peripheral Interface (SPI) peripheral:
@@ -1630,7 +1630,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/* check tx dma handle */
assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
-
+
/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
}
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c
index 7b82642662..6a13aa896c 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_spi_ex.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Extended SPI HAL module driver.
* This file provides firmware functions to manage the following
* SPI peripheral extended functionalities :
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sram.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sram.c
index 5d9e99b1e7..e33c56e014 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sram.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sram.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_sram.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief SRAM HAL module driver.
* This file provides a generic firmware to drive SRAM memories
* mounted as external device.
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_swpmi.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_swpmi.c
index fa7e7fdb50..eef7e0410a 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_swpmi.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_swpmi.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_swpmi.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief SWPMI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Single Wire Protocol Master Interface (SWPMI).
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c
index c1da7a9af7..7c515a18b1 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_tim.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer (TIM) peripheral:
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c
index 0b74eeaf39..df10ae7903 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_tim_ex.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer Extended peripheral:
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_timebase_tim_template.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_timebase_tim_template.c
index baa806d084..7d1c35d3b5 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_timebase_tim_template.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_timebase_tim_template.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_timebase_tim_template.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief HAL time base based on the hardware TIM Template.
*
* This file override the native HAL time base functions (defined as weak)
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tsc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tsc.c
index bb359f054a..87b70370cd 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tsc.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tsc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_tsc.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief This file provides firmware functions to manage the following
* functionalities of the Touch Sensing Controller (TSC) peripheral:
* + Initialization and De-initialization
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c
index 85bdb36a71..1a63cdb6cb 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_uart.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief UART HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c
index 10f04a4f0a..c542d4ab8f 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_uart_ex.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief Extended UART HAL module driver.
* This file provides firmware functions to manage the following extended
* functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart.c
index 2994277bf7..27af8852d7 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_usart.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief USART HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_wwdg.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_wwdg.c
index 89d15d31d8..1cf1bdc342 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_wwdg.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_wwdg.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_hal_wwdg.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief WWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Window Watchdog (WWDG) peripheral:
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_adc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_adc.c
index fbe5bab374..7d5d8288ef 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_adc.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_adc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_adc.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief ADC LL module driver
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_comp.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_comp.c
index ff30c68a41..c167cf5149 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_comp.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_comp.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_comp.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief COMP LL module driver
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_crc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_crc.c
index 707be5940e..8c79156d2a 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_crc.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_crc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_crc.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief CRC LL module driver.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_crs.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_crs.c
index 4183dd35b5..c3fb3e5caf 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_crs.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_crs.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_crs.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief CRS LL module driver.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dac.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dac.c
index abfa7fabb2..d63f830eed 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dac.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dac.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_dac.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief DAC LL module driver
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dma.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dma.c
index 23d9b153c5..74d77c0012 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dma.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dma.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_dma.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief DMA LL module driver.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dma2d.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dma2d.c
index cb972ae9d3..ea3ca423bf 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dma2d.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dma2d.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_dma2d.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief DMA2D LL module driver.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_exti.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_exti.c
index 2125f66d3e..0ed3b46830 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_exti.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_exti.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_exti.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief EXTI LL module driver.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_fmc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_fmc.c
index 2932dfdd55..ca400a1cae 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_fmc.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_fmc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_fmc.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief FMC Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_gpio.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_gpio.c
index 1d201fb76a..ff0abe794a 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_gpio.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_gpio.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_gpio.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief GPIO LL module driver.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_i2c.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_i2c.c
index 5200dc021c..f9674583c1 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_i2c.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_i2c.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_i2c.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief I2C LL module driver.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_lptim.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_lptim.c
index 41d2184c74..77677b07b8 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_lptim.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_lptim.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_lptim.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief LPTIM LL module driver.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_lpuart.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_lpuart.c
index 0bc4ffc218..9ed6b6cd24 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_lpuart.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_lpuart.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_lpuart.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief LPUART LL module driver.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_opamp.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_opamp.c
index 202e386bc8..8f22ebf4b4 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_opamp.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_opamp.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_opamp.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief OPAMP LL module driver
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_pwr.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_pwr.c
index 23ea428557..8d7cb558eb 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_pwr.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_pwr.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_pwr.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief PWR LL module driver.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rcc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rcc.c
index f3e5597b7f..403ecf77a4 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rcc.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rcc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_rcc.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief RCC LL module driver.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rng.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rng.c
index 46596183a8..6406678f48 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rng.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rng.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_rng.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief RNG LL module driver.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rtc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rtc.c
index b562d109fa..ff51a88257 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rtc.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rtc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_rtc.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief RTC LL module driver.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_sdmmc.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_sdmmc.c
index cdb2615b49..f361a38efb 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_sdmmc.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_sdmmc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_sdmmc.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief SDMMC Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_spi.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_spi.c
index 15bf571b3d..d2a03dbae8 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_spi.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_spi.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_spi.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief SPI LL module driver.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_swpmi.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_swpmi.c
index a24169ed35..3ff6a28fcc 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_swpmi.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_swpmi.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_swpmi.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief SWPMI LL module driver.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_tim.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_tim.c
index 062087571d..db4b14ac63 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_tim.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_tim.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_tim.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief TIM LL module driver.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usart.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usart.c
index 31d6de7c63..46598340f3 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usart.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usart.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_usart.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief USART LL module driver.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c
index 5674589f30..2bb97be498 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_usb.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief USB Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
diff --git a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c
index 09bf57818c..64846adcdd 100644
--- a/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c
+++ b/system/Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l4xx_ll_utils.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 21-April-2017
+ * @version V1.7.2
+ * @date 16-June-2017
* @brief UTILS LL module driver.
******************************************************************************
* @attention
diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md
new file mode 100644
index 0000000000..ed862ed92c
--- /dev/null
+++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md
@@ -0,0 +1,17 @@
+# STM32YYxx HAL Drivers version:
+
+ * STM32F0: 1.6.0
+ * STM32F1: 1.1.1
+ * STM32F2: 1.2.1
+ * STM32F3: 1.5.0
+ * STM32F4: 1.7.1
+ * STM32F7: 1.2.2
+ * STM32L0: 1.8.1
+ * STM32L1: 1.3.0
+ * STM32L4: 1.7.2
+
+Release notes of each STM32YYxx HAL Drivers available here:
+
+`system/Drivers/STM32YYxx_HAL_Driver/Release_Notes.html`
+
+Where 'YY' is the STM32 MCU series.
diff --git a/variants/DISCO_F100RB/stm32f1xx_hal_conf.h b/variants/DISCO_F100RB/stm32f1xx_hal_conf.h
index fae1919075..0ff7f8d78a 100644
--- a/variants/DISCO_F100RB/stm32f1xx_hal_conf.h
+++ b/variants/DISCO_F100RB/stm32f1xx_hal_conf.h
@@ -2,15 +2,15 @@
******************************************************************************
* @file stm32f1xx_hal_conf.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.1
+ * @date 12-May-2017
* @brief HAL configuration template file.
* This file should be copied to the application folder and renamed
* to stm32f1xx_hal_conf.h.
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2016 STMicroelectronics
+ * © COPYRIGHT(c) 2017 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -83,6 +83,7 @@
#define HAL_UART_MODULE_ENABLED
//#define HAL_USART_MODULE_ENABLED
//#define HAL_WWDG_MODULE_ENABLED
+#define HAL_MMC_MODULE_ENABLED
/* ########################## Oscillator Values adaptation ####################*/
/**
@@ -92,14 +93,14 @@
*/
#if !defined (HSE_VALUE)
#if defined(USE_STM3210C_EVAL)
- #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+ #define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */
#else
- #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+ #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
#endif
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
- #define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */
+ #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
@@ -108,22 +109,28 @@
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
- #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
+ #define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz */
#endif /* HSI_VALUE */
+/**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE 40000U /*!< LSI Typical Value in Hz */
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature. */
/**
* @brief External Low Speed oscillator (LSE) value.
* This value is used by the UART, RTC HAL module to compute the system frequency
*/
#if !defined (LSE_VALUE)
- #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
+ #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
-
#if !defined (LSE_STARTUP_TIMEOUT)
- #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
+ #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
@@ -132,53 +139,52 @@
/**
* @brief This is the HAL system configuration section
*/
-#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
-#define TICK_INT_PRIORITY ((uint32_t)0x000F) /*!< tick interrupt priority */
-#define USE_RTOS 0
-#define PREFETCH_ENABLE 1
+#define VDD_VALUE 3300U /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */
+#define USE_RTOS 0U
+#define PREFETCH_ENABLE 1U
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
-/*#define USE_FULL_ASSERT 1*/
-
+/* #define USE_FULL_ASSERT 1U */
/* ################## Ethernet peripheral configuration ##################### */
/* Section 1 : Ethernet peripheral configuration */
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0 2
-#define MAC_ADDR1 0
-#define MAC_ADDR2 0
-#define MAC_ADDR3 0
-#define MAC_ADDR4 0
-#define MAC_ADDR5 0
+#define MAC_ADDR0 2U
+#define MAC_ADDR1 0U
+#define MAC_ADDR2 0U
+#define MAC_ADDR3 0U
+#define MAC_ADDR4 0U
+#define MAC_ADDR5 0U
/* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
-#define ETH_RXBUFNB ((uint32_t)8) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
-#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
+#define ETH_RXBUFNB 8U /* 8 Rx buffers of size ETH_RX_BUF_SIZE */
+#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
/* Section 2: PHY configuration section */
/* DP83848 PHY Address*/
-#define DP83848_PHY_ADDRESS 0x01
+#define DP83848_PHY_ADDRESS 0x01U
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
+#define PHY_RESET_DELAY 0x000000FFU
/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
+#define PHY_CONFIG_DELAY 0x00000FFFU
-#define PHY_READ_TO ((uint32_t)0x0000FFFF)
-#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
+#define PHY_READ_TO 0x0000FFFFU
+#define PHY_WRITE_TO 0x0000FFFFU
/* Section 3: Common PHY Registers */
-#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
-#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
+#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */
+#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
@@ -197,9 +203,9 @@
/* Section 4: Extended PHY Registers */
-#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
-#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
-#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
+#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */
+#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */
+#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */
#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
@@ -211,7 +217,14 @@
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
+/* ################## SPI peripheral configuration ########################## */
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+* Activated: CRC code is present inside driver
+* Deactivated: CRC code cleaned from driver
+*/
+
+#define USE_SPI_CRC 1U
/* Includes ------------------------------------------------------------------*/
/**
@@ -334,11 +347,13 @@
#include "stm32f1xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
-
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32f1xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32f1xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
@@ -350,11 +365,11 @@
* If expr is true, it returns no value.
* @retval None
*/
- #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
- #define assert_param(expr) ((void)0)
+ #define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
diff --git a/variants/NUCLEO_F103RB/stm32f1xx_hal_conf.h b/variants/NUCLEO_F103RB/stm32f1xx_hal_conf.h
index 505534a30e..f7e43947ff 100644
--- a/variants/NUCLEO_F103RB/stm32f1xx_hal_conf.h
+++ b/variants/NUCLEO_F103RB/stm32f1xx_hal_conf.h
@@ -2,15 +2,15 @@
******************************************************************************
* @file stm32f1xx_hal_conf.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.1
+ * @date 12-May-2017
* @brief HAL configuration template file.
* This file should be copied to the application folder and renamed
* to stm32f1xx_hal_conf.h.
******************************************************************************
* @attention
*
- * © COPYRIGHT(c) 2016 STMicroelectronics
+ * © COPYRIGHT(c) 2017 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -83,6 +83,7 @@
#define HAL_UART_MODULE_ENABLED
//#define HAL_USART_MODULE_ENABLED
//#define HAL_WWDG_MODULE_ENABLED
+#define HAL_MMC_MODULE_ENABLED
/* ########################## Oscillator Values adaptation ####################*/
/**
@@ -92,14 +93,14 @@
*/
#if !defined (HSE_VALUE)
#if defined(USE_STM3210C_EVAL)
- #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+ #define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */
#else
- #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+ #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
#endif
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
- #define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */
+ #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
@@ -108,22 +109,28 @@
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
- #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
+ #define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz */
#endif /* HSI_VALUE */
+/**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE 40000U /*!< LSI Typical Value in Hz */
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature. */
/**
* @brief External Low Speed oscillator (LSE) value.
* This value is used by the UART, RTC HAL module to compute the system frequency
*/
#if !defined (LSE_VALUE)
- #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
+ #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
-
#if !defined (LSE_STARTUP_TIMEOUT)
- #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
+ #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
@@ -132,53 +139,52 @@
/**
* @brief This is the HAL system configuration section
*/
-#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
-#define TICK_INT_PRIORITY ((uint32_t)0x000F) /*!< tick interrupt priority */
-#define USE_RTOS 0
-#define PREFETCH_ENABLE 1
+#define VDD_VALUE 3300U /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */
+#define USE_RTOS 0U
+#define PREFETCH_ENABLE 1U
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
-/*#define USE_FULL_ASSERT 1*/
-
+/* #define USE_FULL_ASSERT 1U */
/* ################## Ethernet peripheral configuration ##################### */
/* Section 1 : Ethernet peripheral configuration */
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0 2
-#define MAC_ADDR1 0
-#define MAC_ADDR2 0
-#define MAC_ADDR3 0
-#define MAC_ADDR4 0
-#define MAC_ADDR5 0
+#define MAC_ADDR0 2U
+#define MAC_ADDR1 0U
+#define MAC_ADDR2 0U
+#define MAC_ADDR3 0U
+#define MAC_ADDR4 0U
+#define MAC_ADDR5 0U
/* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
-#define ETH_RXBUFNB ((uint32_t)8) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
-#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
+#define ETH_RXBUFNB 8U /* 8 Rx buffers of size ETH_RX_BUF_SIZE */
+#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
/* Section 2: PHY configuration section */
/* DP83848 PHY Address*/
-#define DP83848_PHY_ADDRESS 0x01
+#define DP83848_PHY_ADDRESS 0x01U
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
+#define PHY_RESET_DELAY 0x000000FFU
/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
+#define PHY_CONFIG_DELAY 0x00000FFFU
-#define PHY_READ_TO ((uint32_t)0x0000FFFF)
-#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
+#define PHY_READ_TO 0x0000FFFFU
+#define PHY_WRITE_TO 0x0000FFFFU
/* Section 3: Common PHY Registers */
-#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
-#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
+#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */
+#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
@@ -197,9 +203,9 @@
/* Section 4: Extended PHY Registers */
-#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
-#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
-#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
+#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */
+#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */
+#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */
#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
@@ -211,7 +217,14 @@
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
+/* ################## SPI peripheral configuration ########################## */
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+* Activated: CRC code is present inside driver
+* Deactivated: CRC code cleaned from driver
+*/
+
+#define USE_SPI_CRC 1U
/* Includes ------------------------------------------------------------------*/
/**
@@ -334,11 +347,13 @@
#include "stm32f1xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
-
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32f1xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32f1xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
@@ -350,11 +365,11 @@
* If expr is true, it returns no value.
* @retval None
*/
- #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
- #define assert_param(expr) ((void)0)
+ #define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
diff --git a/variants/NUCLEO_F207ZG/stm32f2xx_hal_conf.h b/variants/NUCLEO_F207ZG/stm32f2xx_hal_conf.h
index 1c7ebe8e04..1f0e92e3f9 100644
--- a/variants/NUCLEO_F207ZG/stm32f2xx_hal_conf.h
+++ b/variants/NUCLEO_F207ZG/stm32f2xx_hal_conf.h
@@ -47,28 +47,30 @@
/**
* @brief This is the list of modules to be used in the HAL driver
*/
-
#define HAL_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
-/*#define HAL_CRYP_MODULE_ENABLED */
/*#define HAL_CAN_MODULE_ENABLED */
/*#define HAL_CRC_MODULE_ENABLED */
/*#define HAL_CRYP_MODULE_ENABLED */
/*#define HAL_DAC_MODULE_ENABLED */
/*#define HAL_DCMI_MODULE_ENABLED */
+#define HAL_DMA_MODULE_ENABLED
#define HAL_ETH_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
/*#define HAL_NAND_MODULE_ENABLED */
/*#define HAL_NOR_MODULE_ENABLED */
/*#define HAL_PCCARD_MODULE_ENABLED */
/*#define HAL_SRAM_MODULE_ENABLED */
/*#define HAL_HASH_MODULE_ENABLED */
+#define HAL_GPIO_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
/*#define HAL_I2S_MODULE_ENABLED */
/*#define HAL_IWDG_MODULE_ENABLED */
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
/*#define HAL_RNG_MODULE_ENABLED */
/*#define HAL_RTC_MODULE_ENABLED */
/*#define HAL_SD_MODULE_ENABLED */
-#define HAL_MMC_MODULE_ENABLED
#define HAL_SPI_MODULE_ENABLED
#define HAL_TIM_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
@@ -76,14 +78,10 @@
/*#define HAL_IRDA_MODULE_ENABLED */
/*#define HAL_SMARTCARD_MODULE_ENABLED */
/*#define HAL_WWDG_MODULE_ENABLED */
+#define HAL_CORTEX_MODULE_ENABLED
#define HAL_PCD_MODULE_ENABLED
/*#define HAL_HCD_MODULE_ENABLED */
-#define HAL_GPIO_MODULE_ENABLED
-#define HAL_DMA_MODULE_ENABLED
-#define HAL_RCC_MODULE_ENABLED
-#define HAL_FLASH_MODULE_ENABLED
-#define HAL_PWR_MODULE_ENABLED
-#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_MMC_MODULE_ENABLED
/* ########################## HSE/HSI Values adaptation ##################### */
/**
@@ -92,11 +90,11 @@
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
- #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
+ #define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
- #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */
+ #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
@@ -105,27 +103,26 @@
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
- #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
+ #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
- #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/
+ #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature.*/
/**
* @brief External Low Speed oscillator (LSE) value.
-
*/
#if !defined (LSE_VALUE)
- #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
+ #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
- #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */
+ #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
#endif /* LSE_STARTUP_TIMEOUT */
/**
@@ -134,7 +131,7 @@
* frequency, this source is inserted directly through I2S_CKIN pad.
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
- #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/
+ #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the Internal oscillator in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
@@ -144,11 +141,11 @@
/**
* @brief This is the HAL system configuration section
*/
-#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */
-#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */
+#define VDD_VALUE 3300U /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */
#define USE_RTOS 0U
-#define PREFETCH_ENABLE 1
-#define INSTRUCTION_CACHE_ENABLE 1
+#define PREFETCH_ENABLE 1U
+#define INSTRUCTION_CACHE_ENABLE 1U
#define DATA_CACHE_ENABLE 1U
/* ########################## Assert Selection ############################## */
@@ -173,49 +170,56 @@
/* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
-#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
-#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
+#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
+#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
/* Section 2: PHY configuration section */
-/* LAN8742A_PHY_ADDRESS Address*/
-#define LAN8742A_PHY_ADDRESS 1U
+/* DP83848 PHY Address*/
+#define DP83848_PHY_ADDRESS 0x01U
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY ((uint32_t)0x000000FFU)
+#define PHY_RESET_DELAY 0x000000FFU
/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU)
+#define PHY_CONFIG_DELAY 0x00000FFFU
-#define PHY_READ_TO ((uint32_t)0x0000FFFFU)
-#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU)
+#define PHY_READ_TO 0x0000FFFFU
+#define PHY_WRITE_TO 0x0000FFFFU
/* Section 3: Common PHY Registers */
-#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */
-#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */
+#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */
+#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */
-#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */
-#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */
-#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */
-#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */
-#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */
-#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */
-#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */
+#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
+#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
+#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
+#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
+#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
+#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
+#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
-#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */
-#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */
-#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */
+#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
+#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
+#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
/* Section 4: Extended PHY Registers */
-#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */
-#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */
-#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */
+#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */
+#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */
+#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */
+
+#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
+#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
+#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
-#define PHY_ISFR ((uint16_t)0x000BU) /*!< PHY Interrupt Source Flag register Offset */
-#define PHY_ISFR_INT4 ((uint16_t)0x000BU) /*!< PHY Link down inturrupt */
+#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
+#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
+
+#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
+#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
/* ################## SPI peripheral configuration ########################## */
@@ -224,7 +228,8 @@
* Deactivated: CRC code cleaned from driver
*/
-#define USE_SPI_CRC 0U
+#define USE_SPI_CRC 1U
+
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
@@ -326,10 +331,6 @@
#include "stm32f2xx_hal_sd.h"
#endif /* HAL_SD_MODULE_ENABLED */
-#ifdef HAL_MMC_MODULE_ENABLED
- #include "stm32f2xx_hal_mmc.h"
-#endif /* HAL_MMC_MODULE_ENABLED */
-
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32f2xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
@@ -366,6 +367,9 @@
#include "stm32f2xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32f2xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
diff --git a/variants/NUCLEO_F303RE/stm32f3xx_hal_conf.h b/variants/NUCLEO_F303RE/stm32f3xx_hal_conf.h
index 7be547452d..5fbb6b1393 100644
--- a/variants/NUCLEO_F303RE/stm32f3xx_hal_conf.h
+++ b/variants/NUCLEO_F303RE/stm32f3xx_hal_conf.h
@@ -162,10 +162,11 @@
*/
#define VDD_VALUE (3300U) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority (lowest by default) */
-#define USE_RTOS 0
-#define PREFETCH_ENABLE 1
-#define INSTRUCTION_CACHE_ENABLE 0
-#define DATA_CACHE_ENABLE 0
+#define USE_RTOS 0U
+#define PREFETCH_ENABLE 1U
+#define INSTRUCTION_CACHE_ENABLE 0U
+#define DATA_CACHE_ENABLE 0U
+#define USE_SPI_CRC 1U
/* ########################## Assert Selection ############################## */
/**
@@ -315,15 +316,15 @@
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
- * @param expr: If expr is false, it calls assert_failed function
+ * @param expr If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
- #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
- void assert_failed(uint8_t* file, uint32_t line);
+ void assert_failed(char* file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
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