From 184fb08037d0349b715d6926af7ec54595607151 Mon Sep 17 00:00:00 2001 From: Sam Elliott Date: Fri, 2 Aug 2019 15:39:43 +0100 Subject: [PATCH 1/3] rustbuild: RISC-V is no longer an experimental LLVM target This commit moves RISC-V from the experimental LLVM targets to the regular LLVM targets. RISC-V was made non-experimental in https://reviews.llvm.org/rL366399 I have also sorted the list of LLVM targets, and changed the code around setting llvm_exp_targets (and its default) to match the code setting llvm_targets (and its default), ensuring future changes to the defaults, as LLVM targets become stable, affect as few places as possible. --- config.toml.example | 6 +++--- src/bootstrap/config.rs | 5 ++--- src/bootstrap/native.rs | 7 +++++-- 3 files changed, 10 insertions(+), 8 deletions(-) diff --git a/config.toml.example b/config.toml.example index c14adf8ce33c7..a1917031e4eb4 100644 --- a/config.toml.example +++ b/config.toml.example @@ -57,14 +57,14 @@ # support. You'll need to write a target specification at least, and most # likely, teach rustc about the C ABI of the target. Get in touch with the # Rust team and file an issue if you need assistance in porting! -#targets = "X86;ARM;AArch64;Mips;PowerPC;SystemZ;MSP430;Sparc;NVPTX;Hexagon" +#targets = "AArch64;ARM;Hexagon;MSP430;Mips;NVPTX;PowerPC;RISCV;Sparc;SystemZ;X86" # LLVM experimental targets to build support for. These targets are specified in # the same format as above, but since these targets are experimental, they are # not built by default and the experimental Rust compilation targets that depend # on them will not work unless the user opts in to building them. By default the -# `WebAssembly` and `RISCV` targets are enabled when compiling LLVM from scratch. -#experimental-targets = "WebAssembly;RISCV" +# `WebAssembly` target is enabled when compiling LLVM from scratch. +#experimental-targets = "WebAssembly" # Cap the number of parallel linker invocations when compiling LLVM. # This can be useful when building LLVM with debug info, which significantly diff --git a/src/bootstrap/config.rs b/src/bootstrap/config.rs index 20d7548df5c65..5a5f4ac725204 100644 --- a/src/bootstrap/config.rs +++ b/src/bootstrap/config.rs @@ -75,7 +75,7 @@ pub struct Config { pub llvm_link_shared: bool, pub llvm_clang_cl: Option, pub llvm_targets: Option, - pub llvm_experimental_targets: String, + pub llvm_experimental_targets: Option, pub llvm_link_jobs: Option, pub llvm_version_suffix: Option, pub llvm_use_linker: Option, @@ -524,8 +524,7 @@ impl Config { set(&mut config.llvm_static_stdcpp, llvm.static_libstdcpp); set(&mut config.llvm_link_shared, llvm.link_shared); config.llvm_targets = llvm.targets.clone(); - config.llvm_experimental_targets = llvm.experimental_targets.clone() - .unwrap_or_else(|| "WebAssembly;RISCV".to_string()); + config.llvm_experimental_targets = llvm.experimental_targets.clone(); config.llvm_link_jobs = llvm.link_jobs; config.llvm_version_suffix = llvm.version_suffix.clone(); config.llvm_clang_cl = llvm.clang_cl.clone(); diff --git a/src/bootstrap/native.rs b/src/bootstrap/native.rs index bf824775ccbf2..9405ae4b15535 100644 --- a/src/bootstrap/native.rs +++ b/src/bootstrap/native.rs @@ -125,14 +125,17 @@ impl Step for Llvm { } else { match builder.config.llvm_targets { Some(ref s) => s, - None => "X86;ARM;AArch64;Mips;PowerPC;SystemZ;MSP430;Sparc;NVPTX;Hexagon", + None => "AArch64;ARM;Hexagon;MSP430;Mips;NVPTX;PowerPC;RISCV;Sparc;SystemZ;X86", } }; let llvm_exp_targets = if self.emscripten { "" } else { - &builder.config.llvm_experimental_targets[..] + match builder.config.llvm_experimental_targets { + Some(ref s) => s, + None => "WebAssembly", + } }; let assertions = if builder.config.llvm_assertions {"ON"} else {"OFF"}; From 9cb948feea23e18d26f2457e8f672c36e4f91e5d Mon Sep 17 00:00:00 2001 From: Sam Elliott Date: Fri, 2 Aug 2019 17:05:59 +0100 Subject: [PATCH 2/3] rustbuild: WebAssembly is no longer an experimental LLVM backend --- config.toml.example | 7 +++---- src/bootstrap/native.rs | 4 ++-- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/config.toml.example b/config.toml.example index a1917031e4eb4..6816eaeaa9486 100644 --- a/config.toml.example +++ b/config.toml.example @@ -57,14 +57,13 @@ # support. You'll need to write a target specification at least, and most # likely, teach rustc about the C ABI of the target. Get in touch with the # Rust team and file an issue if you need assistance in porting! -#targets = "AArch64;ARM;Hexagon;MSP430;Mips;NVPTX;PowerPC;RISCV;Sparc;SystemZ;X86" +#targets = "AArch64;ARM;Hexagon;MSP430;Mips;NVPTX;PowerPC;RISCV;Sparc;SystemZ;WebAssembly;X86" # LLVM experimental targets to build support for. These targets are specified in # the same format as above, but since these targets are experimental, they are # not built by default and the experimental Rust compilation targets that depend -# on them will not work unless the user opts in to building them. By default the -# `WebAssembly` target is enabled when compiling LLVM from scratch. -#experimental-targets = "WebAssembly" +# on them will not work unless the user opts in to building them. +#experimental-targets = "" # Cap the number of parallel linker invocations when compiling LLVM. # This can be useful when building LLVM with debug info, which significantly diff --git a/src/bootstrap/native.rs b/src/bootstrap/native.rs index 9405ae4b15535..174e4638aac81 100644 --- a/src/bootstrap/native.rs +++ b/src/bootstrap/native.rs @@ -125,7 +125,7 @@ impl Step for Llvm { } else { match builder.config.llvm_targets { Some(ref s) => s, - None => "AArch64;ARM;Hexagon;MSP430;Mips;NVPTX;PowerPC;RISCV;Sparc;SystemZ;X86", + None => "AArch64;ARM;Hexagon;MSP430;Mips;NVPTX;PowerPC;RISCV;Sparc;SystemZ;WebAssembly;X86", } }; @@ -134,7 +134,7 @@ impl Step for Llvm { } else { match builder.config.llvm_experimental_targets { Some(ref s) => s, - None => "WebAssembly", + None => "", } }; From 2921de63bb2287f6971f3fe54cae96035c8e1ec6 Mon Sep 17 00:00:00 2001 From: Sam Elliott Date: Fri, 2 Aug 2019 17:40:57 +0100 Subject: [PATCH 3/3] rustbuild: correct line length --- src/bootstrap/native.rs | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/bootstrap/native.rs b/src/bootstrap/native.rs index 174e4638aac81..f02def3e1b05d 100644 --- a/src/bootstrap/native.rs +++ b/src/bootstrap/native.rs @@ -125,7 +125,8 @@ impl Step for Llvm { } else { match builder.config.llvm_targets { Some(ref s) => s, - None => "AArch64;ARM;Hexagon;MSP430;Mips;NVPTX;PowerPC;RISCV;Sparc;SystemZ;WebAssembly;X86", + None => "AArch64;ARM;Hexagon;MSP430;Mips;NVPTX;PowerPC;RISCV;\ + Sparc;SystemZ;WebAssembly;X86", } };