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Attempted to fix #141972 Parameter ABI inconsistency error in Rust for RISC-V

O-riscvTarget: RISC-V architectureTarget: RISC-V architecture

S-waiting-on-authorStatus: This is awaiting some action (such as code changes or more information) from the author.Status: This is awaiting some action (such as code changes or more information) from the author.

T-compilerRelevant to the compiler team, which will review and decide on the PR/issue.Relevant to the compiler team, which will review and decide on the PR/issue.

Status: Open (in progress).

rust-lang/rustnumber 141979

#141979 In rust-lang/rust;

· YingkaiLi-VM opened on Jun 3, 2025

Parameter ABI inconsistency error in Rust for RISC-V

A-ABIArea: Concerning the application binary interface (ABI)Area: Concerning the application binary interface (ABI)

C-bugCategory: This is a bug.Category: This is a bug.

O-riscvTarget: RISC-V architectureTarget: RISC-V architecture

T-compilerRelevant to the compiler team, which will review and decide on the PR/issue.Relevant to the compiler team, which will review and decide on the PR/issue.

Status: Open.

#141972 In rust-lang/rust;

· YingkaiLi-VM opened on Jun 3, 2025

[RISCV] Code model other than medium does not work with lto

A-LLVMArea: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.

A-LTOArea: Link-time optimization (LTO)Area: Link-time optimization (LTO)

C-bugCategory: This is a bug.Category: This is a bug.

O-riscvTarget: RISC-V architectureTarget: RISC-V architecture

P-lowLow priorityLow priority

regression-from-stable-to-stablePerformance or correctness regression from one stable version to another.Performance or correctness regression from one stable version to another.

S-has-mcveStatus: A Minimal Complete and Verifiable Example has been found for this issueStatus: A Minimal Complete and Verifiable Example has been found for this issue

Status: Open.

#139479 In rust-lang/rust;

· kxxt opened on Apr 7, 2025

is_riscv_feature_detected doesn't seem to actually detect anything at runtime

A-target-featureArea: Enabling/disabling target features like AVX, Neon, etc.Area: Enabling/disabling target features like AVX, Neon, etc.

C-bugCategory: This is a bug.Category: This is a bug.

O-riscvTarget: RISC-V architectureTarget: RISC-V architecture

T-libsRelevant to the library team, which will review and decide on the PR/issue.Relevant to the library team, which will review and decide on the PR/issue.

Status: Open.

#139139 In rust-lang/rust;

· ThomasHabets opened on Mar 30, 2025

RISC-V RVV not enabled despite <code>-Ctarget-cpu=native</code>

A-LLVMArea: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.

A-target-featureArea: Enabling/disabling target features like AVX, Neon, etc.Area: Enabling/disabling target features like AVX, Neon, etc.

C-bugCategory: This is a bug.Category: This is a bug.

O-riscvTarget: RISC-V architectureTarget: RISC-V architecture

T-compilerRelevant to the compiler team, which will review and decide on the PR/issue.Relevant to the compiler team, which will review and decide on the PR/issue.

Status: Open.

#138789 In rust-lang/rust;

· ThomasHabets opened on Mar 21, 2025

RISC-V intrinsics with one or more target features are not inlined

A-LLVMArea: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.

C-bugCategory: This is a bug.Category: This is a bug.

C-optimizationCategory: An issue highlighting optimization opportunities or PRs implementing suchCategory: An issue highlighting optimization opportunities or PRs implementing such

O-riscvTarget: RISC-V architectureTarget: RISC-V architecture

T-compilerRelevant to the compiler team, which will review and decide on the PR/issue.Relevant to the compiler team, which will review and decide on the PR/issue.

Status: Open.

#137293 In rust-lang/rust;

· brkydnc opened on Feb 19, 2025

How should we handle dynamic vector ABIs?

A-ABIArea: Concerning the application binary interface (ABI)Area: Concerning the application binary interface (ABI)

A-SIMDArea: SIMD (Single Instruction Multiple Data)Area: SIMD (Single Instruction Multiple Data)

C-discussionCategory: Discussion or questions that doesn't represent real issues.Category: Discussion or questions that doesn't represent real issues.

E-needs-designThis issue needs exploration and design to see how and if we can fix/implement itThis issue needs exploration and design to see how and if we can fix/implement it

O-AArch64Armv8-A or later processors in AArch64 modeArmv8-A or later processors in AArch64 mode

O-riscvTarget: RISC-V architectureTarget: RISC-V architecture

T-compilerRelevant to the compiler team, which will review and decide on the PR/issue.Relevant to the compiler team, which will review and decide on the PR/issue.

Status: Open.

#133146 In rust-lang/rust;

· workingjubilee opened on Nov 17, 2024

All interrupt ABIs should enforce either <code>()</code> or <code>!</code> as return types

A-ABIArea: Concerning the application binary interface (ABI)Area: Concerning the application binary interface (ABI)

A-hardware-interruptsArea: Code for handling the "interrupt ABI" of various processorsArea: Code for handling the "interrupt ABI" of various processors

A-LLVMArea: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.

C-bugCategory: This is a bug.Category: This is a bug.

F-abi_x86_interrupt

O-msp430

O-riscvTarget: RISC-V architectureTarget: RISC-V architecture

O-x86_32Target: x86 processors, 32 bit (like i686-*) (IA-32)Target: x86 processors, 32 bit (like i686-*) (IA-32)

O-x86_64Target: x86-64 processors (like x86_64-*) (also known as amd64 and x64)Target: x86-64 processors (like x86_64-*) (also known as amd64 and x64)

T-compilerRelevant to the compiler team, which will review and decide on the PR/issue.Relevant to the compiler team, which will review and decide on the PR/issue.

Status: Open.

#132841 In rust-lang/rust;

· workingjubilee opened on Nov 10, 2024

Most <code>extern "*-interrupt-*" fn</code> should enforce 0-sized signatures

A-ABIArea: Concerning the application binary interface (ABI)Area: Concerning the application binary interface (ABI)

A-hardware-interruptsArea: Code for handling the "interrupt ABI" of various processorsArea: Code for handling the "interrupt ABI" of various processors

A-LLVMArea: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.

C-bugCategory: This is a bug.Category: This is a bug.

O-AVRTarget: AVR processors (ATtiny, ATmega, etc.)Target: AVR processors (ATtiny, ATmega, etc.)

O-msp430

O-riscvTarget: RISC-V architectureTarget: RISC-V architecture

T-compilerRelevant to the compiler team, which will review and decide on the PR/issue.Relevant to the compiler team, which will review and decide on the PR/issue.

Status: Open.

#132837 In rust-lang/rust;

· workingjubilee opened on Nov 10, 2024

Directly calling <code>extern "riscv-interrupt-{m,s}" fn</code>... compiles?

A-ABIArea: Concerning the application binary interface (ABI)Area: Concerning the application binary interface (ABI)

A-hardware-interruptsArea: Code for handling the "interrupt ABI" of various processorsArea: Code for handling the "interrupt ABI" of various processors

A-LLVMArea: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.

C-bugCategory: This is a bug.Category: This is a bug.

O-AVRTarget: AVR processors (ATtiny, ATmega, etc.)Target: AVR processors (ATtiny, ATmega, etc.)

O-riscvTarget: RISC-V architectureTarget: RISC-V architecture

T-compilerRelevant to the compiler team, which will review and decide on the PR/issue.Relevant to the compiler team, which will review and decide on the PR/issue.

Status: Open.

#132836 In rust-lang/rust;

· workingjubilee opened on Nov 10, 2024

Some <code>-Ctarget-feature</code>s must be restrained on RISCV

A-ABIArea: Concerning the application binary interface (ABI)Area: Concerning the application binary interface (ABI)

A-floating-pointArea: Floating point numbers and arithmeticArea: Floating point numbers and arithmetic

C-bugCategory: This is a bug.Category: This is a bug.

E-needs-investigationCall for partcipation: This issues needs some investigation to determine current statusCall for partcipation: This issues needs some investigation to determine current status

O-riscvTarget: RISC-V architectureTarget: RISC-V architecture

T-compilerRelevant to the compiler team, which will review and decide on the PR/issue.Relevant to the compiler team, which will review and decide on the PR/issue.

Status: Open.

#132618 In rust-lang/rust;

· workingjubilee opened on Nov 4, 2024

rustc SIGSEGV compiling rug 1.24.1 crate on RISC-V Armbian 24.5.0

C-discussionCategory: Discussion or questions that doesn't represent real issues.Category: Discussion or questions that doesn't represent real issues.

I-crashIssue: The compiler crashes (SIGSEGV, SIGABRT, etc). Use I-ICE instead when the compiler panics.Issue: The compiler crashes (SIGSEGV, SIGABRT, etc). Use I-ICE instead when the compiler panics.

O-riscvTarget: RISC-V architectureTarget: RISC-V architecture

Status: Open.

#127180 In rust-lang/rust;

· mathsDOTearth opened on Jun 30, 2024