Create README.md

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Author: GProtoZeroW

README.md

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+# PythonUberHDL
+Python Jupyter Notebooks and FPGA designs showcasing what myHDL can do over traditional Verilog or VHDL
+
+Three Major usages of traditional HDL will be explored in a textbook style using Jupyter Notebooks and other learning materials to show how with
+[myHDL](http://www.myhdl.org/), [myhdlpeek](https://github.com/xesscorp/myhdlpeek), and other Python libraries. Python can simplify the development and enhance the testing of HDL that was once only possible with Verilog and VHDL
+
+The Three Main areas of HDL that will be explored are:
+1. Elementry Digital Logic at the introductory Electrical Engineering Bachelors levels (not to say this can be pick up anyone willing to invest the time or effort); 
+2. Digital Signal Processing 
+3. Fundamental Computer (Embedded) System design
+
+Accompanying YouTube Videos will be posted at (PyLCARS)