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deps: V8: cherry-pick 77d515484864
Original commit message: [riscv64] Move explicit specialization into .cc file Building with Gcc-10 causes error "explicit specialization in non-namespace scope". This change fixes it. Bug: v8:12649 Change-Id: I36b2b042b336c2dfd32ba5541fdbbdb8dc8b4fd7 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3473997 Reviewed-by: ji qiu <[email protected]> Commit-Queue: ji qiu <[email protected]> Cr-Commit-Position: refs/heads/main@{#79185} Refs: v8/v8@77d5154 PR-URL: #42067 Refs: v8/v8@b663343 Reviewed-By: Michaël Zasso <[email protected]> Reviewed-By: Jiawen Geng <[email protected]> Reviewed-By: Richard Lau <[email protected]> Reviewed-By: Colin Ihrig <[email protected]> Reviewed-By: Mary Marchini <[email protected]> Reviewed-By: Juan José Arboleda <[email protected]> Reviewed-By: James M Snell <[email protected]> Reviewed-By: Stewart X Addison <[email protected]>
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‎common.gypi

+1-1
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@
3636

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# Reset this number to 0 on major V8 upgrades.
3838
# Increment by one for each non-official patch applied to deps/v8.
39-
'v8_embedder_string': '-node.14',
39+
'v8_embedder_string': '-node.15',
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4141
##### V8 defaults for Node.js #####
4242

‎deps/v8/src/execution/riscv64/simulator-riscv64.cc

+203
Original file line numberDiff line numberDiff line change
@@ -86,6 +86,209 @@
8686
// PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
8787
// HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
8888
// MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
89+
static inline bool is_aligned(const unsigned val, const unsigned pos) {
90+
return pos ? (val & (pos - 1)) == 0 : true;
91+
}
92+
93+
static inline bool is_overlapped(const int astart, int asize, const int bstart,
94+
int bsize) {
95+
asize = asize == 0 ? 1 : asize;
96+
bsize = bsize == 0 ? 1 : bsize;
97+
98+
const int aend = astart + asize;
99+
const int bend = bstart + bsize;
100+
101+
return std::max(aend, bend) - std::min(astart, bstart) < asize + bsize;
102+
}
103+
static inline bool is_overlapped_widen(const int astart, int asize,
104+
const int bstart, int bsize) {
105+
asize = asize == 0 ? 1 : asize;
106+
bsize = bsize == 0 ? 1 : bsize;
107+
108+
const int aend = astart + asize;
109+
const int bend = bstart + bsize;
110+
111+
if (astart < bstart && is_overlapped(astart, asize, bstart, bsize) &&
112+
!is_overlapped(astart, asize, bstart + bsize, bsize)) {
113+
return false;
114+
} else {
115+
return std::max(aend, bend) - std::min(astart, bstart) < asize + bsize;
116+
}
117+
}
118+
119+
#ifdef DEBUG
120+
#define require_align(val, pos) \
121+
if (!is_aligned(val, pos)) { \
122+
std::cout << val << " " << pos << std::endl; \
123+
} \
124+
CHECK_EQ(is_aligned(val, pos), true)
125+
#else
126+
#define require_align(val, pos) CHECK_EQ(is_aligned(val, pos), true)
127+
#endif
128+
129+
// RVV
130+
// The following code about RVV was based from:
131+
// https://github.com/riscv/riscv-isa-sim
132+
// Copyright (c) 2010-2017, The Regents of the University of California
133+
// (Regents). All Rights Reserved.
134+
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// Redistribution and use in source and binary forms, with or without
136+
// modification, are permitted provided that the following conditions are met:
137+
// 1. Redistributions of source code must retain the above copyright
138+
// notice, this list of conditions and the following disclaimer.
139+
// 2. Redistributions in binary form must reproduce the above copyright
140+
// notice, this list of conditions and the following disclaimer in the
141+
// documentation and/or other materials provided with the distribution.
142+
// 3. Neither the name of the Regents nor the
143+
// names of its contributors may be used to endorse or promote products
144+
// derived from this software without specific prior written permission.
145+
146+
// IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
147+
// SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS,
148+
// ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
149+
// REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
150+
151+
// REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED
152+
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
153+
// PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
154+
// HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
155+
// MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
156+
template <uint64_t N>
157+
struct type_usew_t;
158+
template <>
159+
struct type_usew_t<8> {
160+
using type = uint8_t;
161+
};
162+
163+
template <>
164+
struct type_usew_t<16> {
165+
using type = uint16_t;
166+
};
167+
168+
template <>
169+
struct type_usew_t<32> {
170+
using type = uint32_t;
171+
};
172+
173+
template <>
174+
struct type_usew_t<64> {
175+
using type = uint64_t;
176+
};
177+
178+
template <>
179+
struct type_usew_t<128> {
180+
using type = __uint128_t;
181+
};
182+
template <uint64_t N>
183+
struct type_sew_t;
184+
185+
template <>
186+
struct type_sew_t<8> {
187+
using type = int8_t;
188+
};
189+
190+
template <>
191+
struct type_sew_t<16> {
192+
using type = int16_t;
193+
};
194+
195+
template <>
196+
struct type_sew_t<32> {
197+
using type = int32_t;
198+
};
199+
200+
template <>
201+
struct type_sew_t<64> {
202+
using type = int64_t;
203+
};
204+
205+
template <>
206+
struct type_sew_t<128> {
207+
using type = __int128_t;
208+
};
209+
210+
#define VV_PARAMS(x) \
211+
type_sew_t<x>::type& vd = \
212+
Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
213+
type_sew_t<x>::type vs1 = Rvvelt<type_sew_t<x>::type>(rvv_vs1_reg(), i); \
214+
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
215+
216+
#define VV_UPARAMS(x) \
217+
type_usew_t<x>::type& vd = \
218+
Rvvelt<type_usew_t<x>::type>(rvv_vd_reg(), i, true); \
219+
type_usew_t<x>::type vs1 = Rvvelt<type_usew_t<x>::type>(rvv_vs1_reg(), i); \
220+
type_usew_t<x>::type vs2 = Rvvelt<type_usew_t<x>::type>(rvv_vs2_reg(), i);
221+
222+
#define VX_PARAMS(x) \
223+
type_sew_t<x>::type& vd = \
224+
Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
225+
type_sew_t<x>::type rs1 = (type_sew_t<x>::type)(get_register(rs1_reg())); \
226+
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
227+
228+
#define VX_UPARAMS(x) \
229+
type_usew_t<x>::type& vd = \
230+
Rvvelt<type_usew_t<x>::type>(rvv_vd_reg(), i, true); \
231+
type_usew_t<x>::type rs1 = (type_usew_t<x>::type)(get_register(rs1_reg())); \
232+
type_usew_t<x>::type vs2 = Rvvelt<type_usew_t<x>::type>(rvv_vs2_reg(), i);
233+
234+
#define VI_PARAMS(x) \
235+
type_sew_t<x>::type& vd = \
236+
Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
237+
type_sew_t<x>::type simm5 = (type_sew_t<x>::type)(instr_.RvvSimm5()); \
238+
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
239+
240+
#define VI_UPARAMS(x) \
241+
type_usew_t<x>::type& vd = \
242+
Rvvelt<type_usew_t<x>::type>(rvv_vd_reg(), i, true); \
243+
type_usew_t<x>::type uimm5 = (type_usew_t<x>::type)(instr_.RvvUimm5()); \
244+
type_usew_t<x>::type vs2 = Rvvelt<type_usew_t<x>::type>(rvv_vs2_reg(), i);
245+
246+
#define VN_PARAMS(x) \
247+
constexpr int half_x = x >> 1; \
248+
type_sew_t<half_x>::type& vd = \
249+
Rvvelt<type_sew_t<half_x>::type>(rvv_vd_reg(), i, true); \
250+
type_sew_t<x>::type uimm5 = (type_sew_t<x>::type)(instr_.RvvUimm5()); \
251+
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
252+
253+
#define VN_UPARAMS(x) \
254+
constexpr int half_x = x >> 1; \
255+
type_usew_t<half_x>::type& vd = \
256+
Rvvelt<type_usew_t<half_x>::type>(rvv_vd_reg(), i, true); \
257+
type_usew_t<x>::type uimm5 = (type_usew_t<x>::type)(instr_.RvvUimm5()); \
258+
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
259+
260+
#define VXI_PARAMS(x) \
261+
type_sew_t<x>::type& vd = \
262+
Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
263+
type_sew_t<x>::type vs1 = Rvvelt<type_sew_t<x>::type>(rvv_vs1_reg(), i); \
264+
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i); \
265+
type_sew_t<x>::type rs1 = (type_sew_t<x>::type)(get_register(rs1_reg())); \
266+
type_sew_t<x>::type simm5 = (type_sew_t<x>::type)(instr_.RvvSimm5());
267+
268+
#define VI_XI_SLIDEDOWN_PARAMS(x, off) \
269+
auto& vd = Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
270+
auto vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i + off);
271+
272+
#define VI_XI_SLIDEUP_PARAMS(x, offset) \
273+
auto& vd = Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
274+
auto vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i - offset);
275+
276+
/* Vector Integer Extension */
277+
#define VI_VIE_PARAMS(x, scale) \
278+
if ((x / scale) < 8) UNREACHABLE(); \
279+
auto& vd = Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
280+
auto vs2 = Rvvelt<type_sew_t<x / scale>::type>(rvv_vs2_reg(), i);
281+
282+
#define VI_VIE_UPARAMS(x, scale) \
283+
if ((x / scale) < 8) UNREACHABLE(); \
284+
auto& vd = Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
285+
auto vs2 = Rvvelt<type_usew_t<x / scale>::type>(rvv_vs2_reg(), i);
286+
287+
#define require_noover(astart, asize, bstart, bsize) \
288+
CHECK_EQ(!is_overlapped(astart, asize, bstart, bsize), true)
289+
#define require_noover_widen(astart, asize, bstart, bsize) \
290+
CHECK_EQ(!is_overlapped_widen(astart, asize, bstart, bsize), true)
291+
89292
#define RVV_VI_GENERAL_LOOP_BASE \
90293
for (uint64_t i = rvv_vstart(); i < rvv_vl(); i++) {
91294
#define RVV_VI_LOOP_END \

‎deps/v8/src/execution/riscv64/simulator-riscv64.h

-133
Original file line numberDiff line numberDiff line change
@@ -645,139 +645,6 @@ class Simulator : public SimulatorBase {
645645
}
646646
}
647647

648-
// RVV
649-
// The following code about RVV was based from:
650-
// https://github.com/riscv/riscv-isa-sim
651-
// Copyright (c) 2010-2017, The Regents of the University of California
652-
// (Regents). All Rights Reserved.
653-
654-
// Redistribution and use in source and binary forms, with or without
655-
// modification, are permitted provided that the following conditions are met:
656-
// 1. Redistributions of source code must retain the above copyright
657-
// notice, this list of conditions and the following disclaimer.
658-
// 2. Redistributions in binary form must reproduce the above copyright
659-
// notice, this list of conditions and the following disclaimer in the
660-
// documentation and/or other materials provided with the distribution.
661-
// 3. Neither the name of the Regents nor the
662-
// names of its contributors may be used to endorse or promote products
663-
// derived from this software without specific prior written permission.
664-
665-
// IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
666-
// SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS,
667-
// ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
668-
// REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
669-
670-
// REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED
671-
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
672-
// PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
673-
// HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
674-
// MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
675-
template <uint64_t N>
676-
struct type_usew_t;
677-
template <>
678-
struct type_usew_t<8> {
679-
using type = uint8_t;
680-
};
681-
682-
template <>
683-
struct type_usew_t<16> {
684-
using type = uint16_t;
685-
};
686-
687-
template <>
688-
struct type_usew_t<32> {
689-
using type = uint32_t;
690-
};
691-
692-
template <>
693-
struct type_usew_t<64> {
694-
using type = uint64_t;
695-
};
696-
697-
template <>
698-
struct type_usew_t<128> {
699-
using type = __uint128_t;
700-
};
701-
template <uint64_t N>
702-
struct type_sew_t;
703-
704-
template <>
705-
struct type_sew_t<8> {
706-
using type = int8_t;
707-
};
708-
709-
template <>
710-
struct type_sew_t<16> {
711-
using type = int16_t;
712-
};
713-
714-
template <>
715-
struct type_sew_t<32> {
716-
using type = int32_t;
717-
};
718-
719-
template <>
720-
struct type_sew_t<64> {
721-
using type = int64_t;
722-
};
723-
724-
template <>
725-
struct type_sew_t<128> {
726-
using type = __int128_t;
727-
};
728-
729-
#define VV_PARAMS(x) \
730-
type_sew_t<x>::type& vd = \
731-
Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
732-
type_sew_t<x>::type vs1 = Rvvelt<type_sew_t<x>::type>(rvv_vs1_reg(), i); \
733-
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
734-
735-
#define VV_UPARAMS(x) \
736-
type_usew_t<x>::type& vd = \
737-
Rvvelt<type_usew_t<x>::type>(rvv_vd_reg(), i, true); \
738-
type_usew_t<x>::type vs1 = Rvvelt<type_usew_t<x>::type>(rvv_vs1_reg(), i); \
739-
type_usew_t<x>::type vs2 = Rvvelt<type_usew_t<x>::type>(rvv_vs2_reg(), i);
740-
741-
#define VX_PARAMS(x) \
742-
type_sew_t<x>::type& vd = \
743-
Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
744-
type_sew_t<x>::type rs1 = (type_sew_t<x>::type)(get_register(rs1_reg())); \
745-
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
746-
747-
#define VX_UPARAMS(x) \
748-
type_usew_t<x>::type& vd = \
749-
Rvvelt<type_usew_t<x>::type>(rvv_vd_reg(), i, true); \
750-
type_usew_t<x>::type rs1 = (type_usew_t<x>::type)(get_register(rs1_reg())); \
751-
type_usew_t<x>::type vs2 = Rvvelt<type_usew_t<x>::type>(rvv_vs2_reg(), i);
752-
753-
#define VI_PARAMS(x) \
754-
type_sew_t<x>::type& vd = \
755-
Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
756-
type_sew_t<x>::type simm5 = (type_sew_t<x>::type)(instr_.RvvSimm5()); \
757-
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i);
758-
759-
#define VI_UPARAMS(x) \
760-
type_usew_t<x>::type& vd = \
761-
Rvvelt<type_usew_t<x>::type>(rvv_vd_reg(), i, true); \
762-
type_usew_t<x>::type uimm5 = (type_usew_t<x>::type)(instr_.RvvUimm5()); \
763-
type_usew_t<x>::type vs2 = Rvvelt<type_usew_t<x>::type>(rvv_vs2_reg(), i);
764-
765-
#define VXI_PARAMS(x) \
766-
type_sew_t<x>::type& vd = \
767-
Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
768-
type_sew_t<x>::type vs1 = Rvvelt<type_sew_t<x>::type>(rvv_vs1_reg(), i); \
769-
type_sew_t<x>::type vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i); \
770-
type_sew_t<x>::type rs1 = (type_sew_t<x>::type)(get_register(rs1_reg())); \
771-
type_sew_t<x>::type simm5 = (type_sew_t<x>::type)(instr_.RvvSimm5());
772-
773-
#define VI_XI_SLIDEDOWN_PARAMS(x, off) \
774-
auto& vd = Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
775-
auto vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i + off);
776-
777-
#define VI_XI_SLIDEUP_PARAMS(x, offset) \
778-
auto& vd = Rvvelt<type_sew_t<x>::type>(rvv_vd_reg(), i, true); \
779-
auto vs2 = Rvvelt<type_sew_t<x>::type>(rvv_vs2_reg(), i - offset);
780-
781648
inline void rvv_trace_vd() {
782649
if (::v8::internal::FLAG_trace_sim) {
783650
__int128_t value = Vregister_[rvv_vd_reg()];

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