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19 | 19 | __attribute__((__always_inline__, __nodebug__, __target__("avx10.2-256"), \
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20 | 20 | __min_vector_width__(128)))
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21 | 21 |
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| 22 | +/// Constructs a 128-bit integer vector, setting the lower 32 bits to the |
| 23 | +/// lower 32 bits of the parameter \a __A; the upper bits are zeoroed. |
| 24 | +/// |
| 25 | +/// \code{.operation} |
| 26 | +/// result[31:0] := __A[31:0] |
| 27 | +/// result[MAX:32] := 0 |
| 28 | +/// \endcode |
| 29 | +/// |
| 30 | +/// \headerfile <immintrin.h> |
| 31 | +/// |
| 32 | +/// This intrinsic corresponds to the <c> VMOVD </c> instruction. |
| 33 | +/// |
| 34 | +/// \param __A |
| 35 | +/// A 128-bit integer vector. |
| 36 | +/// \returns A 128-bit integer vector. The lower 32 bits are copied from the |
| 37 | +/// parameter \a __A; the upper bits are zeroed. |
22 | 38 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_move_epi32(__m128i __A) {
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23 | 39 | return (__m128i)__builtin_shufflevector(
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24 | 40 | (__v4si)__A, (__v4si)_mm_setzero_si128(), 0, 4, 4, 4);
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25 | 41 | }
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26 | 42 |
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| 43 | +/// Constructs a 128-bit integer vector, setting the lower 16 bits to the |
| 44 | +/// lower 16 bits of the parameter \a __A; the upper bits are zeoroed. |
| 45 | +/// |
| 46 | +/// \code{.operation} |
| 47 | +/// result[15:0] := __A[15:0] |
| 48 | +/// result[MAX:16] := 0 |
| 49 | +/// \endcode |
| 50 | +/// |
| 51 | +/// \headerfile <immintrin.h> |
| 52 | +/// |
| 53 | +/// This intrinsic corresponds to the <c> VMOVW </c> instruction. |
| 54 | +/// |
| 55 | +/// \param __A |
| 56 | +/// A 128-bit integer vector. |
| 57 | +/// \returns A 128-bit integer vector. The lower 16 bits are copied from the |
| 58 | +/// parameter \a __A; the upper bits are zeroed. |
27 | 59 | static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_move_epi16(__m128i __A) {
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28 | 60 | return (__m128i)__builtin_shufflevector(
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29 | 61 | (__v8hi)__A, (__v8hi)_mm_setzero_si128(), 0, 8, 8, 8, 8, 8, 8, 8);
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