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smeenaismeenai
committedNov 11, 2023
Revert "[IR] Mark lshr and ashr constant expressions as undesirable"
This reverts commit 82f68a9. cd7ba9f needs to be reverted to fix test failures on builds without assertions, and this one needs to be reverted first for that.
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‎clang/test/Analysis/builtin_signbit.cpp

+38-50
Original file line numberDiff line numberDiff line change
@@ -12,72 +12,60 @@ long double ld = -1.0L;
1212
// CHECK-BE32-LABEL: define dso_local void @_Z12test_signbitv(
1313
// CHECK-BE32-SAME: ) #[[ATTR0:[0-9]+]] {
1414
// CHECK-BE32-NEXT: entry:
15-
// CHECK-BE32-NEXT: [[TMP0:%.*]] = lshr i128 bitcast (ppc_fp128 0xM3FF00000000000000000000000000000 to i128), 64
16-
// CHECK-BE32-NEXT: [[TMP1:%.*]] = trunc i128 [[TMP0]] to i64
17-
// CHECK-BE32-NEXT: [[TMP2:%.*]] = icmp slt i64 [[TMP1]], 0
18-
// CHECK-BE32-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TMP2]] to i8
15+
// CHECK-BE32-NEXT: [[FROMBOOL:%.*]] = zext i1 icmp slt (i64 trunc (i128 lshr (i128 bitcast (ppc_fp128 0xM3FF00000000000000000000000000000 to i128), i128 64) to i64), i64 0) to i8
1916
// CHECK-BE32-NEXT: store i8 [[FROMBOOL]], ptr @b, align 1
20-
// CHECK-BE32-NEXT: [[TMP3:%.*]] = load ppc_fp128, ptr @ld, align 16
21-
// CHECK-BE32-NEXT: [[TMP4:%.*]] = bitcast ppc_fp128 [[TMP3]] to i128
22-
// CHECK-BE32-NEXT: [[TMP5:%.*]] = lshr i128 [[TMP4]], 64
23-
// CHECK-BE32-NEXT: [[TMP6:%.*]] = trunc i128 [[TMP5]] to i64
24-
// CHECK-BE32-NEXT: [[TMP7:%.*]] = icmp slt i64 [[TMP6]], 0
25-
// CHECK-BE32-NEXT: [[FROMBOOL1:%.*]] = zext i1 [[TMP7]] to i8
17+
// CHECK-BE32-NEXT: [[TMP0:%.*]] = load ppc_fp128, ptr @ld, align 16
18+
// CHECK-BE32-NEXT: [[TMP1:%.*]] = bitcast ppc_fp128 [[TMP0]] to i128
19+
// CHECK-BE32-NEXT: [[TMP2:%.*]] = lshr i128 [[TMP1]], 64
20+
// CHECK-BE32-NEXT: [[TMP3:%.*]] = trunc i128 [[TMP2]] to i64
21+
// CHECK-BE32-NEXT: [[TMP4:%.*]] = icmp slt i64 [[TMP3]], 0
22+
// CHECK-BE32-NEXT: [[FROMBOOL1:%.*]] = zext i1 [[TMP4]] to i8
2623
// CHECK-BE32-NEXT: store i8 [[FROMBOOL1]], ptr @b, align 1
2724
// CHECK-BE32-NEXT: store i8 0, ptr @b, align 1
28-
// CHECK-BE32-NEXT: [[TMP8:%.*]] = load double, ptr @d, align 8
29-
// CHECK-BE32-NEXT: [[CONV:%.*]] = fptrunc double [[TMP8]] to float
30-
// CHECK-BE32-NEXT: [[TMP9:%.*]] = bitcast float [[CONV]] to i32
31-
// CHECK-BE32-NEXT: [[TMP10:%.*]] = icmp slt i32 [[TMP9]], 0
32-
// CHECK-BE32-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TMP10]] to i8
25+
// CHECK-BE32-NEXT: [[TMP5:%.*]] = load double, ptr @d, align 8
26+
// CHECK-BE32-NEXT: [[CONV:%.*]] = fptrunc double [[TMP5]] to float
27+
// CHECK-BE32-NEXT: [[TMP6:%.*]] = bitcast float [[CONV]] to i32
28+
// CHECK-BE32-NEXT: [[TMP7:%.*]] = icmp slt i32 [[TMP6]], 0
29+
// CHECK-BE32-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TMP7]] to i8
3330
// CHECK-BE32-NEXT: store i8 [[FROMBOOL2]], ptr @b, align 1
34-
// CHECK-BE32-NEXT: [[TMP11:%.*]] = lshr i128 bitcast (ppc_fp128 0xM3FF00000000000000000000000000000 to i128), 64
35-
// CHECK-BE32-NEXT: [[TMP12:%.*]] = trunc i128 [[TMP11]] to i64
36-
// CHECK-BE32-NEXT: [[TMP13:%.*]] = icmp slt i64 [[TMP12]], 0
37-
// CHECK-BE32-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TMP13]] to i8
31+
// CHECK-BE32-NEXT: [[FROMBOOL3:%.*]] = zext i1 icmp slt (i64 trunc (i128 lshr (i128 bitcast (ppc_fp128 0xM3FF00000000000000000000000000000 to i128), i128 64) to i64), i64 0) to i8
3832
// CHECK-BE32-NEXT: store i8 [[FROMBOOL3]], ptr @b, align 1
39-
// CHECK-BE32-NEXT: [[TMP14:%.*]] = load ppc_fp128, ptr @ld, align 16
40-
// CHECK-BE32-NEXT: [[TMP15:%.*]] = bitcast ppc_fp128 [[TMP14]] to i128
41-
// CHECK-BE32-NEXT: [[TMP16:%.*]] = lshr i128 [[TMP15]], 64
42-
// CHECK-BE32-NEXT: [[TMP17:%.*]] = trunc i128 [[TMP16]] to i64
43-
// CHECK-BE32-NEXT: [[TMP18:%.*]] = icmp slt i64 [[TMP17]], 0
44-
// CHECK-BE32-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[TMP18]] to i8
33+
// CHECK-BE32-NEXT: [[TMP8:%.*]] = load ppc_fp128, ptr @ld, align 16
34+
// CHECK-BE32-NEXT: [[TMP9:%.*]] = bitcast ppc_fp128 [[TMP8]] to i128
35+
// CHECK-BE32-NEXT: [[TMP10:%.*]] = lshr i128 [[TMP9]], 64
36+
// CHECK-BE32-NEXT: [[TMP11:%.*]] = trunc i128 [[TMP10]] to i64
37+
// CHECK-BE32-NEXT: [[TMP12:%.*]] = icmp slt i64 [[TMP11]], 0
38+
// CHECK-BE32-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[TMP12]] to i8
4539
// CHECK-BE32-NEXT: store i8 [[FROMBOOL4]], ptr @b, align 1
4640
// CHECK-BE32-NEXT: ret void
4741
//
4842
// CHECK-BE64-LABEL: define dso_local void @_Z12test_signbitv(
4943
// CHECK-BE64-SAME: ) #[[ATTR0:[0-9]+]] {
5044
// CHECK-BE64-NEXT: entry:
51-
// CHECK-BE64-NEXT: [[TMP0:%.*]] = lshr i128 bitcast (ppc_fp128 0xM3FF00000000000000000000000000000 to i128), 64
52-
// CHECK-BE64-NEXT: [[TMP1:%.*]] = trunc i128 [[TMP0]] to i64
53-
// CHECK-BE64-NEXT: [[TMP2:%.*]] = icmp slt i64 [[TMP1]], 0
54-
// CHECK-BE64-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TMP2]] to i8
45+
// CHECK-BE64-NEXT: [[FROMBOOL:%.*]] = zext i1 icmp slt (i64 trunc (i128 lshr (i128 bitcast (ppc_fp128 0xM3FF00000000000000000000000000000 to i128), i128 64) to i64), i64 0) to i8
5546
// CHECK-BE64-NEXT: store i8 [[FROMBOOL]], ptr @b, align 1
56-
// CHECK-BE64-NEXT: [[TMP3:%.*]] = load ppc_fp128, ptr @ld, align 16
57-
// CHECK-BE64-NEXT: [[TMP4:%.*]] = bitcast ppc_fp128 [[TMP3]] to i128
58-
// CHECK-BE64-NEXT: [[TMP5:%.*]] = lshr i128 [[TMP4]], 64
59-
// CHECK-BE64-NEXT: [[TMP6:%.*]] = trunc i128 [[TMP5]] to i64
60-
// CHECK-BE64-NEXT: [[TMP7:%.*]] = icmp slt i64 [[TMP6]], 0
61-
// CHECK-BE64-NEXT: [[FROMBOOL1:%.*]] = zext i1 [[TMP7]] to i8
47+
// CHECK-BE64-NEXT: [[TMP0:%.*]] = load ppc_fp128, ptr @ld, align 16
48+
// CHECK-BE64-NEXT: [[TMP1:%.*]] = bitcast ppc_fp128 [[TMP0]] to i128
49+
// CHECK-BE64-NEXT: [[TMP2:%.*]] = lshr i128 [[TMP1]], 64
50+
// CHECK-BE64-NEXT: [[TMP3:%.*]] = trunc i128 [[TMP2]] to i64
51+
// CHECK-BE64-NEXT: [[TMP4:%.*]] = icmp slt i64 [[TMP3]], 0
52+
// CHECK-BE64-NEXT: [[FROMBOOL1:%.*]] = zext i1 [[TMP4]] to i8
6253
// CHECK-BE64-NEXT: store i8 [[FROMBOOL1]], ptr @b, align 1
6354
// CHECK-BE64-NEXT: store i8 0, ptr @b, align 1
64-
// CHECK-BE64-NEXT: [[TMP8:%.*]] = load double, ptr @d, align 8
65-
// CHECK-BE64-NEXT: [[CONV:%.*]] = fptrunc double [[TMP8]] to float
66-
// CHECK-BE64-NEXT: [[TMP9:%.*]] = bitcast float [[CONV]] to i32
67-
// CHECK-BE64-NEXT: [[TMP10:%.*]] = icmp slt i32 [[TMP9]], 0
68-
// CHECK-BE64-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TMP10]] to i8
55+
// CHECK-BE64-NEXT: [[TMP5:%.*]] = load double, ptr @d, align 8
56+
// CHECK-BE64-NEXT: [[CONV:%.*]] = fptrunc double [[TMP5]] to float
57+
// CHECK-BE64-NEXT: [[TMP6:%.*]] = bitcast float [[CONV]] to i32
58+
// CHECK-BE64-NEXT: [[TMP7:%.*]] = icmp slt i32 [[TMP6]], 0
59+
// CHECK-BE64-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TMP7]] to i8
6960
// CHECK-BE64-NEXT: store i8 [[FROMBOOL2]], ptr @b, align 1
70-
// CHECK-BE64-NEXT: [[TMP11:%.*]] = lshr i128 bitcast (ppc_fp128 0xM3FF00000000000000000000000000000 to i128), 64
71-
// CHECK-BE64-NEXT: [[TMP12:%.*]] = trunc i128 [[TMP11]] to i64
72-
// CHECK-BE64-NEXT: [[TMP13:%.*]] = icmp slt i64 [[TMP12]], 0
73-
// CHECK-BE64-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TMP13]] to i8
61+
// CHECK-BE64-NEXT: [[FROMBOOL3:%.*]] = zext i1 icmp slt (i64 trunc (i128 lshr (i128 bitcast (ppc_fp128 0xM3FF00000000000000000000000000000 to i128), i128 64) to i64), i64 0) to i8
7462
// CHECK-BE64-NEXT: store i8 [[FROMBOOL3]], ptr @b, align 1
75-
// CHECK-BE64-NEXT: [[TMP14:%.*]] = load ppc_fp128, ptr @ld, align 16
76-
// CHECK-BE64-NEXT: [[TMP15:%.*]] = bitcast ppc_fp128 [[TMP14]] to i128
77-
// CHECK-BE64-NEXT: [[TMP16:%.*]] = lshr i128 [[TMP15]], 64
78-
// CHECK-BE64-NEXT: [[TMP17:%.*]] = trunc i128 [[TMP16]] to i64
79-
// CHECK-BE64-NEXT: [[TMP18:%.*]] = icmp slt i64 [[TMP17]], 0
80-
// CHECK-BE64-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[TMP18]] to i8
63+
// CHECK-BE64-NEXT: [[TMP8:%.*]] = load ppc_fp128, ptr @ld, align 16
64+
// CHECK-BE64-NEXT: [[TMP9:%.*]] = bitcast ppc_fp128 [[TMP8]] to i128
65+
// CHECK-BE64-NEXT: [[TMP10:%.*]] = lshr i128 [[TMP9]], 64
66+
// CHECK-BE64-NEXT: [[TMP11:%.*]] = trunc i128 [[TMP10]] to i64
67+
// CHECK-BE64-NEXT: [[TMP12:%.*]] = icmp slt i64 [[TMP11]], 0
68+
// CHECK-BE64-NEXT: [[FROMBOOL4:%.*]] = zext i1 [[TMP12]] to i8
8169
// CHECK-BE64-NEXT: store i8 [[FROMBOOL4]], ptr @b, align 1
8270
// CHECK-BE64-NEXT: ret void
8371
//

‎llvm/lib/IR/Constants.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -2133,13 +2133,13 @@ bool ConstantExpr::isDesirableBinOp(unsigned Opcode) {
21332133
case Instruction::FRem:
21342134
case Instruction::And:
21352135
case Instruction::Or:
2136-
case Instruction::LShr:
2137-
case Instruction::AShr:
21382136
return false;
21392137
case Instruction::Add:
21402138
case Instruction::Sub:
21412139
case Instruction::Mul:
21422140
case Instruction::Shl:
2141+
case Instruction::LShr:
2142+
case Instruction::AShr:
21432143
case Instruction::Xor:
21442144
return true;
21452145
default:

‎llvm/test/CodeGen/AArch64/stack-tagging-initializer-merge.ll

+1-2
Original file line numberDiff line numberDiff line change
@@ -215,8 +215,7 @@ entry:
215215

216216
; CHECK-LABEL: define void @InitVectorSplit(
217217
; CHECK: [[TX:%.*]] = call ptr @llvm.aarch64.tagp
218-
; CHECK: [[LSHR:%.*]] = lshr i64 bitcast (<2 x i32> <i32 1, i32 2> to i64), 32
219-
; CHECK: call void @llvm.aarch64.stgp(ptr [[TX]], i64 shl (i64 bitcast (<2 x i32> <i32 1, i32 2> to i64), i64 32), i64 [[LSHR]])
218+
; CHECK: call void @llvm.aarch64.stgp(ptr [[TX]], i64 shl (i64 bitcast (<2 x i32> <i32 1, i32 2> to i64), i64 32), i64 lshr (i64 bitcast (<2 x i32> <i32 1, i32 2> to i64), i64 32))
220219
; CHECK: ret void
221220

222221
define void @MemSetZero() sanitize_memtag {

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