diff --git a/.gitignore b/.gitignore new file mode 100644 index 00000000..7bb44d67 --- /dev/null +++ b/.gitignore @@ -0,0 +1,3 @@ +/.project +/.cproject +/.settings/ diff --git a/driver_lib/driver/gpio16.c b/driver_lib/driver/gpio16.c index 1b832d62..50a47e46 100644 --- a/driver_lib/driver/gpio16.c +++ b/driver_lib/driver/gpio16.c @@ -26,41 +26,33 @@ #include "osapi.h" #include "driver/gpio16.h" -void ICACHE_FLASH_ATTR -gpio16_output_conf(void) -{ +void ICACHE_FLASH_ATTR gpio16_output_conf(void) { WRITE_PERI_REG(PAD_XPD_DCDC_CONF, - (READ_PERI_REG(PAD_XPD_DCDC_CONF) & 0xffffffbc) | (uint32_t)0x1); // mux configuration for XPD_DCDC to output rtc_gpio0 + (READ_PERI_REG(PAD_XPD_DCDC_CONF) & 0xffffffbc) | (uint32_t)0x1); /* mux configuration for XPD_DCDC to output rtc_gpio0 */ WRITE_PERI_REG(RTC_GPIO_CONF, - (READ_PERI_REG(RTC_GPIO_CONF) & (uint32_t)0xfffffffe) | (uint32_t)0x0); //mux configuration for out enable + (READ_PERI_REG(RTC_GPIO_CONF) & (uint32_t)0xfffffffe) | (uint32_t)0x0); /* mux configuration for out enable */ WRITE_PERI_REG(RTC_GPIO_ENABLE, - (READ_PERI_REG(RTC_GPIO_ENABLE) & (uint32_t)0xfffffffe) | (uint32_t)0x1); //out enable + (READ_PERI_REG(RTC_GPIO_ENABLE) & (uint32_t)0xfffffffe) | (uint32_t)0x1); /* out enable */ } -void ICACHE_FLASH_ATTR -gpio16_output_set(uint8_t value) -{ +void ICACHE_FLASH_ATTR gpio16_output_set(uint8_t value) { WRITE_PERI_REG(RTC_GPIO_OUT, (READ_PERI_REG(RTC_GPIO_OUT) & (uint32_t)0xfffffffe) | (uint32_t)(value & 1)); } -void ICACHE_FLASH_ATTR -gpio16_input_conf(void) -{ +void ICACHE_FLASH_ATTR gpio16_input_conf(void) { WRITE_PERI_REG(PAD_XPD_DCDC_CONF, - (READ_PERI_REG(PAD_XPD_DCDC_CONF) & 0xffffffbc) | (uint32_t)0x1); // mux configuration for XPD_DCDC and rtc_gpio0 connection + (READ_PERI_REG(PAD_XPD_DCDC_CONF) & 0xffffffbc) | (uint32_t)0x1); /* mux configuration for XPD_DCDC and rtc_gpio0 connection */ WRITE_PERI_REG(RTC_GPIO_CONF, - (READ_PERI_REG(RTC_GPIO_CONF) & (uint32_t)0xfffffffe) | (uint32_t)0x0); //mux configuration for out enable + (READ_PERI_REG(RTC_GPIO_CONF) & (uint32_t)0xfffffffe) | (uint32_t)0x0); /* mux configuration for out enable */ WRITE_PERI_REG(RTC_GPIO_ENABLE, - READ_PERI_REG(RTC_GPIO_ENABLE) & (uint32_t)0xfffffffe); //out disable + READ_PERI_REG(RTC_GPIO_ENABLE) & (uint32_t)0xfffffffe); /* out disable */ } -uint8_t ICACHE_FLASH_ATTR -gpio16_input_get(void) -{ +uint8_t ICACHE_FLASH_ATTR gpio16_input_get(void) { return (uint8_t)(READ_PERI_REG(RTC_GPIO_IN_DATA) & 1); } diff --git a/driver_lib/driver/hw_timer.c b/driver_lib/driver/hw_timer.c index 245b2c77..9a90ee7c 100644 --- a/driver_lib/driver/hw_timer.c +++ b/driver_lib/driver/hw_timer.c @@ -114,7 +114,7 @@ void ICACHE_FLASH_ATTR hw_timer_init(frc1_timer_source_type source_type, uint8_t ETS_FRC1_INTR_ENABLE(); } -//-------------------------------Test Code Below-------------------------------------- +/*-------------------------------Test Code Below--------------------------------------*/ #if 0 void hw_test_timer_cb(void) { @@ -128,7 +128,7 @@ void hw_test_timer_cb(void) j = 0; } - //hw_timer_arm(50); + /* hw_timer_arm(50); */ } void ICACHE_FLASH_ATTR user_init(void) diff --git a/driver_lib/driver/i2c_master.c b/driver_lib/driver/i2c_master.c index 076d995c..d223a1a8 100644 --- a/driver_lib/driver/i2c_master.c +++ b/driver_lib/driver/i2c_master.c @@ -22,12 +22,13 @@ * */ #include "ets_sys.h" +#include "c_types.h" #include "osapi.h" #include "gpio.h" #include "driver/i2c_master.h" -LOCAL uint8_t m_nLastSDA; -LOCAL uint8_t m_nLastSCL; +static uint8_t m_nLastSDA; +static uint8_t m_nLastSCL; /****************************************************************************** * FunctionName : i2c_master_setDC @@ -37,9 +38,7 @@ LOCAL uint8_t m_nLastSCL; * uint8_t SCL * Returns : NONE *******************************************************************************/ -LOCAL void ICACHE_FLASH_ATTR -i2c_master_setDC(uint8_t SDA, uint8_t SCL) -{ +static void ICACHE_FLASH_ATTR i2c_master_setDC(uint8_t SDA, uint8_t SCL) { SDA &= 0x01; SCL &= 0x01; m_nLastSDA = SDA; @@ -63,9 +62,7 @@ i2c_master_setDC(uint8_t SDA, uint8_t SCL) * Parameters : NONE * Returns : uint8_t - SDA bit value *******************************************************************************/ -LOCAL uint8_t ICACHE_FLASH_ATTR -i2c_master_getDC(void) -{ +static uint8_t ICACHE_FLASH_ATTR i2c_master_getDC(void) { uint8_t sda_out; sda_out = GPIO_INPUT_GET(GPIO_ID_PIN(I2C_MASTER_SDA_GPIO)); return sda_out; @@ -77,29 +74,27 @@ i2c_master_getDC(void) * Parameters : NONE * Returns : NONE *******************************************************************************/ -void ICACHE_FLASH_ATTR -i2c_master_init(void) -{ +void ICACHE_FLASH_ATTR i2c_master_init(void) { uint8_t i; i2c_master_setDC(1, 0); i2c_master_wait(5); - // when SCL = 0, toggle SDA to clear up + /* when SCL = 0, toggle SDA to clear up */ i2c_master_setDC(0, 0) ; i2c_master_wait(5); i2c_master_setDC(1, 0) ; i2c_master_wait(5); - // set data_cnt to max value + /* set data_cnt to max value */ for (i = 0; i < 28; i++) { i2c_master_setDC(1, 0); - i2c_master_wait(5); // sda 1, scl 0 + i2c_master_wait(5); /* sda 1, scl 0 */ i2c_master_setDC(1, 1); - i2c_master_wait(5); // sda 1, scl 1 + i2c_master_wait(5); /* sda 1, scl 1 */ } - // reset all + /* reset all */ i2c_master_stop(); return; } @@ -111,24 +106,22 @@ i2c_master_init(void) * Parameters : NONE * Returns : NONE *******************************************************************************/ -void ICACHE_FLASH_ATTR -i2c_master_gpio_init(void) -{ +void ICACHE_FLASH_ATTR i2c_master_gpio_init(void) { ETS_GPIO_INTR_DISABLE() ; -// ETS_INTR_LOCK(); +/* ETS_INTR_LOCK(); */ PIN_FUNC_SELECT(I2C_MASTER_SDA_MUX, I2C_MASTER_SDA_FUNC); PIN_FUNC_SELECT(I2C_MASTER_SCL_MUX, I2C_MASTER_SCL_FUNC); - GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(I2C_MASTER_SDA_GPIO)), GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(I2C_MASTER_SDA_GPIO))) | GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_ENABLE)); //open drain; + GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(I2C_MASTER_SDA_GPIO)), GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(I2C_MASTER_SDA_GPIO))) | GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_ENABLE)); GPIO_REG_WRITE(GPIO_ENABLE_ADDRESS, GPIO_REG_READ(GPIO_ENABLE_ADDRESS) | (1 << I2C_MASTER_SDA_GPIO)); - GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(I2C_MASTER_SCL_GPIO)), GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(I2C_MASTER_SCL_GPIO))) | GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_ENABLE)); //open drain; + GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(I2C_MASTER_SCL_GPIO)), GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(I2C_MASTER_SCL_GPIO))) | GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_ENABLE)); GPIO_REG_WRITE(GPIO_ENABLE_ADDRESS, GPIO_REG_READ(GPIO_ENABLE_ADDRESS) | (1 << I2C_MASTER_SCL_GPIO)); I2C_MASTER_SDA_HIGH_SCL_HIGH(); ETS_GPIO_INTR_ENABLE() ; -// ETS_INTR_UNLOCK(); +/* ETS_INTR_UNLOCK(); */ i2c_master_init(); } @@ -139,15 +132,13 @@ i2c_master_gpio_init(void) * Parameters : NONE * Returns : NONE *******************************************************************************/ -void ICACHE_FLASH_ATTR -i2c_master_start(void) -{ +void ICACHE_FLASH_ATTR i2c_master_start(void) { i2c_master_setDC(1, m_nLastSCL); i2c_master_wait(5); i2c_master_setDC(1, 1); - i2c_master_wait(5); // sda 1, scl 1 + i2c_master_wait(5); /* sda 1, scl 1 */ i2c_master_setDC(0, 1); - i2c_master_wait(5); // sda 0, scl 1 + i2c_master_wait(5); /* sda 0, scl 1 */ } /****************************************************************************** @@ -156,17 +147,15 @@ i2c_master_start(void) * Parameters : NONE * Returns : NONE *******************************************************************************/ -void ICACHE_FLASH_ATTR -i2c_master_stop(void) -{ +void ICACHE_FLASH_ATTR i2c_master_stop(void) { i2c_master_wait(5); i2c_master_setDC(0, m_nLastSCL); - i2c_master_wait(5); // sda 0 + i2c_master_wait(5); /* sda 0 */ i2c_master_setDC(0, 1); - i2c_master_wait(5); // sda 0, scl 1 + i2c_master_wait(5); /* sda 0, scl 1 */ i2c_master_setDC(1, 1); - i2c_master_wait(5); // sda 1, scl 1 + i2c_master_wait(5); /* sda 1, scl 1 */ } /****************************************************************************** @@ -175,17 +164,15 @@ i2c_master_stop(void) * Parameters : uint8_t level - 0 or 1 * Returns : NONE *******************************************************************************/ -void ICACHE_FLASH_ATTR -i2c_master_setAck(uint8_t level) -{ +void ICACHE_FLASH_ATTR i2c_master_setAck(uint8_t level) { i2c_master_setDC(m_nLastSDA, 0); i2c_master_wait(5); i2c_master_setDC(level, 0); - i2c_master_wait(5); // sda level, scl 0 + i2c_master_wait(5); /* sda level, scl 0 */ i2c_master_setDC(level, 1); - i2c_master_wait(8); // sda level, scl 1 + i2c_master_wait(8); /* sda level, scl 1 */ i2c_master_setDC(level, 0); - i2c_master_wait(5); // sda level, scl 0 + i2c_master_wait(5); /* sda level, scl 0 */ i2c_master_setDC(1, 0); i2c_master_wait(5); } @@ -196,9 +183,7 @@ i2c_master_setAck(uint8_t level) * Parameters : NONE * Returns : uint8_t - ack value, 0 or 1 *******************************************************************************/ -uint8_t ICACHE_FLASH_ATTR -i2c_master_getAck(void) -{ +uint8_t ICACHE_FLASH_ATTR i2c_master_getAck(void) { uint8_t retVal; i2c_master_setDC(m_nLastSDA, 0); i2c_master_wait(5); @@ -221,13 +206,12 @@ i2c_master_getAck(void) * Parameters : NONE * Returns : true : get ack ; false : get nack *******************************************************************************/ -bool ICACHE_FLASH_ATTR -i2c_master_checkAck(void) +bool ICACHE_FLASH_ATTR i2c_master_checkAck(void) { if (i2c_master_getAck()) { - return FALSE; + return false; } else { - return TRUE; + return true; } } @@ -237,20 +221,17 @@ i2c_master_checkAck(void) * Parameters : NONE * Returns : NONE *******************************************************************************/ -void ICACHE_FLASH_ATTR -i2c_master_send_ack(void) -{ +void ICACHE_FLASH_ATTR i2c_master_send_ack(void) { i2c_master_setAck(0x0); } + /****************************************************************************** * FunctionName : i2c_master_send_nack * Description : response nack * Parameters : NONE * Returns : NONE *******************************************************************************/ -void ICACHE_FLASH_ATTR -i2c_master_send_nack(void) -{ +void ICACHE_FLASH_ATTR i2c_master_send_nack(void) { i2c_master_setAck(0x1); } @@ -260,28 +241,26 @@ i2c_master_send_nack(void) * Parameters : NONE * Returns : uint8_t - readed value *******************************************************************************/ -uint8_t ICACHE_FLASH_ATTR -i2c_master_readByte(void) -{ +uint8_t ICACHE_FLASH_ATTR i2c_master_readByte(void) { uint8_t retVal = 0; uint8_t k, i; i2c_master_wait(5); i2c_master_setDC(m_nLastSDA, 0); - i2c_master_wait(5); // sda 1, scl 0 + i2c_master_wait(5); /* sda 1, scl 0 */ for (i = 0; i < 8; i++) { i2c_master_wait(5); i2c_master_setDC(1, 0); - i2c_master_wait(5); // sda 1, scl 0 + i2c_master_wait(5); /* sda 1, scl 0 */ i2c_master_setDC(1, 1); - i2c_master_wait(5); // sda 1, scl 1 + i2c_master_wait(5); /* sda 1, scl 1 */ k = i2c_master_getDC(); i2c_master_wait(5); if (i == 7) { - i2c_master_wait(3); //// + i2c_master_wait(3); } k <<= (7 - i); @@ -289,7 +268,7 @@ i2c_master_readByte(void) } i2c_master_setDC(1, 0); - i2c_master_wait(5); // sda 1, scl 0 + i2c_master_wait(5); /* sda 1, scl 0 */ return retVal; } @@ -300,11 +279,9 @@ i2c_master_readByte(void) * Parameters : uint8_t wrdata - write value * Returns : NONE *******************************************************************************/ -void ICACHE_FLASH_ATTR -i2c_master_writeByte(uint8_t wrdata) -{ +void ICACHE_FLASH_ATTR i2c_master_writeByte(uint8_t wrdata) { uint8_t dat; - sint8 i; + int8_t i; i2c_master_wait(5); @@ -319,7 +296,7 @@ i2c_master_writeByte(uint8_t wrdata) i2c_master_wait(5); if (i == 0) { - i2c_master_wait(3); //// + i2c_master_wait(3); } i2c_master_setDC(dat, 0); diff --git a/driver_lib/driver/key.c b/driver_lib/driver/key.c index 19ec40c0..a67582fd 100644 --- a/driver_lib/driver/key.c +++ b/driver_lib/driver/key.c @@ -30,7 +30,7 @@ #include "gpio.h" #include "driver/key.h" -LOCAL void key_intr_handler(void *arg); +static void key_intr_handler(void *arg); /****************************************************************************** * FunctionName : key_init_single @@ -82,10 +82,10 @@ key_init(struct keys_param *keys) | GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_DISABLE) | GPIO_PIN_SOURCE_SET(GPIO_AS_PIN_SOURCE)); - //clear gpio14 status + /* clear gpio14 status */ GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, BIT(keys->single_key[i]->gpio_id)); - //enable interrupt + /* enable interrupt */ gpio_pin_intr_state_set(GPIO_ID_PIN(keys->single_key[i]->gpio_id), GPIO_PIN_INTR_NEGEDGE); } @@ -98,12 +98,12 @@ key_init(struct keys_param *keys) * Parameters : single_key_param *single_key - single key parameter * Returns : none *******************************************************************************/ -LOCAL void ICACHE_FLASH_ATTR +static void ICACHE_FLASH_ATTR key_5s_cb(struct single_key_param *single_key) { os_timer_disarm(&single_key->key_5s); - // low, then restart + /* low, then restart */ if (0 == GPIO_INPUT_GET(GPIO_ID_PIN(single_key->gpio_id))) { if (single_key->long_press) { single_key->long_press(); @@ -117,12 +117,12 @@ key_5s_cb(struct single_key_param *single_key) * Parameters : single_key_param *single_key - single key parameter * Returns : none *******************************************************************************/ -LOCAL void ICACHE_FLASH_ATTR +static void ICACHE_FLASH_ATTR key_50ms_cb(struct single_key_param *single_key) { os_timer_disarm(&single_key->key_50ms); - // high, then key is up + /* high, then key is up */ if (1 == GPIO_INPUT_GET(GPIO_ID_PIN(single_key->gpio_id))) { os_timer_disarm(&single_key->key_5s); single_key->key_level = 1; @@ -142,7 +142,7 @@ key_50ms_cb(struct single_key_param *single_key) * Parameters : key_param *keys - keys parameter, which inited by key_init_single * Returns : none *******************************************************************************/ -LOCAL void +static void key_intr_handler(void *arg) { uint8_t i; @@ -151,21 +151,21 @@ key_intr_handler(void *arg) for (i = 0; i < keys->key_num; i++) { if (gpio_status & BIT(keys->single_key[i]->gpio_id)) { - //disable interrupt + /* disable interrupt */ gpio_pin_intr_state_set(GPIO_ID_PIN(keys->single_key[i]->gpio_id), GPIO_PIN_INTR_DISABLE); - //clear interrupt status + /* clear interrupt status */ GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, gpio_status & BIT(keys->single_key[i]->gpio_id)); if (keys->single_key[i]->key_level == 1) { - // 5s, restart & enter softap mode + /* 5s, restart & enter softap mode */ os_timer_disarm(&keys->single_key[i]->key_5s); os_timer_setfn(&keys->single_key[i]->key_5s, (os_timer_func_t *)key_5s_cb, keys->single_key[i]); os_timer_arm(&keys->single_key[i]->key_5s, 5000, 0); keys->single_key[i]->key_level = 0; gpio_pin_intr_state_set(GPIO_ID_PIN(keys->single_key[i]->gpio_id), GPIO_PIN_INTR_POSEDGE); } else { - // 50ms, check if this is a real key up + /* 50ms, check if this is a real key up */ os_timer_disarm(&keys->single_key[i]->key_50ms); os_timer_setfn(&keys->single_key[i]->key_50ms, (os_timer_func_t *)key_50ms_cb, keys->single_key[i]); os_timer_arm(&keys->single_key[i]->key_50ms, 50, 0); diff --git a/driver_lib/driver/sdio_slv.c b/driver_lib/driver/sdio_slv.c index dd909946..cfb218e9 100644 --- a/driver_lib/driver/sdio_slv.c +++ b/driver_lib/driver/sdio_slv.c @@ -25,20 +25,20 @@ #include "ets_sys.h" #include "osapi.h" #include "os_type.h" -//#include "gpio.h" #include "user_interface.h" #include "mem.h" -#include "driver/slc_register.h" #include "driver/sdio_slv.h" +#include "driver/slc_register.h" -#define SDIO_TOKEN_SIZE 0 // 4 +#define SDIO_TOKEN_SIZE 0 /* 4 */ #define RX_BUFFER_SIZE 512 #define RX_BUFFER_NUM 4 #define TX_BUFFER_SIZE 512 #define SLC_INTEREST_EVENT (SLC_TX_EOF_INT_ENA | SLC_RX_EOF_INT_ENA | SLC_RX_UDF_INT_ENA | SLC_TX_DSCR_ERR_INT_ENA) #define TRIG_TOHOST_INT() SET_PERI_REG_MASK(SLC_INTVEC_TOHOST , BIT0);\ - //CLEAR_PERI_REG_MASK(SLC_INTVEC_TOHOST , BIT0) + /* CLEAR_PERI_REG_MASK(SLC_INTVEC_TOHOST , BIT0) */ + struct sdio_queue { uint32_t blocksize: 12; uint32_t datalen: 12; @@ -65,7 +65,6 @@ union sdio_slave_status { uint32_t word_value; }; -//uint8_t rx_buffer[RX_BUFFER_NUM][RX_BUFFER_SIZE],tx_buffer[1024]; uint8_t tx_buffer[TX_BUFFER_SIZE]; uint32_t data_len = 0; @@ -82,8 +81,6 @@ struct sdio_list *pTail_ToSend; struct sdio_list *pHead_Sended; struct sdio_list *pTail_Sended; - - os_event_t *sdioQueue; struct sdio_queue rx_que, tx_que; @@ -93,7 +90,6 @@ static void sdio_slave_isr(void *para); static void tx_buff_handle_done(void); static void rx_buff_read_done(void); static void tx_buff_write_done(void); - static void sdio_try_to_load(void); static void sdio_read_done_process(void); @@ -102,21 +98,20 @@ void sdio_slave_init(void) uint32_t regval = 0; union sdio_slave_status sdio_sta; ETS_SDIO_INTR_DISABLE(); - ////reset orginal link + /* reset orginal link */ SET_PERI_REG_MASK(SLC_CONF0, SLC_RXLINK_RST | SLC_TXLINK_RST); CLEAR_PERI_REG_MASK(SLC_CONF0, SLC_RXLINK_RST | SLC_TXLINK_RST); os_printf("RX&TX link reset!\n"); - //set sdio mode + /* set sdio mode */ SET_PERI_REG_MASK(SLC_RX_DSCR_CONF, SLC_RX_EOF_MODE | SLC_RX_FILL_MODE); - //clear to host interrupt io signal for preventing from random initial signal. + /* clear to host interrupt io signal for preventing from random initial signal. */ WRITE_PERI_REG(SLC_HOST_INTR_CLR, 0xffffffff); - //enable 2 events to trigger the to host intr io + /* enable 2 events to trigger the to host intr io */ SET_PERI_REG_MASK(SLC_HOST_INTR_ENA, SLC_HOST_TOHOST_BIT0_INT_ENA); - ////initialize rx queue information - has_read = TRUE; + has_read = true; pHead_ToSend = NULL; int32_t loop = RX_BUFFER_NUM; @@ -131,13 +126,14 @@ void sdio_slave_init(void) p = p->next; } - //os_printf("p:0x%08x\r\n",p); + /* os_printf("p:0x%08x\r\n",p); */ p->tail = p->buffer + SDIO_TOKEN_SIZE; p->next = NULL; } pTail_Sended = p; + /* initialize rx queue information */ rx_que.blocksize = RX_BUFFER_SIZE; rx_que.datalen = 0; rx_que.eof = 1; @@ -148,7 +144,7 @@ void sdio_slave_init(void) rx_que.next_link_ptr = 0; - ////initialize tx queue information + /* initialize tx queue information */ tx_que.blocksize = TX_BUFFER_SIZE; tx_que.datalen = 0; tx_que.eof = 0; @@ -158,7 +154,7 @@ void sdio_slave_init(void) tx_que.buf_ptr = (uint32_t)tx_buffer; tx_que.next_link_ptr = 0; - ///////link tx&rx queue information address to sdio hardware + /* link tx&rx queue information address to sdio hardware */ CLEAR_PERI_REG_MASK(SLC_RX_LINK, SLC_RXLINK_DESCADDR_MASK); regval = ((uint32_t)&rx_que); SET_PERI_REG_MASK(SLC_RX_LINK, regval & SLC_RXLINK_DESCADDR_MASK); @@ -170,7 +166,7 @@ void sdio_slave_init(void) SET_PERI_REG_MASK(SLC_RX_DSCR_CONF, SLC_TOKEN_NO_REPLACE); #endif - /////config sdio_status reg + /* config sdio_status reg */ sdio_sta.elm_value.comm_cnt = 7; sdio_sta.elm_value.intr_no = INIT_STAGE; sdio_sta.elm_value.wr_busy = 0; @@ -181,18 +177,17 @@ void sdio_slave_init(void) WRITE_PERI_REG(SLC_HOST_CONF_W2, sdio_sta.word_value); - /////attach isr func to sdio interrupt + /* attach isr func to sdio interrupt */ ETS_SDIO_INTR_ATTACH(sdio_slave_isr, NULL); - /////enable sdio operation intr + /* enable sdio operation intr */ WRITE_PERI_REG(SLC_INT_ENA, SLC_INTEREST_EVENT); - /////clear sdio initial random active intr signal + /* clear sdio initial random active intr signal */ WRITE_PERI_REG(SLC_INT_CLR, 0xffffffff); - /////enable sdio intr in cpu + /* enable sdio intr in cpu */ ETS_SDIO_INTR_ENABLE(); } -static void sdio_slave_isr(void *para) -{ +static void sdio_slave_isr(void *para) { uint32_t slc_intr_status, postval; static uint8_t state = 0; uint16_t rx_len, i; @@ -206,42 +201,41 @@ static void sdio_slave_isr(void *para) return; } - //clear all intrs + /* clear all intrs */ WRITE_PERI_REG(SLC_INT_CLR, slc_intr_status); - //os_printf("slc_intr_status:0x%08x\r\n",slc_intr_status); - //process every intr + /* os_printf("slc_intr_status:0x%08x\r\n",slc_intr_status); */ - //TO HOST DONE + /* TO HOST DONE */ if (slc_intr_status & SLC_RX_EOF_INT_ENA) { - //following code must be called after a data pack has been read + /* following code must be called after a data pack has been read */ rx_buff_read_done(); - //TRIG_TOHOST_INT(); - //system_os_post(2, 1, 0); + /* TRIG_TOHOST_INT(); + system_os_post(2, 1, 0); */ sdio_read_done_process(); } - //FROM HOST DONE + /* FROM HOST DONE */ if (slc_intr_status & SLC_TX_EOF_INT_ENA) { - //call the following function after host cpu data transmission finished + /* call the following function after host cpu data transmission finished */ tx_buff_write_done(); - //system_os_post(USER_TASK_PRIO_1,SDIO_DATA_ERROR,0); - //os_printf("%d,%s\r\n",tx_que.datalen,tx_que.buf_ptr); - //at_fake_uart_rx((uint8_t*)tx_que.buf_ptr,tx_que.datalen); + /* system_os_post(USER_TASK_PRIO_1,SDIO_DATA_ERROR,0); */ + /* os_printf("%d,%s\r\n",tx_que.datalen,tx_que.buf_ptr); */ + /* at_fake_uart_rx((uint8_t*)tx_que.buf_ptr,tx_que.datalen); */ if (sdio_recv_data_callback_ptr) { sdio_recv_data_callback_ptr((uint8_t *)tx_que.buf_ptr, tx_que.datalen); } tx_buff_handle_done(); TRIG_TOHOST_INT(); - //system_os_post(2, 3, 0); + /* system_os_post(2, 3, 0); */ } - //TO HOST underflow + /* TO HOST underflow */ if (slc_intr_status & SLC_RX_UDF_INT_ENA) { } - //FROM HOST overflow + /* FROM HOST overflow */ if (slc_intr_status & SLC_TX_DSCR_ERR_INT_ENA) { } @@ -254,52 +248,49 @@ static void sdio_slave_isr(void *para) } -static void rx_buff_read_done(void) -{ +static void rx_buff_read_done(void) { union sdio_slave_status sdio_sta; - /////modify sdio status reg + + /* modify sdio status reg */ sdio_sta.word_value = READ_PERI_REG(SLC_HOST_CONF_W2); sdio_sta.elm_value.comm_cnt++; sdio_sta.elm_value.rd_empty = 1; sdio_sta.elm_value.rx_length = 0; sdio_sta.elm_value.intr_no &= (~RX_AVAILIBLE); - WRITE_PERI_REG(SLC_HOST_CONF_W2, sdio_sta.word_value); //update sdio status register - //os_printf("rx_buff_read_done\r\n"); + WRITE_PERI_REG(SLC_HOST_CONF_W2, sdio_sta.word_value); /* update sdio status register */ + /* os_printf("rx_buff_read_done\r\n"); */ } -static void tx_buff_write_done(void) -{ +static void tx_buff_write_done(void) { union sdio_slave_status sdio_sta; - /////modify sdio status reg + + /* modify sdio status reg */ sdio_sta.word_value = READ_PERI_REG(SLC_HOST_CONF_W2); sdio_sta.elm_value.comm_cnt++; sdio_sta.elm_value.wr_busy = 1; sdio_sta.elm_value.intr_no &= (~TX_AVAILIBLE); - WRITE_PERI_REG(SLC_HOST_CONF_W2, sdio_sta.word_value); //update sdio status register + WRITE_PERI_REG(SLC_HOST_CONF_W2, sdio_sta.word_value); /* update sdio status register */ } -static void tx_buff_handle_done(void) -{ +static void tx_buff_handle_done(void) { union sdio_slave_status sdio_sta; - /////config tx queue information + /* config tx queue information */ tx_que.blocksize = TX_BUFFER_SIZE; tx_que.datalen = 0; tx_que.eof = 0; tx_que.owner = 1; - /////modify sdio status reg + /* modify sdio status reg */ sdio_sta.word_value = READ_PERI_REG(SLC_HOST_CONF_W2); sdio_sta.elm_value.wr_busy = 0; sdio_sta.elm_value.intr_no |= TX_AVAILIBLE; - SET_PERI_REG_MASK(SLC_TX_LINK, SLC_TXLINK_START); //tx buffer is ready for being written - WRITE_PERI_REG(SLC_HOST_CONF_W2, sdio_sta.word_value); //update sdio status register - //*******************************************************************// - + SET_PERI_REG_MASK(SLC_TX_LINK, SLC_TXLINK_START); /* tx buffer is ready for being written */ + WRITE_PERI_REG(SLC_HOST_CONF_W2, sdio_sta.word_value); /* update sdio status register */ } -static int32_t rx_buff_load_done(uint16_t rx_len) -{ + +static int32_t rx_buff_load_done(uint16_t rx_len) { union sdio_slave_status sdio_sta; if (rx_len == 0) { @@ -310,32 +301,31 @@ static int32_t rx_buff_load_done(uint16_t rx_len) rx_len = rx_que.blocksize; } - //os_memcpy(rx_que.buf_ptr,data,rx_len); - /////config rx queue information + /* os_memcpy(rx_que.buf_ptr,data,rx_len); */ + /* config rx queue information */ rx_que.blocksize = RX_BUFFER_SIZE; rx_que.datalen = rx_len + SDIO_TOKEN_SIZE; rx_que.eof = 1; rx_que.owner = 1; - //ETS_SDIO_INTR_DISABLE(); - //available_buffer_amount--; + /* ETS_SDIO_INTR_DISABLE(); */ + /* available_buffer_amount--; */ - /////modify sdio status reg + /* modify sdio status reg */ sdio_sta.word_value = READ_PERI_REG(SLC_HOST_CONF_W2); sdio_sta.elm_value.rd_empty = 0; sdio_sta.elm_value.intr_no |= RX_AVAILIBLE; sdio_sta.elm_value.rx_length = rx_len; - SET_PERI_REG_MASK(SLC_RX_LINK, SLC_RXLINK_START); //rx buffer is ready for being read - WRITE_PERI_REG(SLC_HOST_CONF_W2, sdio_sta.word_value); //update sdio status register - //ETS_SDIO_INTR_ENABLE(); - //os_printf("rx_buff_load_done(%d,0x%08x):%s\r\n",rx_len,rx_que.buf_ptr,rx_que.buf_ptr); - //os_printf("rx_buff_load_done:%d\r\n",rx_len); + SET_PERI_REG_MASK(SLC_RX_LINK, SLC_RXLINK_START); /* rx buffer is ready for being read */ + WRITE_PERI_REG(SLC_HOST_CONF_W2, sdio_sta.word_value); /* update sdio status register */ + /* ETS_SDIO_INTR_ENABLE(); */ + /* os_printf("rx_buff_load_done(%d,0x%08x):%s\r\n",rx_len,rx_que.buf_ptr,rx_que.buf_ptr); */ + return rx_len; } -int32_t ICACHE_FLASH_ATTR sdio_load_data(const uint8_t *data, uint32_t len) -{ +int32_t ICACHE_FLASH_ATTR sdio_load_data(const uint8_t *data, uint32_t len) { int32_t data_len = 0; if (pHead_Sended == NULL) { @@ -353,7 +343,7 @@ int32_t ICACHE_FLASH_ATTR sdio_load_data(const uint8_t *data, uint32_t len) pHead_Sended->tail += len; len = 0; data_len += len; - //os_printf(">555:0x%08x,0x%08x\r\n",pHead_Sended->buffer,pHead_Sended->tail); + /* os_printf(">555:0x%08x,0x%08x\r\n",pHead_Sended->buffer,pHead_Sended->tail); */ } else { os_memcpy(pHead_Sended->tail, data, left_len); pHead_Sended->tail += left_len; @@ -377,12 +367,10 @@ int32_t ICACHE_FLASH_ATTR sdio_load_data(const uint8_t *data, uint32_t len) os_printf("buf full\r\n"); break; } - - //os_printf(">666\r\n"); } } - //os_printf(">>pHead_ToSend:0x%08x\r\n",pHead_ToSend); + /* os_printf(">>pHead_ToSend:0x%08x\r\n",pHead_ToSend); */ if (pHead_ToSend == NULL) { pTail_ToSend = pHead_Sended; @@ -390,28 +378,26 @@ int32_t ICACHE_FLASH_ATTR sdio_load_data(const uint8_t *data, uint32_t len) pHead_Sended = pHead_Sended->next; pTail_ToSend->next = NULL; - //system_os_post(2, 2, 0); + /* system_os_post(2, 2, 0); */ sdio_try_to_load(); } return data_len; } -static void sdio_try_to_load(void) -{ - if ((has_read == TRUE) && (pHead_ToSend != NULL)) { +static void sdio_try_to_load(void) { + if ((has_read == true) && (pHead_ToSend != NULL)) { rx_que.buf_ptr = (uint32_t)pHead_ToSend->buffer; rx_buff_load_done(pHead_ToSend->tail - pHead_ToSend->buffer - SDIO_TOKEN_SIZE); - //pHead_ToSend = pHead_ToSend->next; - has_read = FALSE; - //os_printf("SLC_INT_STATUS:0x%08x\r\n",READ_PERI_REG(SLC_INT_STATUS)); + /* pHead_ToSend = pHead_ToSend->next; */ + has_read = false; + /* os_printf("SLC_INT_STATUS:0x%08x\r\n",READ_PERI_REG(SLC_INT_STATUS)); */ TRIG_TOHOST_INT(); } } -static void sdio_read_done_process(void) -{ - has_read = TRUE; +static void sdio_read_done_process(void) { + has_read = true; pHead_ToSend->tail = pHead_ToSend->buffer + SDIO_TOKEN_SIZE; @@ -426,13 +412,13 @@ static void sdio_read_done_process(void) pHead_ToSend = pHead_ToSend->next; pTail_Sended->next = NULL; - //os_printf(">>pHead_ToSend:0x%08x,pHead_Sended:0x%08x,0x%08x,0x%08x\r\n",pHead_ToSend,pHead_Sended,pHead_Sended->buffer,pHead_Sended->tail); + /* os_printf(">>pHead_ToSend:0x%08x,pHead_Sended:0x%08x,0x%08x,0x%08x\r\n",pHead_ToSend,pHead_Sended,pHead_Sended->buffer,pHead_Sended->tail); */ if (pHead_ToSend) { rx_que.buf_ptr = (uint32_t)pHead_ToSend->buffer; rx_buff_load_done(pHead_ToSend->tail - pHead_ToSend->buffer - SDIO_TOKEN_SIZE); - has_read = FALSE; - //os_printf("intr trig\r\n"); - //TRIG_TOHOST_INT(); + has_read = false; + /* os_printf("intr trig\r\n"); + TRIG_TOHOST_INT(); */ } else if ((pHead_Sended != NULL) && (pHead_Sended->buffer != (pHead_Sended->tail - SDIO_TOKEN_SIZE))) { pHead_ToSend = pHead_Sended; pTail_ToSend = pHead_ToSend; @@ -441,18 +427,17 @@ static void sdio_read_done_process(void) rx_que.buf_ptr = (uint32_t)pHead_ToSend->buffer; rx_buff_load_done(pHead_ToSend->tail - pHead_ToSend->buffer - SDIO_TOKEN_SIZE); - has_read = FALSE; - //os_printf("intr trig\r\n"); - //TRIG_TOHOST_INT(); + has_read = false; + /* os_printf("intr trig\r\n"); + TRIG_TOHOST_INT(); */ } TRIG_TOHOST_INT(); } -bool sdio_register_recv_cb(sdio_recv_data_callback_t cb) -{ +bool sdio_register_recv_cb(sdio_recv_data_callback_t cb) { sdio_recv_data_callback_ptr = cb; - return TRUE; + return true; } diff --git a/driver_lib/driver/spi.c b/driver_lib/driver/spi.c index c0d9821f..ee87d802 100644 --- a/driver_lib/driver/spi.c +++ b/driver_lib/driver/spi.c @@ -21,13 +21,46 @@ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ +#include "gpio.h" +#include "user_interface.h" +#include "mem.h" #include "driver/spi.h" #include "driver/spi_overlap.h" +#define SPI_MISO +#define SPI_QUEUE_LEN 8 +#define MOSI 0 +#define MISO 1 +#define STATUS_R_IN_WR 2 +#define STATUS_W 3 +#define TR_DONE_ALONE 4 +#define WR_RD 5 +#define DATA_ERROR 6 +#define STATUS_R_IN_RD 7 + #define CACHE_FLASH_CTRL_REG 0x3ff0000C #define CACHE_FLUSH_START_BIT BIT0 #define CACHE_EMPTY_FLAG_BIT BIT1 + +static uint8_t spi_data[32] = {0}; +static uint8_t idx = 0; +static uint8_t spi_flg = 0; +os_event_t *spiQueue; + +/* init the two intr line of slave + gpio0: wr_ready ,and + gpio2: rd_ready , controlled by slave */ +void ICACHE_FLASH_ATTR gpio_init(void) { + + PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO0_U, FUNC_GPIO0); + PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, FUNC_GPIO2); + /* PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO4_U, FUNC_GPIO4); */ + GPIO_OUTPUT_SET(0, 1); + GPIO_OUTPUT_SET(2, 0); + /* GPIO_OUTPUT_SET(4, 1); */ +} + /****************************************************************************** * FunctionName : cache_flush * Description : clear all the cpu cache data for stability test. @@ -43,18 +76,18 @@ void cache_flush(void) CLEAR_PERI_REG_MASK(CACHE_FLASH_CTRL_REG, CACHE_FLUSH_START_BIT); } + /****************************************************************************** * FunctionName : spi_master_init * Description : SPI master initial function for common byte units transmission * Parameters : uint8_t spi_no - SPI module number, Only "SPI" and "HSPI" are valid *******************************************************************************/ -void ICACHE_FLASH_ATTR -spi_master_init(uint8_t spi_no) +void ICACHE_FLASH_ATTR spi_master_init(uint8_t spi_no) { uint32_t regvalue; if (spi_no > 1) { - return; //handle invalid input number + return; /*handle invalid input number */ } SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_CS_SETUP | SPI_CS_HOLD | SPI_USR_COMMAND); @@ -63,8 +96,9 @@ spi_master_init(uint8_t spi_no) WRITE_PERI_REG(SPI_CLOCK(spi_no), ((3 & SPI_CLKCNT_N) << SPI_CLKCNT_N_S) | ((1 & SPI_CLKCNT_H) << SPI_CLKCNT_H_S) | - ((3 & SPI_CLKCNT_L) << SPI_CLKCNT_L_S)); //clear bit 31,set SPI clock div + ((3 & SPI_CLKCNT_L) << SPI_CLKCNT_L_S)); /* clear bit 31,set SPI clock div */ } + /****************************************************************************** * FunctionName : spi_lcd_9bit_write * Description : SPI 9bits transmission function for driving LCD TM035PDZV36 @@ -72,14 +106,13 @@ spi_master_init(uint8_t spi_no) * uint8_t high_bit - first high bit of the data, 0 is for "0",the other value 1-255 is for "1" * uint8_t low_8bit- the rest 8bits of the data. *******************************************************************************/ -void ICACHE_FLASH_ATTR -spi_lcd_9bit_write(uint8_t spi_no, uint8_t high_bit, uint8_t low_8bit) +void ICACHE_FLASH_ATTR spi_lcd_9bit_write(uint8_t spi_no, uint8_t high_bit, uint8_t low_8bit) { uint32_t regvalue; uint8_t bytetemp; if (spi_no > 1) { - return; //handle invalid input number + return; /* handle invalid input number */ } if (high_bit) { @@ -88,39 +121,39 @@ spi_lcd_9bit_write(uint8_t spi_no, uint8_t high_bit, uint8_t low_8bit) bytetemp = (low_8bit >> 1) & 0x7f; } - regvalue = ((8 & SPI_USR_COMMAND_BITLEN) << SPI_USR_COMMAND_BITLEN_S) | ((uint32_t)bytetemp); //configure transmission variable,9bit transmission length and first 8 command bit + regvalue = ((8 & SPI_USR_COMMAND_BITLEN) << SPI_USR_COMMAND_BITLEN_S) | ((uint32_t)bytetemp); /* configure transmission variable,9bit transmission length and first 8 command bit */ if (low_8bit & 0x01) { - regvalue |= BIT15; //write the 9th bit + regvalue |= BIT15; /* write the 9th bit */ } - while (READ_PERI_REG(SPI_CMD(spi_no))&SPI_USR); //waiting for spi module available + while (READ_PERI_REG(SPI_CMD(spi_no))&SPI_USR); /* waiting for spi module available */ - WRITE_PERI_REG(SPI_USER2(spi_no), regvalue); //write command and command length into spi reg - SET_PERI_REG_MASK(SPI_CMD(spi_no), SPI_USR); //transmission start -// while(READ_PERI_REG(SPI_CMD(spi_no))&SPI_USR); + WRITE_PERI_REG(SPI_USER2(spi_no), regvalue); /* write command and command length into spi reg */ + SET_PERI_REG_MASK(SPI_CMD(spi_no), SPI_USR); /* transmission start */ +/* while(READ_PERI_REG(SPI_CMD(spi_no))&SPI_USR); */ } + /****************************************************************************** * FunctionName : spi_mast_byte_write * Description : SPI master 1 byte transmission function * Parameters : uint8_t spi_no - SPI module number, Only "SPI" and "HSPI" are valid * uint8_t data- transmitted data *******************************************************************************/ -void ICACHE_FLASH_ATTR -spi_mast_byte_write(uint8_t spi_no, uint8_t data) +void ICACHE_FLASH_ATTR spi_mast_byte_write(uint8_t spi_no, uint8_t data) { uint32_t regvalue; if (spi_no > 1) { - return; //handle invalid input number + return; /* handle invalid input number */ } while (READ_PERI_REG(SPI_CMD(spi_no))&SPI_USR); CLEAR_PERI_REG_MASK(SPI_USER(spi_no), SPI_USR_MOSI | SPI_USR_MISO); - //SPI_FLASH_USER2 bit28-31 is cmd length,cmd bit length is value(0-15)+1, - // bit15-0 is cmd value. + /*SPI_FLASH_USER2 bit28-31 is cmd length,cmd bit length is value(0-15)+1, + bit15-0 is cmd value. */ WRITE_PERI_REG(SPI_USER2(spi_no), ((7 & SPI_USR_COMMAND_BITLEN) << SPI_USR_COMMAND_BITLEN_S) | ((uint32_t)data)); SET_PERI_REG_MASK(SPI_CMD(spi_no), SPI_USR); @@ -136,13 +169,12 @@ spi_mast_byte_write(uint8_t spi_no, uint8_t data) * Parameters : uint8_t spi_no - SPI module number, Only "SPI" and "HSPI" are valid * uint8_t data- transmitted data *******************************************************************************/ -void ICACHE_FLASH_ATTR -spi_byte_write_espslave(uint8_t spi_no, uint8_t data) +void ICACHE_FLASH_ATTR spi_byte_write_espslave(uint8_t spi_no, uint8_t data) { uint32_t regvalue; if (spi_no > 1) { - return; //handle invalid input number + return; /* handle invalid input number */ } while (READ_PERI_REG(SPI_CMD(spi_no))&SPI_USR); @@ -150,14 +182,15 @@ spi_byte_write_espslave(uint8_t spi_no, uint8_t data) SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_USR_MOSI); CLEAR_PERI_REG_MASK(SPI_USER(spi_no), SPI_USR_MISO | SPI_USR_ADDR | SPI_USR_DUMMY); - //SPI_FLASH_USER2 bit28-31 is cmd length,cmd bit length is value(0-15)+1, - // bit15-0 is cmd value. - //0x70000000 is for 8bits cmd, 0x04 is eps8266 slave write cmd value + /* SPI_FLASH_USER2 bit28-31 is cmd length,cmd bit length is value(0-15)+1, + bit15-0 is cmd value. + 0x70000000 is for 8bits cmd, 0x04 is eps8266 slave write cmd value */ WRITE_PERI_REG(SPI_USER2(spi_no), ((7 & SPI_USR_COMMAND_BITLEN) << SPI_USR_COMMAND_BITLEN_S) | 4); WRITE_PERI_REG(SPI_W0(spi_no), (uint32_t)(data)); SET_PERI_REG_MASK(SPI_CMD(spi_no), SPI_USR); } + /****************************************************************************** * FunctionName : spi_byte_read_espslave * Description : SPI master 1 byte read function for esp8266 slave, @@ -166,22 +199,21 @@ spi_byte_write_espslave(uint8_t spi_no, uint8_t data) * Parameters : uint8_t spi_no - SPI module number, Only "SPI" and "HSPI" are valid * uint8_t* data- recieved data address *******************************************************************************/ -void ICACHE_FLASH_ATTR -spi_byte_read_espslave(uint8_t spi_no, uint8_t *data) +void ICACHE_FLASH_ATTR spi_byte_read_espslave(uint8_t spi_no, uint8_t *data) { uint32_t regvalue; if (spi_no > 1) { - return; //handle invalid input number + return; /* handle invalid input number */ } while (READ_PERI_REG(SPI_CMD(spi_no))&SPI_USR); SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_USR_MISO); CLEAR_PERI_REG_MASK(SPI_USER(spi_no), SPI_USR_MOSI | SPI_USR_ADDR | SPI_USR_DUMMY); - //SPI_FLASH_USER2 bit28-31 is cmd length,cmd bit length is value(0-15)+1, - // bit15-0 is cmd value. - //0x70000000 is for 8bits cmd, 0x06 is eps8266 slave read cmd value + /* SPI_FLASH_USER2 bit28-31 is cmd length,cmd bit length is value(0-15)+1, + bit15-0 is cmd value. + 0x70000000 is for 8bits cmd, 0x06 is eps8266 slave read cmd value */ WRITE_PERI_REG(SPI_USER2(spi_no), ((7 & SPI_USR_COMMAND_BITLEN) << SPI_USR_COMMAND_BITLEN_S) | 6); SET_PERI_REG_MASK(SPI_CMD(spi_no), SPI_USR); @@ -198,14 +230,13 @@ spi_byte_read_espslave(uint8_t spi_no, uint8_t *data) * Parameters : uint8_t spi_no - SPI module number, Only "SPI" and "HSPI" are valid * uint8_t data_len - read&write data pack length,using byte as unit,the range is 1-32 *******************************************************************************/ -void ICACHE_FLASH_ATTR -spi_slave_init(uint8_t spi_no, uint8_t data_len) +void ICACHE_FLASH_ATTR spi_slave_init(uint8_t spi_no, uint8_t data_len) { uint32_t regvalue; uint32_t data_bit_len; if (spi_no > 1) { - return; //handle invalid input number + return; /* handle invalid input number */ } if (data_len <= 1) { @@ -216,163 +247,86 @@ spi_slave_init(uint8_t spi_no, uint8_t data_len) data_bit_len = (data_len << 3) - 1; } - //clear bit9,bit8 of reg PERIPHS_IO_MUX - //bit9 should be cleared when HSPI clock doesn't equal CPU clock - //bit8 should be cleared when SPI clock doesn't equal CPU clock - ////WRITE_PERI_REG(PERIPHS_IO_MUX, 0x105); //clear bit9//TEST + /* clear bit9,bit8 of reg PERIPHS_IO_MUX + bit9 should be cleared when HSPI clock doesn't equal CPU clock + bit8 should be cleared when SPI clock doesn't equal CPU clock */ + /* WRITE_PERI_REG(PERIPHS_IO_MUX, 0x105); */ /* clear bit9 TEST */ if (spi_no == SPI) { - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, 1);//configure io to spi mode - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CMD_U, 1);//configure io to spi mode - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA0_U, 1);//configure io to spi mode - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA1_U, 1);//configure io to spi mode + PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, 1); /* configure io to spi mode */ + PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CMD_U, 1); + PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA0_U, 1); + PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA1_U, 1); } else if (spi_no == HSPI) { - PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDI_U, 2);//configure io to spi mode - PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, 2);//configure io to spi mode - PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTMS_U, 2);//configure io to spi mode - PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, 2);//configure io to spi mode + PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDI_U, 2);/* configure io to spi mode */ + PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, 2); + PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTMS_U, 2); + PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, 2); } - //regvalue=READ_PERI_REG(SPI_FLASH_SLAVE(spi_no)); - //slave mode,slave use buffers which are register "SPI_FLASH_C0~C15", enable trans done isr - //set bit 30 bit 29 bit9,bit9 is trans done isr mask + /* regvalue=READ_PERI_REG(SPI_FLASH_SLAVE(spi_no)); */ + /* slave mode,slave use buffers which are register "SPI_FLASH_C0~C15", enable trans done isr + //set bit 30 bit 29 bit9,bit9 is trans done isr mask */ SET_PERI_REG_MASK(SPI_SLAVE(spi_no), SPI_SLAVE_MODE | SPI_SLV_WR_RD_BUF_EN | SPI_SLV_WR_BUF_DONE_EN | SPI_SLV_RD_BUF_DONE_EN | SPI_SLV_WR_STA_DONE_EN | SPI_SLV_RD_STA_DONE_EN | SPI_TRANS_DONE_EN); - //disable general trans intr - //CLEAR_PERI_REG_MASK(SPI_SLAVE(spi_no),SPI_TRANS_DONE_EN); + /* disable general trans intr */ + /* CLEAR_PERI_REG_MASK(SPI_SLAVE(spi_no),SPI_TRANS_DONE_EN); */ - CLEAR_PERI_REG_MASK(SPI_USER(spi_no), SPI_FLASH_MODE);//disable flash operation mode - SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_USR_MISO_HIGHPART); //SLAVE SEND DATA BUFFER IN C8-C15 + CLEAR_PERI_REG_MASK(SPI_USER(spi_no), SPI_FLASH_MODE); /* disable flash operation mode */ + SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_USR_MISO_HIGHPART); /* SLAVE SEND DATA BUFFER IN C8-C15 */ -//////**************RUN WHEN SLAVE RECIEVE*******************/////// - //tow lines below is to configure spi timing. - SET_PERI_REG_MASK(SPI_CTRL2(spi_no), (0x2 & SPI_MOSI_DELAY_NUM) << SPI_MOSI_DELAY_NUM_S) ; //delay num +/**************RUN WHEN SLAVE RECEIVE*******************/ + /* two lines below is to configure spi timing. */ + SET_PERI_REG_MASK(SPI_CTRL2(spi_no), (0x2 & SPI_MOSI_DELAY_NUM) << SPI_MOSI_DELAY_NUM_S) ; /* delay num */ os_printf("SPI_CTRL2 is %08x\n", READ_PERI_REG(SPI_CTRL2(spi_no))); WRITE_PERI_REG(SPI_CLOCK(spi_no), 0); +/***************************************************/ +/* set 8 bit slave command length, because slave must have at least one bit addr, + 8 bit slave+8bit addr, so master device first 2 bytes can be regarded as a command + and the following bytes are datas, + 32 bytes input will be stored in SPI_FLASH_C0-C7 + 32 bytes output data should be set to SPI_FLASH_C8-C15 + */ + WRITE_PERI_REG(SPI_USER2(spi_no), (0x7 & SPI_USR_COMMAND_BITLEN) << SPI_USR_COMMAND_BITLEN_S); /* 0x70000000 */ -/////***************************************************////// - - //set 8 bit slave command length, because slave must have at least one bit addr, - //8 bit slave+8bit addr, so master device first 2 bytes can be regarded as a command - //and the following bytes are datas, - //32 bytes input wil be stored in SPI_FLASH_C0-C7 - //32 bytes output data should be set to SPI_FLASH_C8-C15 - WRITE_PERI_REG(SPI_USER2(spi_no), (0x7 & SPI_USR_COMMAND_BITLEN) << SPI_USR_COMMAND_BITLEN_S); //0x70000000 - - //set 8 bit slave recieve buffer length, the buffer is SPI_FLASH_C0-C7 - //set 8 bit slave status register, which is the low 8 bit of register "SPI_FLASH_STATUS" + /* set 8 bit slave recieve buffer length, the buffer is SPI_FLASH_C0-C7 + set 8 bit slave status register, which is the low 8 bit of register "SPI_FLASH_STATUS" */ SET_PERI_REG_MASK(SPI_SLAVE1(spi_no), ((data_bit_len & SPI_SLV_BUF_BITLEN) << SPI_SLV_BUF_BITLEN_S) | ((0x7 & SPI_SLV_STATUS_BITLEN) << SPI_SLV_STATUS_BITLEN_S) | ((0x7 & SPI_SLV_WR_ADDR_BITLEN) << SPI_SLV_WR_ADDR_BITLEN_S) | ((0x7 & SPI_SLV_RD_ADDR_BITLEN) << SPI_SLV_RD_ADDR_BITLEN_S)); - SET_PERI_REG_MASK(SPI_PIN(spi_no), BIT19); //BIT19 + SET_PERI_REG_MASK(SPI_PIN(spi_no), BIT19); - //maybe enable slave transmission liston + /* maybe enable slave transmission listen */ SET_PERI_REG_MASK(SPI_CMD(spi_no), SPI_USR); - //register level2 isr function, which contains spi, hspi and i2s events + /* register level2 isr function, which contains spi, hspi and i2s events */ ETS_SPI_INTR_ATTACH(spi_slave_isr_handler, NULL); - //enable level2 isr, which contains spi, hspi and i2s events + /* enable level2 isr, which contains spi, hspi and i2s events */ ETS_SPI_INTR_ENABLE(); } - - - - -/* ============================================================================================= - * code below is for spi slave r/w testcase with 2 r/w state lines connected to the spi master mcu - * replace with your own process functions - * find "add system_os_post here" in spi_slave_isr_handler. - * ============================================================================================= - */ - - - - - - - -#ifdef SPI_SLAVE_DEBUG -/****************************************************************************** -* FunctionName : hspi_master_readwrite_repeat -* Description : SPI master test function for reading and writing esp8266 slave buffer, - the function uses HSPI module -*******************************************************************************/ -os_timer_t timer2; - -void hspi_master_readwrite_repeat(void) -{ - static uint8_t data = 0; - uint8_t temp; - - os_timer_disarm(&timer2); - spi_byte_read_espslave(HSPI, &temp); - - temp++; - spi_byte_write_espslave(HSPI, temp); - os_timer_setfn(&timer2, (os_timer_func_t *)hspi_master_readwrite_repeat, NULL); - os_timer_arm(&timer2, 500, 0); -} -#endif - - /****************************************************************************** * FunctionName : spi_slave_isr_handler * Description : SPI interrupt function, SPI HSPI and I2S interrupt can trig this function some basic operation like clear isr flag has been done, - and it is availible for adding user coder in the funtion + and it is available for adding user coder in the function * Parameters : void *para- function parameter address, which has been registered in function spi_slave_init *******************************************************************************/ -#include "gpio.h" -#include "user_interface.h" -#include "mem.h" -static uint8_t spi_data[32] = {0}; -static uint8_t idx = 0; -static uint8_t spi_flg = 0; -#define SPI_MISO -#define SPI_QUEUE_LEN 8 -os_event_t *spiQueue; -#define MOSI 0 -#define MISO 1 -#define STATUS_R_IN_WR 2 -#define STATUS_W 3 -#define TR_DONE_ALONE 4 -#define WR_RD 5 -#define DATA_ERROR 6 -#define STATUS_R_IN_RD 7 -//init the two intr line of slave -//gpio0: wr_ready ,and -//gpio2: rd_ready , controlled by slave -void ICACHE_FLASH_ATTR -gpio_init() -{ - - PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO0_U, FUNC_GPIO0); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, FUNC_GPIO2); - //PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO4_U, FUNC_GPIO4); - GPIO_OUTPUT_SET(0, 1); - GPIO_OUTPUT_SET(2, 0); - //GPIO_OUTPUT_SET(4, 1); -} - - - -void spi_slave_isr_handler(void *para) -{ +void spi_slave_isr_handler(void *para) { uint32_t regvalue, calvalue; static uint8_t state = 0; uint32_t recv_data, send_data; if (READ_PERI_REG(0x3ff00020)&BIT4) { - //following 3 lines is to clear isr signal + /* following 3 lines is to clear isr signal */ CLEAR_PERI_REG_MASK(SPI_SLAVE(SPI), 0x3ff); - } else if (READ_PERI_REG(0x3ff00020)&BIT7) { //bit7 is for hspi isr, + } else if (READ_PERI_REG(0x3ff00020)&BIT7) { /* bit7 is for hspi isr, */ regvalue = READ_PERI_REG(SPI_SLAVE(HSPI)); CLEAR_PERI_REG_MASK(SPI_SLAVE(HSPI), SPI_TRANS_DONE_EN | @@ -406,30 +360,52 @@ void spi_slave_isr_handler(void *para) spi_data[(idx << 2) + 3] = (recv_data >> 24) & 0xff; idx++; } - - //add system_os_post here GPIO_OUTPUT_SET(0, 1); } if (regvalue & SPI_SLV_RD_BUF_DONE) { - //it is necessary to call GPIO_OUTPUT_SET(2, 1), when new data is preped in SPI_W8-15 and needs to be sended. + /* it is necessary to call GPIO_OUTPUT_SET(2, 1), when new data is preped in SPI_W8-15 and needs to be sended. */ GPIO_OUTPUT_SET(2, 0); - //add system_os_post here - //system_os_post(USER_TASK_PRIO_1,WR_RD,regvalue); + /*add system_os_post here */ + /* system_os_post(USER_TASK_PRIO_1, WR_RD, regvalue); */ } - } else if (READ_PERI_REG(0x3ff00020)&BIT9) { //bit7 is for i2s isr, + } else if (READ_PERI_REG(0x3ff00020)&BIT9) { } } +/* ============================================================================================= + * code below is for spi slave r/w testcase with 2 r/w state lines connected to the spi master mcu + * replace with your own process functions + * find "add system_os_post here" in spi_slave_isr_handler. + * ============================================================================================= + */ + #ifdef SPI_SLAVE_DEBUG +/****************************************************************************** +* FunctionName : hspi_master_readwrite_repeat +* Description : SPI master test function for reading and writing esp8266 slave buffer, + the function uses HSPI module +*******************************************************************************/ +os_timer_t timer2; -void ICACHE_FLASH_ATTR -set_miso_data() -{ +void hspi_master_readwrite_repeat(void) { + static uint8_t data = 0; + uint8_t temp; + + os_timer_disarm(&timer2); + spi_byte_read_espslave(HSPI, &temp); + + temp++; + spi_byte_write_espslave(HSPI, temp); + os_timer_setfn(&timer2, (os_timer_func_t *)hspi_master_readwrite_repeat, NULL); + os_timer_arm(&timer2, 500, 0); +} + +void ICACHE_FLASH_ATTR set_miso_data(void) { if (GPIO_INPUT_GET(2) == 0) { WRITE_PERI_REG(SPI_W8(HSPI), 0x05040302); WRITE_PERI_REG(SPI_W9(HSPI), 0x09080706); @@ -444,24 +420,17 @@ set_miso_data() } } - - -void ICACHE_FLASH_ATTR -disp_spi_data() -{ +void ICACHE_FLASH_ATTR disp_spi_data(void) { uint8_t i = 0; for (i = 0; i < 32; i++) { os_printf("data %d : 0x%02x\n\r", i, spi_data[i]); } - //os_printf("d31:0x%02x\n\r",spi_data[31]); + /* os_printf("d31:0x%02x\n\r",spi_data[31]); */ } - -void ICACHE_FLASH_ATTR -spi_task(os_event_t *e) -{ +void ICACHE_FLASH_ATTR spi_task(os_event_t *e) { uint8_t data; switch (e->sig) { @@ -498,8 +467,7 @@ spi_task(os_event_t *e) } } -void ICACHE_FLASH_ATTR -spi_task_init(void) +void ICACHE_FLASH_ATTR spi_task_init(void) { spiQueue = (os_event_t *)os_malloc(sizeof(os_event_t) * SPI_QUEUE_LEN); system_os_task(spi_task, USER_TASK_PRIO_1, spiQueue, SPI_QUEUE_LEN); @@ -507,9 +475,7 @@ spi_task_init(void) os_timer_t spi_timer_test; -void ICACHE_FLASH_ATTR -spi_test_init() -{ +void ICACHE_FLASH_ATTR spi_test_init(void) { os_printf("spi init\n\r"); spi_slave_init(HSPI); os_printf("gpio init\n\r"); @@ -521,11 +487,9 @@ spi_test_init() set_miso_data(); #endif - //os_timer_disarm(&spi_timer_test); - //os_timer_setfn(&spi_timer_test, (os_timer_func_t *)set_miso_data, NULL);//wjl - //os_timer_arm(&spi_timer_test,50,1); + /* os_timer_disarm(&spi_timer_test); + os_timer_setfn(&spi_timer_test, (os_timer_func_t *)set_miso_data, NULL);//wjl + os_timer_arm(&spi_timer_test,50,1); */ } #endif - - diff --git a/driver_lib/driver/spi_interface.c b/driver_lib/driver/spi_interface.c index b54ce877..35b4f920 100644 --- a/driver_lib/driver/spi_interface.c +++ b/driver_lib/driver/spi_interface.c @@ -21,47 +21,26 @@ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - -/** - * @file spi_interface.c - * @brief Defines and Macros for the SPI. - */ - -#include "osapi.h" #include "ets_sys.h" +#include "osapi.h" #include "driver/spi_interface.h" -//***************************************************************************** -// -// Make sure all of the definitions in this header have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -/** - * @brief Based on pAttr initialize SPI module. - * - */ -void ICACHE_FLASH_ATTR SPIInit(SpiNum spiNum, SpiAttr *pAttr) -{ +void ICACHE_FLASH_ATTR spi_init(SpiNum spiNum, SpiAttr *pAttr) { if ((spiNum > SpiNum_HSPI) || (NULL == pAttr)) { return; } - // SPI_CPOL & SPI_CPHA + /* SPI_CPOL & SPI_CPHA */ switch (pAttr->subMode) { case SpiSubMode_1: CLEAR_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE); - SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE); // CHPA_FALLING_EDGE_SAMPLE + SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE); /* CHPA_FALLING_EDGE_SAMPLE */ break; case SpiSubMode_2: SET_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE); - SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE); // CHPA_FALLING_EDGE_SAMPLE + SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE); /* CHPA_FALLING_EDGE_SAMPLE */ break; case SpiSubMode_3: @@ -73,11 +52,9 @@ void ICACHE_FLASH_ATTR SPIInit(SpiNum spiNum, SpiAttr *pAttr) default: CLEAR_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE); CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE); - // To do nothing break; } - // SPI bit order if (SpiBitOrder_MSBFirst == pAttr->bitOrder) { CLEAR_PERI_REG_MASK(SPI_CTRL(spiNum), SPI_WR_BIT_ORDER); CLEAR_PERI_REG_MASK(SPI_CTRL(spiNum), SPI_RD_BIT_ORDER); @@ -85,21 +62,18 @@ void ICACHE_FLASH_ATTR SPIInit(SpiNum spiNum, SpiAttr *pAttr) SET_PERI_REG_MASK(SPI_CTRL(spiNum), SPI_WR_BIT_ORDER); SET_PERI_REG_MASK(SPI_CTRL(spiNum), SPI_RD_BIT_ORDER); } else { - // To do nothing } - // Disable flash operation mode - // As earlier as better, if not SPI_CTRL2 can not to be set delay cycles. + /* Disable flash operation mode + As earlier as better, if not SPI_CTRL2 can not to be set delay cycles. */ CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_FLASH_MODE); - // SPI mode type if (SpiMode_Master == pAttr->mode) { - // SPI mode type + /* SPI mode type */ CLEAR_PERI_REG_MASK(SPI_SLAVE(spiNum), SPI_SLAVE_MODE); - // SPI Send buffer - CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO_HIGHPART); // By default slave send buffer C0-C7 + CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO_HIGHPART); /* By default slave send buffer C0-C7 */ - // SPI Speed + /* SPI Speed */ if (1 < (pAttr->speed)) { uint8_t i, k; i = (pAttr->speed / 40) ? (pAttr->speed / 40) : 1; @@ -109,33 +83,30 @@ void ICACHE_FLASH_ATTR SPIInit(SpiNum spiNum, SpiAttr *pAttr) (((i - 1) & SPI_CLKDIV_PRE) << SPI_CLKDIV_PRE_S) | (((k - 1) & SPI_CLKCNT_N) << SPI_CLKCNT_N_S) | ((((k + 1) / 2 - 1) & SPI_CLKCNT_H) << SPI_CLKCNT_H_S) | - (((k - 1) & SPI_CLKCNT_L) << SPI_CLKCNT_L_S)); //clear bit 31,set SPI clock div + (((k - 1) & SPI_CLKCNT_L) << SPI_CLKCNT_L_S)); /* clear bit 31,set SPI clock div */ } else { - WRITE_PERI_REG(SPI_CLOCK(spiNum), SPI_CLK_EQU_SYSCLK); // 80Mhz speed + WRITE_PERI_REG(SPI_CLOCK(spiNum), SPI_CLK_EQU_SYSCLK); /* 80Mhz speed */ } - // By default format:CMD+ADDR+DATA + /* By default format:CMD+ADDR+DATA */ SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CS_SETUP | SPI_CS_HOLD | SPI_USR_MOSI); - - //delay num SET_PERI_REG_MASK(SPI_CTRL2(spiNum), ((0x1 & SPI_MISO_DELAY_NUM) << SPI_MISO_DELAY_NUM_S)); } else if (SpiMode_Slave == pAttr->mode) { - // BIT19 must do + /* BIT19 must do */ SET_PERI_REG_MASK(SPI_PIN(spiNum), BIT19); - // SPI mode type + /* SPI mode type */ SET_PERI_REG_MASK(SPI_SLAVE(spiNum), SPI_SLAVE_MODE); - // SPI Send buffer - SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO_HIGHPART);// By default slave send buffer C8-C15 + SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO_HIGHPART); /* By default slave send buffer C8-C15 */ SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI); - // If do not set delay cycles, slave not working,master cann't get the data. - SET_PERI_REG_MASK(SPI_CTRL2(spiNum), ((0x1 & SPI_MOSI_DELAY_NUM) << SPI_MOSI_DELAY_NUM_S)); //delay num - // SPI Speed + /* If do not set delay cycles, slave not working,master cann't get the data. */ + SET_PERI_REG_MASK(SPI_CTRL2(spiNum), ((0x1 & SPI_MOSI_DELAY_NUM) << SPI_MOSI_DELAY_NUM_S)); + /* SPI Speed */ WRITE_PERI_REG(SPI_CLOCK(spiNum), 0); - // By default format::CMD(8bits)+ADDR(8bits)+DATA(32bytes). + /* By default format::CMD(8bits)+ADDR(8bits)+DATA(32bytes) */ SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_BITLEN, 7, SPI_USR_COMMAND_BITLEN_S); SET_PERI_REG_BITS(SPI_SLAVE1(spiNum), SPI_SLV_WR_ADDR_BITLEN, @@ -144,16 +115,15 @@ void ICACHE_FLASH_ATTR SPIInit(SpiNum spiNum, SpiAttr *pAttr) 7, SPI_SLV_RD_ADDR_BITLEN_S); SET_PERI_REG_BITS(SPI_SLAVE1(spiNum), SPI_SLV_BUF_BITLEN, (32 * 8 - 1), SPI_SLV_BUF_BITLEN_S); - // For 8266 work on slave mode. + /* For 8266 work on slave mode */ SET_PERI_REG_BITS(SPI_SLAVE1(spiNum), SPI_SLV_STATUS_BITLEN, 7, SPI_SLV_STATUS_BITLEN_S); } else { - // To do nothing } - //clear Daul or Quad lines transmission mode + /* clear Dual or Quad lines transmission mode */ CLEAR_PERI_REG_MASK(SPI_CTRL(spiNum), SPI_QIO_MODE | SPI_DIO_MODE | SPI_DOUT_MODE | SPI_QOUT_MODE); - // Clear the data buffer. + /* Clear the data buffer */ uint8_t i; uint32_t regAddr = REG_SPI_BASE(spiNum) + 0x40; @@ -161,44 +131,26 @@ void ICACHE_FLASH_ATTR SPIInit(SpiNum spiNum, SpiAttr *pAttr) WRITE_PERI_REG(regAddr, 0); regAddr += 4; } - } -/** - * @brief Set address value by master mode. - * - */ -void ICACHE_FLASH_ATTR SPIMasterCfgAddr(SpiNum spiNum, uint32_t addr) -{ +void ICACHE_FLASH_ATTR spi_master_config_addr(SpiNum spiNum, uint32_t addr) { if (spiNum > SpiNum_HSPI) { return; } - - // Set address WRITE_PERI_REG(SPI_ADDR(spiNum), addr); } -/** - * @brief Set command value by master mode. - * - */ -void ICACHE_FLASH_ATTR SPIMasterCfgCmd(SpiNum spiNum, uint32_t cmd) -{ +void ICACHE_FLASH_ATTR spi_master_config_cmd(SpiNum spiNum, uint32_t cmd) { if (spiNum > SpiNum_HSPI) { return; } - // SPI_USER2 bit28-31 is cmd length,cmd bit length is value(0-15)+1, - // bit15-0 is cmd value. + /* SPI_USER2 bit28-31 is cmd length,cmd bit length is value(0-15)+1, + bit15-0 is cmd value */ SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_VALUE, cmd, SPI_USR_COMMAND_VALUE_S); } -/** - * @brief Send data to slave. - * - */ -int32_t ICACHE_FLASH_ATTR SPIMasterSendData(SpiNum spiNum, SpiData *pInData) -{ +int32_t ICACHE_FLASH_ATTR spi_master_send_data(SpiNum spiNum, SpiData *pInData) { char idx = 0; if ((spiNum > SpiNum_HSPI) @@ -211,22 +163,21 @@ int32_t ICACHE_FLASH_ATTR SPIMasterSendData(SpiNum spiNum, SpiData *pInData) while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR); - // Set command by user. + /* Set command */ if (pInData->cmdLen != 0) { - // Max command length 16 bits. + /* Max command length 16 bits */ SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_BITLEN, ((pInData->cmdLen << 3) - 1), SPI_USR_COMMAND_BITLEN_S); - // Enable command + /* Enable and load command */ SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_COMMAND); - // Load command - SPIMasterCfgCmd(spiNum, pInData->cmd); + spi_master_config_cmd(spiNum, pInData->cmd); } else { CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_COMMAND); SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_BITLEN, 0, SPI_USR_COMMAND_BITLEN_S); } - // Set Address by user. + /* Set address */ if (pInData->addrLen == 0) { CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_ADDR); SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_ADDR_BITLEN, @@ -238,28 +189,27 @@ int32_t ICACHE_FLASH_ATTR SPIMasterSendData(SpiNum spiNum, SpiData *pInData) SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_ADDR_BITLEN, ((pInData->addrLen << 3) - 1), SPI_USR_ADDR_BITLEN_S); - // Enable address + /* Enable and load address */ SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_ADDR); - // Load address - SPIMasterCfgAddr(spiNum, *pInData->addr); + spi_master_config_addr(spiNum, *pInData->addr); } - // Set data by user. + /* Set data */ if (pInData->dataLen != 0) { if (NULL == value) { return -1; } - // Enable MOSI + /* Enable MOSI */ SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI); CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO); - // Load send buffer + /* Load send buffer */ do { WRITE_PERI_REG((SPI_W0(spiNum) + (idx << 2)), *value++); } while (++idx < ((pInData->dataLen / 4) + ((pInData->dataLen % 4) ? 1 : 0))); - // Set data send buffer length.Max data length 64 bytes. + /* Set data send buffer length.Max data length 64 bytes. */ SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MOSI_BITLEN, ((pInData->dataLen << 3) - 1), SPI_USR_MOSI_BITLEN_S); } else { CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI); @@ -267,10 +217,10 @@ int32_t ICACHE_FLASH_ATTR SPIMasterSendData(SpiNum spiNum, SpiData *pInData) 0, SPI_USR_MOSI_BITLEN_S); } - // Start send data + /* Start send */ SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR); - // Wait for transmit done + /* Wait for transmit done */ while (!(READ_PERI_REG(SPI_SLAVE(spiNum))&SPI_TRANS_DONE)); CLEAR_PERI_REG_MASK(SPI_SLAVE(spiNum), SPI_TRANS_DONE); @@ -281,8 +231,7 @@ int32_t ICACHE_FLASH_ATTR SPIMasterSendData(SpiNum spiNum, SpiData *pInData) * @brief Receive data from slave. * */ -int32_t ICACHE_FLASH_ATTR SPIMasterRecvData(SpiNum spiNum, SpiData *pOutData) -{ +int32_t ICACHE_FLASH_ATTR spi_master_recv_data(SpiNum spiNum, SpiData *pOutData) { char idx = 0; if ((spiNum > SpiNum_HSPI) @@ -294,22 +243,21 @@ int32_t ICACHE_FLASH_ATTR SPIMasterRecvData(SpiNum spiNum, SpiData *pOutData) while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR); - // Set command by user. + /* Set command */ if (pOutData->cmdLen != 0) { - // Max command length 16 bits. + /* Max command length 16 bits. */ SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_BITLEN, ((pOutData->cmdLen << 3) - 1), SPI_USR_COMMAND_BITLEN_S); - // Enable command + /* Enable and load command */ SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_COMMAND); - // Load command - SPIMasterCfgCmd(spiNum, pOutData->cmd); + spi_master_config_cmd(spiNum, pOutData->cmd); } else { CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_COMMAND); SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_BITLEN, 0, SPI_USR_COMMAND_BITLEN_S); } - // Set Address by user. + /* Set Address */ if (pOutData->addrLen == 0) { CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_ADDR); SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_ADDR_BITLEN, @@ -321,23 +269,22 @@ int32_t ICACHE_FLASH_ATTR SPIMasterRecvData(SpiNum spiNum, SpiData *pOutData) SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_ADDR_BITLEN, ((pOutData->addrLen << 3) - 1), SPI_USR_ADDR_BITLEN_S); - // Enable address + /* Enable and load address */ SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_ADDR); - // Load address - SPIMasterCfgAddr(spiNum, *pOutData->addr); + spi_master_config_addr(spiNum, *pOutData->addr); } - // Set data by user. + /* Set data */ if (pOutData->dataLen != 0) { if (NULL == value) { return -1; } - // Clear MOSI enable + /* Clear MOSI enable */ CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI); - // Enable MOSI + /* Enable MOSI */ SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO); - // Set data send buffer length.Max data length 64 bytes. + /* Set data send buffer length.Max data length 64 bytes. */ SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MISO_BITLEN, ((pOutData->dataLen << 3) - 1), SPI_USR_MISO_BITLEN_S); } else { CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI); @@ -346,17 +293,16 @@ int32_t ICACHE_FLASH_ATTR SPIMasterRecvData(SpiNum spiNum, SpiData *pOutData) 0, SPI_USR_MISO_BITLEN_S); } - // Start send data + /* Start send */ SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR); while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR); - // Read data out + /* Read data out */ do { *value++ = READ_PERI_REG(SPI_W0(spiNum) + (idx << 2)); } while (++idx < ((pOutData->dataLen / 4) + ((pOutData->dataLen % 4) ? 1 : 0))); - return 0; } @@ -364,8 +310,7 @@ int32_t ICACHE_FLASH_ATTR SPIMasterRecvData(SpiNum spiNum, SpiData *pOutData) * @brief Load data to send buffer by slave mode. * */ -int32_t ICACHE_FLASH_ATTR SPISlaveSendData(SpiNum spiNum, uint32_t *pInData, uint8_t inLen) -{ +int32_t ICACHE_FLASH_ATTR spi_slave_send_data(SpiNum spiNum, uint32_t *pInData, uint8_t inLen) { if (NULL == pInData) { return -1; } @@ -377,22 +322,21 @@ int32_t ICACHE_FLASH_ATTR SPISlaveSendData(SpiNum spiNum, uint32_t *pInData, uin WRITE_PERI_REG((SPI_W8(spiNum) + (i << 2)), *value++); } - // Enable slave transmission liston + /* Enable slave transmission listen */ SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR); return 0; } /** - * @brief Configurate slave prepare for receive data. + * @brief Configure slave prepare for receive data. * */ -int32_t ICACHE_FLASH_ATTR SPISlaveRecvData(SpiNum spiNum) -{ +int32_t ICACHE_FLASH_ATTR spi_slave_recv_data(SpiNum spiNum) { if ((spiNum > SpiNum_HSPI)) { return -1; } - // Enable slave transmission liston + /* Enable slave transmission listen */ SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR); return 0; @@ -402,28 +346,27 @@ int32_t ICACHE_FLASH_ATTR SPISlaveRecvData(SpiNum spiNum) * @brief Send data to slave(ESP8266 register of RD_STATUS or WR_STATUS). * */ -void ICACHE_FLASH_ATTR SPIMasterSendStatus(SpiNum spiNum, uint8_t data) -{ +void ICACHE_FLASH_ATTR spi_master_send_status(SpiNum spiNum, uint8_t data) { if (spiNum > SpiNum_HSPI) { return; } while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR); - // Enable MOSI + /* Enable MOSI */ SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI); CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO | SPI_USR_DUMMY | SPI_USR_ADDR); - // 8bits cmd, 0x04 is eps8266 slave write cmd value + /* 8bits cmd, 0x04 is eps8266 slave write cmd value */ WRITE_PERI_REG(SPI_USER2(spiNum), ((7 & SPI_USR_COMMAND_BITLEN) << SPI_USR_COMMAND_BITLEN_S) | MASTER_WRITE_STATUS_TO_SLAVE_CMD); - // Set data send buffer length. + /* Set data send buffer length. */ SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MOSI_BITLEN, ((sizeof(data) << 3) - 1), SPI_USR_MOSI_BITLEN_S); WRITE_PERI_REG(SPI_W0(spiNum), (uint32_t)(data)); - // Start SPI + /* Start SPI */ SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR); } @@ -432,27 +375,26 @@ void ICACHE_FLASH_ATTR SPIMasterSendStatus(SpiNum spiNum, uint8_t data) * @brief Receive status register from slave(ESP8266). * */ -int32_t ICACHE_FLASH_ATTR SPIMasterRecvStatus(SpiNum spiNum) -{ +int32_t ICACHE_FLASH_ATTR spi_master_recv_status(SpiNum spiNum) { if (spiNum > SpiNum_HSPI) { return -1; } while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR); - // Enable MISO + /* Enable MISO */ SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO); CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI | SPI_USR_DUMMY | SPI_USR_ADDR); - // 8bits cmd, 0x06 is eps8266 slave read status cmd value + /* 8bits cmd, 0x06 is eps8266 slave read status cmd value */ WRITE_PERI_REG(SPI_USER2(spiNum), ((7 & SPI_USR_COMMAND_BITLEN) << SPI_USR_COMMAND_BITLEN_S) | MASTER_READ_STATUS_FROM_SLAVE_CMD); - // Set revcive buffer length. + /* Set receive buffer length. */ SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MISO_BITLEN, 7, SPI_USR_MISO_BITLEN_S); - // start spi module. + /* start SPI */ SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR); while (READ_PERI_REG(SPI_CMD(spiNum))&SPI_USR); @@ -466,42 +408,36 @@ int32_t ICACHE_FLASH_ATTR SPIMasterRecvStatus(SpiNum spiNum) * @brief Select SPI CS pin. * */ -void ICACHE_FLASH_ATTR SPICsPinSelect(SpiNum spiNum, SpiPinCS pinCs) -{ +void ICACHE_FLASH_ATTR spi_cs_pin_select(SpiNum spiNum, SpiPinCS pinCs) { if (spiNum > SpiNum_HSPI) { return; } - // clear select SET_PERI_REG_BITS(SPI_PIN(spiNum), 3, 0, 0); SET_PERI_REG_MASK(SPI_PIN(spiNum), pinCs); } - -void SPIIntCfg(SpiNum spiNum, SpiIntInfo *pIntInfo) -{ +void spi_int_cfg(SpiNum spiNum, SpiIntInfo *pIntInfo) { if ((spiNum > SpiNum_HSPI) || (NULL == pIntInfo)) { return; } - // Clear the interrupt source and disable all of the interrupt. + /* Clear the interrupt source and disable all of the interrupt. */ CLEAR_PERI_REG_MASK(SPI_SLAVE(spiNum), 0x3FF); - SPIIntEnable(spiNum, pIntInfo->src); + spi_int_enable(spiNum, pIntInfo->src); os_printf("src=%x\r\n,isrFunc=%x", (pIntInfo->src << 5), pIntInfo->isrFunc); - // + + /* set and enable ISR */ ETS_SPI_INTR_ATTACH(pIntInfo->isrFunc, NULL); - // Enable isr ETS_SPI_INTR_ENABLE(); } - /** * @brief Enable SPI interrupt source. * */ -void ICACHE_FLASH_ATTR SPIIntEnable(SpiNum spiNum, SpiIntSrc intSrc) -{ +void ICACHE_FLASH_ATTR spi_int_enable(SpiNum spiNum, SpiIntSrc intSrc) { if (spiNum > SpiNum_HSPI) { return; } @@ -513,8 +449,7 @@ void ICACHE_FLASH_ATTR SPIIntEnable(SpiNum spiNum, SpiIntSrc intSrc) * @brief Disable SPI interrupt source. * */ -void ICACHE_FLASH_ATTR SPIIntDisable(SpiNum spiNum, SpiIntSrc intSrc) -{ +void ICACHE_FLASH_ATTR spi_int_disable(SpiNum spiNum, SpiIntSrc intSrc) { if (spiNum > SpiNum_HSPI) { return; } @@ -526,8 +461,7 @@ void ICACHE_FLASH_ATTR SPIIntDisable(SpiNum spiNum, SpiIntSrc intSrc) * @brief Clear all of SPI interrupt source. * */ -void ICACHE_FLASH_ATTR SPIIntClear(SpiNum spiNum) -{ +void ICACHE_FLASH_ATTR spi_int_clear(SpiNum spiNum) { if (spiNum > SpiNum_HSPI) { return; } @@ -538,8 +472,3 @@ void ICACHE_FLASH_ATTR SPIIntClear(SpiNum spiNum) | SpiIntSrc_WrBufDone | SpiIntSrc_RdBufDone); } - - -#ifdef __cplusplus -} -#endif diff --git a/driver_lib/driver/spi_overlap.c b/driver_lib/driver/spi_overlap.c index 169fd48d..90bf88d5 100644 --- a/driver_lib/driver/spi_overlap.c +++ b/driver_lib/driver/spi_overlap.c @@ -22,9 +22,9 @@ * */ -#include "driver/spi_overlap.h" -#include "driver/spi.h" #include "gpio.h" +#include "driver/spi.h" +#include "driver/spi_overlap.h" #define SPI_FLASH_READ_MODE_MASK 0x196000 #define WAIT_HSPI_IDLE() while(READ_PERI_REG(SPI_EXT2(HSPI))||(READ_PERI_REG(SPI_CMD(HSPI))&0xfffc0000)); @@ -41,32 +41,30 @@ #define DISABLE_HSPI_DEV_CS() GPIO_OUTPUT_SET(15, 1);\ PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_GPIO15) struct hspi_device_register hspi_dev_reg; + /****************************************************************************** * FunctionName : hspi_overlap_init * Description : enable hspi and spi module overlap mode *******************************************************************************/ -void ICACHE_FLASH_ATTR -hspi_overlap_init(void) -{ - //hspi overlap to spi, two spi masters on cspi +void ICACHE_FLASH_ATTR hspi_overlap_init(void) { + /* hspi overlap to spi, two spi masters on cspi */ SET_PERI_REG_MASK(HOST_INF_SEL, reg_cspi_overlap); - //set higher priority for spi than hspi + /* set higher priority for spi than hspi */ SET_PERI_REG_MASK(SPI_EXT3(SPI), 0x1); SET_PERI_REG_MASK(SPI_EXT3(HSPI), 0x3); SET_PERI_REG_MASK(SPI_USER(HSPI), BIT(5)); } + /****************************************************************************** * FunctionName : hspi_overlap_deinit * Description : recover hspi and spi module from overlap mode *******************************************************************************/ -void ICACHE_FLASH_ATTR -hspi_overlap_deinit(void) -{ - //hspi overlap to spi, two spi masters on cspi +void ICACHE_FLASH_ATTR hspi_overlap_deinit(void) { + /* hspi overlap to spi, two spi masters on cspi */ CLEAR_PERI_REG_MASK(HOST_INF_SEL, reg_cspi_overlap); - //set higher priority for spi than hspi + /* set higher priority for spi than hspi */ CLEAR_PERI_REG_MASK(SPI_EXT3(SPI), 0x1); CLEAR_PERI_REG_MASK(SPI_EXT3(HSPI), 0x3); CLEAR_PERI_REG_MASK(SPI_USER(HSPI), BIT(5)); @@ -77,11 +75,9 @@ hspi_overlap_deinit(void) * Description : backup SPI normal operation register value and disable CPU cache to modify some flash registers. * Parameters : uint8_t spi_no - SPI module number, Only "SPI" and "HSPI" are valid *******************************************************************************/ -void ICACHE_FLASH_ATTR -spi_reg_backup(uint8_t spi_no, uint32_t *backup_mem) -{ +void ICACHE_FLASH_ATTR spi_reg_backup(uint8_t spi_no, uint32_t *backup_mem) { if (spi_no > 1) { - return; //handle invalid input number + return; } backup_mem[PERIPHS_IO_MUX_BACKUP] = READ_PERI_REG(PERIPHS_IO_MUX); @@ -94,19 +90,18 @@ spi_reg_backup(uint8_t spi_no, uint32_t *backup_mem) backup_mem[SPI_PIN_BACKUP] = READ_PERI_REG(SPI_PIN(spi_no)); backup_mem[SPI_SLAVE_BACKUP] = READ_PERI_REG(SPI_SLAVE(spi_no)); } + /****************************************************************************** * FunctionName : spi_reg_recover * Description : recover SPI normal operation register value and enable CPU cache. * Parameters : uint8_t spi_no - SPI module number, Only "SPI" and "HSPI" are valid *******************************************************************************/ -void ICACHE_FLASH_ATTR -spi_reg_recover(uint8_t spi_no, uint32_t *backup_mem) -{ +void ICACHE_FLASH_ATTR spi_reg_recover(uint8_t spi_no, uint32_t *backup_mem) { if (spi_no > 1) { - return; //handle invalid input number + return; } -// WRITE_PERI_REG(PERIPHS_IO_MUX, backup_mem[PERIPHS_IO_MUX_BACKUP]); +/* WRITE_PERI_REG(PERIPHS_IO_MUX, backup_mem[PERIPHS_IO_MUX_BACKUP]); */ WRITE_PERI_REG(SPI_USER(spi_no), backup_mem[SPI_USER_BACKUP]); WRITE_PERI_REG(SPI_CTRL(spi_no), backup_mem[SPI_CTRL_BACKUP]); WRITE_PERI_REG(SPI_CLOCK(spi_no), backup_mem[SPI_CLOCK_BACKUP]); @@ -114,12 +109,10 @@ spi_reg_recover(uint8_t spi_no, uint32_t *backup_mem) WRITE_PERI_REG(SPI_USER2(spi_no), backup_mem[SPI_USER2_BACKUP]); WRITE_PERI_REG(SPI_CMD(spi_no), backup_mem[SPI_CMD_BACKUP]); WRITE_PERI_REG(SPI_PIN(spi_no), backup_mem[SPI_PIN_BACKUP]); -// WRITE_PERI_REG(SPI_SLAVE(spi_no), backup_mem[SPI_SLAVE_BACKUP]); +/* WRITE_PERI_REG(SPI_SLAVE(spi_no), backup_mem[SPI_SLAVE_BACKUP]); */ } -void ICACHE_FLASH_ATTR -hspi_master_dev_init(uint8_t dev_no, uint8_t clk_polar, uint8_t clk_div) -{ +void ICACHE_FLASH_ATTR hspi_master_dev_init(uint8_t dev_no, uint8_t clk_polar, uint8_t clk_div) { uint32_t regtemp; if ((dev_no > 3) || (clk_polar > 1) || (clk_div > 0x1f)) { @@ -148,7 +141,7 @@ hspi_master_dev_init(uint8_t dev_no, uint8_t clk_polar, uint8_t clk_div) hspi_dev_reg.hspi_reg_backup_flag = 1; - // spi_reg_recover(HSPI, hspi_dev_reg.hspi_flash_reg_backup); + /* spi_reg_recover(HSPI, hspi_dev_reg.hspi_flash_reg_backup); */ hspi_dev_reg.selected_dev_num = HSPI_IDLE; } @@ -188,9 +181,7 @@ hspi_master_dev_init(uint8_t dev_no, uint8_t clk_polar, uint8_t clk_div) } } -void ICACHE_FLASH_ATTR -hspi_dev_sel(uint8_t dev_no) -{ +void ICACHE_FLASH_ATTR hspi_dev_sel(uint8_t dev_no) { uint32_t regval; if (dev_no > 3) { @@ -423,17 +414,15 @@ hspi_dev_sel(uint8_t dev_no) * uint32_t * addr_dest--start address for preped destination memory space * uint32_t byte_length--length of the data which needs to be read from flash *******************************************************************************/ -SpiFlashOpResult ICACHE_FLASH_ATTR -hspi_overlap_read_flash_data(SpiFlashChip *spi, uint32_t flash_addr, uint32_t *addr_dest, uint32_t byte_length) -{ +SpiFlashOpResult ICACHE_FLASH_ATTR hspi_overlap_read_flash_data(SpiFlashChip *spi, uint32_t flash_addr, uint32_t *addr_dest, uint32_t byte_length) { uint32_t temp_addr, reg_tmp; - sint32 temp_length; + int32_t temp_length; uint8_t i; uint8_t remain_word_num; hspi_dev_sel(SPI_CS0_FLASH); - //address range check + /* address range check */ if ((flash_addr + byte_length) > (spi->chip_size)) { return SPI_FLASH_RESULT_ERR; } @@ -443,7 +432,7 @@ hspi_overlap_read_flash_data(SpiFlashChip *spi, uint32_t flash_addr, uint32_t *a while (temp_length > 0) { if (temp_length >= SPI_BUFF_BYTE_NUM) { - // reg_tmp=((temp_addr&0xff)<<16)|(temp_addr&0xff00)|((temp_addr&0xff0000)>>16)|(SPI_BUFF_BYTE_NUM << SPI_FLASH_BYTES_LEN); + /* reg_tmp=((temp_addr&0xff)<<16)|(temp_addr&0xff00)|((temp_addr&0xff0000)>>16)|(SPI_BUFF_BYTE_NUM << SPI_FLASH_BYTES_LEN); */ reg_tmp = temp_addr | (SPI_BUFF_BYTE_NUM << SPI_FLASH_BYTES_LEN) ; WRITE_PERI_REG(SPI_ADDR(HSPI), reg_tmp); WRITE_PERI_REG(SPI_CMD(HSPI), SPI_FLASH_READ); @@ -475,8 +464,7 @@ hspi_overlap_read_flash_data(SpiFlashChip *spi, uint32_t flash_addr, uint32_t *a return SPI_FLASH_RESULT_OK; } -void ICACHE_FLASH_ATTR -hspi_overlap_flash_init(void) +void ICACHE_FLASH_ATTR hspi_overlap_flash_init(void) { hspi_master_dev_init(SPI_CS0_FLASH, 0, 0); diff --git a/driver_lib/driver/uart.c b/driver_lib/driver/uart.c index 935457bd..a09b051a 100644 --- a/driver_lib/driver/uart.c +++ b/driver_lib/driver/uart.c @@ -23,19 +23,20 @@ */ #include "ets_sys.h" -#include "osapi.h" +#include "c_types.h" +#include "os_type.h" #include "osapi.h" #include "mem.h" -#include "os_type.h" #include "user_interface.h" -#include "driver/uart.h" #include "driver/uart_register.h" +#include "driver/uart.h" -// UartDev is defined and initialized in rom code. -extern UartDevice UartDev; +#define FUNC_UART0_CTS 4 +#define FUNC_U1TXD_BK 2 +#define UART_LINE_INV_MASK (0x3f<<19) -LOCAL struct UartBuffer *pTxBuffer = NULL; -LOCAL struct UartBuffer *pRxBuffer = NULL; +/* UartDev is defined and initialized in ROM */ +extern UARTDevice_t UartDev; /*uart demo with a system task, to output what uart receives*/ /*this is a example to process uart data from task,please change the priority to fit your application task if exists*/ @@ -44,12 +45,10 @@ LOCAL struct UartBuffer *pRxBuffer = NULL; #define uart_recvTaskQueueLen 10 os_event_t uart_recvTaskQueue[uart_recvTaskQueueLen]; -#define DBG -#define DBG1 uart1_sendStr_no_wait -#define DBG2 os_printf - +#define DBG0(x, ...) +#define DBG1(x, ...) uart_send_str_no_wait(UART1, (x), ## __VA_ARGS__) -LOCAL void uart0_rx_intr_handler(void *para); +static void uart0_rx_intr_handler(void *para); /****************************************************************************** * FunctionName : uart_config @@ -59,165 +58,260 @@ LOCAL void uart0_rx_intr_handler(void *para); * Parameters : uart_no, use UART0 or UART1 defined ahead * Returns : NONE *******************************************************************************/ -LOCAL void ICACHE_FLASH_ATTR -uart_config(uint8_t uart_no) -{ - if (uart_no == UART1) { +static void ICACHE_FLASH_ATTR uart_config(UARTNum uart) { + if (uart == UART1) { PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, FUNC_U1TXD_BK); } else { /* rcv_buff size if 0x100 */ - ETS_UART_INTR_ATTACH(uart0_rx_intr_handler, &(UartDev.rcv_buff)); + ETS_UART_INTR_ATTACH(uart0_rx_intr_handler, &(UartDev.rx_buff)); PIN_PULLUP_DIS(PERIPHS_IO_MUX_U0TXD_U); PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD); #if UART_HW_RTS - PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_U0RTS); //HW FLOW CONTROL RTS PIN + PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_U0RTS); /* HW FLOW CONTROL RTS PIN */ #endif #if UART_HW_CTS - PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, FUNC_U0CTS); //HW FLOW CONTROL CTS PIN + PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, FUNC_U0CTS); /* HW FLOW CONTROL CTS PIN */ #endif } - uart_div_modify(uart_no, UART_CLK_FREQ / (UartDev.baut_rate));//SET BAUDRATE + uart_div_modify(uart, UART_CLK_FREQ / (UartDev.baud_rate)); - WRITE_PERI_REG(UART_CONF0(uart_no), ((UartDev.exist_parity & UART_PARITY_EN_M) << UART_PARITY_EN_S) //SET BIT AND PARITY MODE - | ((UartDev.parity & UART_PARITY_M) << UART_PARITY_S) - | ((UartDev.stop_bits & UART_STOP_BIT_NUM) << UART_STOP_BIT_NUM_S) - | ((UartDev.data_bits & UART_BIT_NUM) << UART_BIT_NUM_S)); + WRITE_PERI_REG(UART_CONF0(uart), + ((UartDev.exist_parity & UART_PARITY_EN_M) << UART_PARITY_EN_S) + | ((UartDev.parity & UART_PARITY_M) << UART_PARITY_S) + | ((UartDev.stop_bits & UART_STOP_BIT_NUM) << UART_STOP_BIT_NUM_S) + | ((UartDev.data_bits & UART_BIT_NUM) << UART_BIT_NUM_S)); - //clear rx and tx fifo,not ready - SET_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST); //RESET FIFO - CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST); + /* clear rx and tx fifo,not ready */ + SET_PERI_REG_MASK(UART_CONF0(uart), UART_RXFIFO_RST | UART_TXFIFO_RST); + CLEAR_PERI_REG_MASK(UART_CONF0(uart), UART_RXFIFO_RST | UART_TXFIFO_RST); - if (uart_no == UART0) { - //set rx fifo trigger - WRITE_PERI_REG(UART_CONF1(uart_no), - ((100 & UART_RXFIFO_FULL_THRHD) << UART_RXFIFO_FULL_THRHD_S) | + if (uart == UART0) { + /* set rx fifo trigger */ + WRITE_PERI_REG(UART_CONF1(uart), + ((100 & UART_RXFIFO_FULL_THRHD) << UART_RXFIFO_FULL_THRHD_S) | #if UART_HW_RTS ((110 & UART_RX_FLOW_THRHD) << UART_RX_FLOW_THRHD_S) | - UART_RX_FLOW_EN | //enbale rx flow control + UART_RX_FLOW_EN | /* enable rx flow control */ #endif - (0x02 & UART_RX_TOUT_THRHD) << UART_RX_TOUT_THRHD_S | + (0x02 & UART_RX_TOUT_THRHD) << UART_RX_TOUT_THRHD_S | UART_RX_TOUT_EN | - ((0x10 & UART_TXFIFO_EMPTY_THRHD) << UART_TXFIFO_EMPTY_THRHD_S)); //wjl + ((0x10 & UART_TXFIFO_EMPTY_THRHD) << UART_TXFIFO_EMPTY_THRHD_S)); #if UART_HW_CTS - SET_PERI_REG_MASK(UART_CONF0(uart_no), UART_TX_FLOW_EN); //add this sentense to add a tx flow control via MTCK( CTS ) + SET_PERI_REG_MASK(UART_CONF0(uart_no), UART_TX_FLOW_EN); /* add this sentence to add a tx flow control via MTCK( CTS ) */ #endif - SET_PERI_REG_MASK(UART_INT_ENA(uart_no), UART_RXFIFO_TOUT_INT_ENA | UART_FRM_ERR_INT_ENA); + SET_PERI_REG_MASK(UART_INT_ENA(uart), UART_RXFIFO_TOUT_INT_ENA | UART_FRM_ERR_INT_ENA); } else { - WRITE_PERI_REG(UART_CONF1(uart_no), ((UartDev.rcv_buff.TrigLvl & UART_RXFIFO_FULL_THRHD) << UART_RXFIFO_FULL_THRHD_S)); //TrigLvl default val == 1 + WRITE_PERI_REG(UART_CONF1(uart), ((UartDev.rx_buff.trig_lvl & UART_RXFIFO_FULL_THRHD) << UART_RXFIFO_FULL_THRHD_S)); } - //clear all interrupt - WRITE_PERI_REG(UART_INT_CLR(uart_no), 0xffff); - //enable rx_interrupt - SET_PERI_REG_MASK(UART_INT_ENA(uart_no), UART_RXFIFO_FULL_INT_ENA | UART_RXFIFO_OVF_INT_ENA); + /* clear all interrupt */ + WRITE_PERI_REG(UART_INT_CLR(uart), 0xffff); + /* enable rx_interrupt */ + SET_PERI_REG_MASK(UART_INT_ENA(uart), UART_RXFIFO_FULL_INT_ENA | UART_RXFIFO_OVF_INT_ENA); } -/****************************************************************************** - * FunctionName : uart1_tx_one_char - * Description : Internal used function - * Use uart1 interface to transfer one char - * Parameters : uint8_t TxChar - character to tx - * Returns : OK -*******************************************************************************/ -STATUS uart_tx_one_char(uint8_t uart, uint8_t TxChar) -{ - while (true) { - uint32_t fifo_cnt = READ_PERI_REG(UART_STATUS(uart)) & (UART_TXFIFO_CNT << UART_TXFIFO_CNT_S); +#if UART_BUFF_EN - if ((fifo_cnt >> UART_TXFIFO_CNT_S & UART_TXFIFO_CNT) < 126) { - break; +static UARTBuffer_t *p_tx_buffer = NULL; +static UARTBuffer_t *p_rx_buffer = NULL; + +static UARTBuffer_t * ICACHE_FLASH_ATTR init_uart_buf(uint32_t buf_size) { + uint32_t heap_size = system_get_free_heap_size(); + + if (heap_size <= buf_size) { + DBG1("no buf for uart\n\r"); + return NULL; + } else { + DBG0("test heap size: %d\n\r", heap_size); + UARTBuffer_t *p = (UARTBuffer_t *)os_malloc(sizeof(UARTBuffer_t)); + p->buf_size = buf_size; + p->p_buf = (uint8_t *)os_malloc(p->buf_size); + p->p_in_pos = p->p_buf; + p->p_out_pos = p->p_buf; + p->space = p->buf_size; + p->buf_state = OK; + p->next = NULL; + p->tcp_control = RUN; + return p; + } +} + +static void copy_uart_buf(UARTBuffer_t *p, char *pdata, uint16_t len) { + if (len == 0) { + return ; + } + + uint16_t tail_len = p->p_buf + p->buf_size - p->p_in_pos; + + if (tail_len >= len) { + os_memcpy(p->p_in_pos, pdata, len); + p->p_in_pos += len; + p->p_in_pos = (p->p_buf + (p->p_in_pos - p->p_buf) % p->buf_size); + p->space -= len; + } else { + os_memcpy(p->p_in_pos, pdata, tail_len); + p->p_in_pos += (tail_len); + p->p_in_pos = (p->p_buf + (p->p_in_pos - p->p_buf) % p->buf_size); + p->space -= tail_len; + os_memcpy(p->p_in_pos, pdata + tail_len, len - tail_len); + p->p_in_pos += (len - tail_len); + p->p_in_pos = (p->p_buf + (p->p_in_pos - p->p_buf) % p->buf_size); + p->space -= (len - tail_len); + } + +} + +static void ICACHE_FLASH_ATTR free_uart_buf(UARTBuffer_t *p_buf) { + os_free(p_buf->p_buf); + os_free(p_buf); +} + +static uint16_t ICACHE_FLASH_ATTR rx_buf_deq(char *pdata, uint16_t len) { + uint16_t buf_len = (p_rx_buffer->buf_size - p_rx_buffer->space); + uint16_t tail_len = p_rx_buffer->p_buf + p_rx_buffer->buf_size - p_rx_buffer->p_out_pos ; + uint16_t len_tmp = 0; + len_tmp = ((len > buf_len) ? buf_len : len); + + if (p_rx_buffer->p_out_pos <= p_rx_buffer->p_in_pos) { + os_memcpy(pdata, p_rx_buffer->p_out_pos, len_tmp); + p_rx_buffer->p_out_pos += len_tmp; + p_rx_buffer->space += len_tmp; + } else { + if (len_tmp > tail_len) { + os_memcpy(pdata, p_rx_buffer->p_out_pos, tail_len); + p_rx_buffer->p_out_pos += tail_len; + p_rx_buffer->p_out_pos = (p_rx_buffer->p_buf + (p_rx_buffer->p_out_pos - p_rx_buffer->p_buf) % p_rx_buffer->buf_size); + p_rx_buffer->space += tail_len; + + os_memcpy(pdata + tail_len, p_rx_buffer->p_out_pos, len_tmp - tail_len); + p_rx_buffer->p_out_pos += (len_tmp - tail_len); + p_rx_buffer->p_out_pos = (p_rx_buffer->p_buf + (p_rx_buffer->p_out_pos - p_rx_buffer->p_buf) % p_rx_buffer->buf_size); + p_rx_buffer->space += (len_tmp - tail_len); + } else { + /* os_printf("case 3 in rx deq\n\r"); */ + os_memcpy(pdata, p_rx_buffer->p_out_pos, len_tmp); + p_rx_buffer->p_out_pos += len_tmp; + p_rx_buffer->p_out_pos = (p_rx_buffer->p_buf + (p_rx_buffer->p_out_pos - p_rx_buffer->p_buf) % p_rx_buffer->buf_size); + p_rx_buffer->space += len_tmp; } } - WRITE_PERI_REG(UART_FIFO(uart), TxChar); - return OK; + if (p_rx_buffer->space >= UART_FIFO_LEN) { + uart_rx_intr_enable(UART0); + } + + return len_tmp; } -/****************************************************************************** - * FunctionName : uart1_write_char - * Description : Internal used function - * Do some special deal while tx char is '\r' or '\n' - * Parameters : char c - character to tx - * Returns : NONE -*******************************************************************************/ -LOCAL void ICACHE_FLASH_ATTR -uart1_write_char(char c) -{ - if (c == '\n') { - uart_tx_one_char(UART1, '\r'); - uart_tx_one_char(UART1, '\n'); - } else if (c == '\r') { +static void rx_buf_enq(void) { + uint8_t fifo_len, buf_idx; + uint8_t fifo_data; +#if 1 + fifo_len = (READ_PERI_REG(UART_STATUS(UART0)) >> UART_RXFIFO_CNT_S)&UART_RXFIFO_CNT; + if (fifo_len >= p_rx_buffer->space) { + os_printf("buf full!!!\n\r"); } else { - uart_tx_one_char(UART1, c); + buf_idx = 0; + + while (buf_idx < fifo_len) { + buf_idx++; + fifo_data = READ_PERI_REG(UART_FIFO(UART0)) & 0xFF; + *(p_rx_buffer->p_in_pos++) = fifo_data; + + if (p_rx_buffer->p_in_pos == (p_rx_buffer->p_buf + p_rx_buffer->buf_size)) { + p_rx_buffer->p_in_pos = p_rx_buffer->p_buf; + } + } + + p_rx_buffer->space -= fifo_len ; + + if (p_rx_buffer->space >= UART_FIFO_LEN) { + /* os_printf("after rx enq buf enough\n\r"); */ + uart_rx_intr_enable(UART0); + } } + +#endif } -//os_printf output to fifo or to the tx buffer -LOCAL void ICACHE_FLASH_ATTR -uart0_write_char_no_wait(char c) +static void ICACHE_FLASH_ATTR tx_buf_enq(char *pdata, uint16_t len) { -#if UART_BUFF_EN //send to uart0 fifo but do not wait - uint8_t chr; + CLEAR_PERI_REG_MASK(UART_INT_ENA(UART0), UART_TXFIFO_EMPTY_INT_ENA); - if (c == '\n') { - chr = '\r'; - tx_buff_enq(&chr, 1); - chr = '\n'; - tx_buff_enq(&chr, 1); - } else if (c == '\r') { + if (p_tx_buffer == NULL) { + DBG1("\n\rnull, create buffer struct\n\r"); + p_tx_buffer = init_uart_buf(UART_TX_BUFFER_SIZE); + if (p_tx_buffer != NULL) { + copy_uart_buf(p_tx_buffer, pdata, len); + } else { + DBG1("uart tx MALLOC no buf \n\r"); + } } else { - tx_buff_enq(&c, 1); + if (len <= p_tx_buffer->space) { + copy_uart_buf(p_tx_buffer, pdata, len); + } else { + DBG1("UART TX BUF FULL!!!!\n\r"); + } } -#else //send to uart tx buffer - - if (c == '\n') { - uart_tx_one_char_no_wait(UART0, '\r'); - uart_tx_one_char_no_wait(UART0, '\n'); - } else if (c == '\r') { +#if 0 - } else { - uart_tx_one_char_no_wait(UART0, c); + if (p_tx_buffer->space <= URAT_TX_LOWER_SIZE) { + set_tcp_block(); } #endif + SET_PERI_REG_MASK(UART_CONF1(UART0), (UART_TX_EMPTY_THRESH_VAL & UART_TXFIFO_EMPTY_THRHD) << UART_TXFIFO_EMPTY_THRHD_S); + SET_PERI_REG_MASK(UART_INT_ENA(UART0), UART_TXFIFO_EMPTY_INT_ENA); } -/****************************************************************************** - * FunctionName : uart0_tx_buffer - * Description : use uart0 to transfer buffer - * Parameters : uint8_t *buf - point to send buffer - * uint16_t len - buffer len - * Returns : -*******************************************************************************/ -void ICACHE_FLASH_ATTR -uart0_tx_buffer(uint8_t *buf, uint16_t len) +static void tx_fifo_insert(UARTNum uart, UARTBuffer_t *p, uint8_t len) { - uint16_t i; + uint8_t i; for (i = 0; i < len; i++) { - uart_tx_one_char(UART0, buf[i]); + WRITE_PERI_REG(UART_FIFO(uart), *(p->p_out_pos++)); + + if (p->p_out_pos == (p->p_buf + p->buf_size)) { + p->p_out_pos = p->p_buf; + } } + + p->p_out_pos = (p->p_buf + (p->p_out_pos - p->p_buf) % p->buf_size); + p->space += len; } -/****************************************************************************** - * FunctionName : uart0_sendStr - * Description : use uart0 to transfer buffer - * Parameters : uint8_t *buf - point to send buffer - * uint16_t len - buffer len - * Returns : -*******************************************************************************/ -void ICACHE_FLASH_ATTR -uart0_sendStr(const char *str) -{ - while (*str) { - uart_tx_one_char(UART0, *str++); +static void tx_buf_start(UARTNum uart) { + uint8_t tx_fifo_len = (READ_PERI_REG(UART_STATUS(uart)) >> UART_TXFIFO_CNT_S)&UART_TXFIFO_CNT; + uint8_t fifo_remain = UART_FIFO_LEN - tx_fifo_len ; + uint8_t len_tmp; + uint16_t tail_ptx_len, head_ptx_len, data_len; + /* struct UartBuffer* pTxBuff = *get_buff_prt(); */ + + if (p_tx_buffer) { + data_len = (p_tx_buffer->buf_size - p_tx_buffer->space); + + if (data_len > fifo_remain) { + len_tmp = fifo_remain; + tx_fifo_insert(uart, p_tx_buffer, len_tmp); + SET_PERI_REG_MASK(UART_INT_ENA(UART0), UART_TXFIFO_EMPTY_INT_ENA); + } else { + len_tmp = data_len; + tx_fifo_insert(uart, p_tx_buffer, len_tmp); + } + } else { + DBG1("pTxBuff null \n\r"); } } -void at_port_print(const char *str) __attribute__((alias("uart0_sendStr"))); + +#endif + +static void ICACHE_FLASH_ATTR uart0_send_str(const char *str) { uart_send_str(UART0, str); } +void at_port_print(const char *str) __attribute__((alias("uart0_send_str"))); + /****************************************************************************** * FunctionName : uart0_rx_intr_handler * Description : Internal used function @@ -225,82 +319,59 @@ void at_port_print(const char *str) __attribute__((alias("uart0_sendStr"))); * Parameters : void *para - point to ETS_UART_INTR_ATTACH's arg * Returns : NONE *******************************************************************************/ -LOCAL void -uart0_rx_intr_handler(void *para) -{ - /* uart0 and uart1 intr combine togther, when interrupt occur, see reg 0x3ff20020, bit2, bit0 represents +/* ATTENTION: + * IN NON-OS VERSION SDK, DO NOT USE "ICACHE_FLASH_ATTR" FUNCTIONS IN THE WHOLE HANDLER PROCESS + * ALL THE FUNCTIONS CALLED IN INTERRUPT HANDLER MUST BE DECLARED IN RAM. IF NOT, POST AN EVENT + * AND PROCESS IN SYSTEM TASK + */ + +static void uart0_rx_intr_handler(void *para) { + /* uart0 and uart1 intr combine together, when interrupt occur, see reg 0x3ff20020, bit2, bit0 represents * uart1 and uart0 respectively */ - uint8_t RcvChar; - uint8_t uart_no = UART0;//UartDev.buff_uart_no; + uint8_t rx_char; + uint8_t uart = UART0; uint8_t fifo_len = 0; uint8_t buf_idx = 0; uint8_t temp, cnt; - //RcvMsgBuff *pRxBuff = (RcvMsgBuff *)para; + /* RcvMsgBuff *pRxBuff = (RcvMsgBuff *)para; */ - /*ATTENTION:*/ - /*IN NON-OS VERSION SDK, DO NOT USE "ICACHE_FLASH_ATTR" FUNCTIONS IN THE WHOLE HANDLER PROCESS*/ - /*ALL THE FUNCTIONS CALLED IN INTERRUPT HANDLER MUST BE DECLARED IN RAM */ - /*IF NOT , POST AN EVENT AND PROCESS IN SYSTEM TASK */ - if (UART_FRM_ERR_INT_ST == (READ_PERI_REG(UART_INT_ST(uart_no)) & UART_FRM_ERR_INT_ST)) { + if (UART_FRM_ERR_INT_ST == (READ_PERI_REG(UART_INT_ST(uart)) & UART_FRM_ERR_INT_ST)) { DBG1("FRM_ERR\r\n"); - WRITE_PERI_REG(UART_INT_CLR(uart_no), UART_FRM_ERR_INT_CLR); - } else if (UART_RXFIFO_FULL_INT_ST == (READ_PERI_REG(UART_INT_ST(uart_no)) & UART_RXFIFO_FULL_INT_ST)) { - DBG("f"); + WRITE_PERI_REG(UART_INT_CLR(uart), UART_FRM_ERR_INT_CLR); + } else if (UART_RXFIFO_FULL_INT_ST == (READ_PERI_REG(UART_INT_ST(uart)) & UART_RXFIFO_FULL_INT_ST)) { + DBG0("f"); uart_rx_intr_disable(UART0); WRITE_PERI_REG(UART_INT_CLR(UART0), UART_RXFIFO_FULL_INT_CLR); system_os_post(uart_recvTaskPrio, 0, 0); - } else if (UART_RXFIFO_TOUT_INT_ST == (READ_PERI_REG(UART_INT_ST(uart_no)) & UART_RXFIFO_TOUT_INT_ST)) { - DBG("t"); + } else if (UART_RXFIFO_TOUT_INT_ST == (READ_PERI_REG(UART_INT_ST(uart)) & UART_RXFIFO_TOUT_INT_ST)) { + DBG0("t"); uart_rx_intr_disable(UART0); WRITE_PERI_REG(UART_INT_CLR(UART0), UART_RXFIFO_TOUT_INT_CLR); system_os_post(uart_recvTaskPrio, 0, 0); - } else if (UART_TXFIFO_EMPTY_INT_ST == (READ_PERI_REG(UART_INT_ST(uart_no)) & UART_TXFIFO_EMPTY_INT_ST)) { - DBG("e"); + } else if (UART_TXFIFO_EMPTY_INT_ST == (READ_PERI_REG(UART_INT_ST(uart)) & UART_TXFIFO_EMPTY_INT_ST)) { + DBG0("e"); /* to output uart data from uart buffer directly in empty interrupt handler*/ /*instead of processing in system event, in order not to wait for current task/function to quit */ - /*ATTENTION:*/ - /*IN NON-OS VERSION SDK, DO NOT USE "ICACHE_FLASH_ATTR" FUNCTIONS IN THE WHOLE HANDLER PROCESS*/ - /*ALL THE FUNCTIONS CALLED IN INTERRUPT HANDLER MUST BE DECLARED IN RAM */ + CLEAR_PERI_REG_MASK(UART_INT_ENA(UART0), UART_TXFIFO_EMPTY_INT_ENA); #if UART_BUFF_EN - tx_start_uart_buffer(UART0); + tx_buf_start(UART0); #endif - //system_os_post(uart_recvTaskPrio, 1, 0); - WRITE_PERI_REG(UART_INT_CLR(uart_no), UART_TXFIFO_EMPTY_INT_CLR); + /* system_os_post(uart_recvTaskPrio, 1, 0); */ + WRITE_PERI_REG(UART_INT_CLR(uart), UART_TXFIFO_EMPTY_INT_CLR); - } else if (UART_RXFIFO_OVF_INT_ST == (READ_PERI_REG(UART_INT_ST(uart_no)) & UART_RXFIFO_OVF_INT_ST)) { - WRITE_PERI_REG(UART_INT_CLR(uart_no), UART_RXFIFO_OVF_INT_CLR); + } else if (UART_RXFIFO_OVF_INT_ST == (READ_PERI_REG(UART_INT_ST(uart)) & UART_RXFIFO_OVF_INT_ST)) { + WRITE_PERI_REG(UART_INT_CLR(uart), UART_RXFIFO_OVF_INT_CLR); DBG1("RX OVF!!\r\n"); } } -/****************************************************************************** - * FunctionName : uart_init - * Description : user interface for init uart - * Parameters : UartBautRate uart0_br - uart0 bautrate - * UartBautRate uart1_br - uart1 bautrate - * Returns : NONE -*******************************************************************************/ -#if UART_SELFTEST&UART_BUFF_EN -os_timer_t buff_timer_t; -void ICACHE_FLASH_ATTR -uart_test_rx() -{ - uint8_t uart_buf[128] = {0}; - uint16_t len = 0; - len = rx_buff_deq(uart_buf, 128); - tx_buff_enq(uart_buf, len); -} -#endif - -LOCAL void ICACHE_FLASH_ATTR /////// -uart_recvTask(os_event_t *events) -{ +static void ICACHE_FLASH_ATTR uart_recv_task(os_event_t *events) { if (events->sig == 0) { #if UART_BUFF_EN - Uart_rx_buff_enq(); + rx_buf_enq(); #else uint8_t fifo_len = (READ_PERI_REG(UART_STATUS(UART0)) >> UART_RXFIFO_CNT_S)&UART_RXFIFO_CNT; uint8_t d_tmp = 0; @@ -316,524 +387,306 @@ uart_recvTask(os_event_t *events) #endif } else if (events->sig == 1) { #if UART_BUFF_EN - //already move uart buffer output to uart empty interrupt - //tx_start_uart_buffer(UART0); + /* already move uart buffer output to uart empty interrupt */ + tx_buf_start(UART0); #else #endif } } -void ICACHE_FLASH_ATTR -uart_init(UartBautRate uart0_br, UartBautRate uart1_br) -{ - /*this is a example to process uart data from task,please change the priority to fit your application task if exists*/ - system_os_task(uart_recvTask, uart_recvTaskPrio, uart_recvTaskQueue, uart_recvTaskQueueLen); //demo with a task to process the uart data +void ICACHE_FLASH_ATTR uart_init(UARTBaudRate uart0_br, UARTBaudRate uart1_br) { + /* this is an example to process uart data from a system task + * please change the priority to fit your application task if exists */ + system_os_task(uart_recv_task, uart_recvTaskPrio, uart_recvTaskQueue, uart_recvTaskQueueLen); - UartDev.baut_rate = uart0_br; + UartDev.baud_rate = uart0_br; uart_config(UART0); - UartDev.baut_rate = uart1_br; + UartDev.baud_rate = uart1_br; uart_config(UART1); ETS_UART_INTR_ENABLE(); #if UART_BUFF_EN - pTxBuffer = Uart_Buf_Init(UART_TX_BUFFER_SIZE); - pRxBuffer = Uart_Buf_Init(UART_RX_BUFFER_SIZE); + p_tx_buffer = init_uart_buf(UART_TX_BUFFER_SIZE); + p_rx_buffer = init_uart_buf(UART_RX_BUFFER_SIZE); #endif /*option 1: use default print, output from uart0 , will wait some time if fifo is full */ - //do nothing... + /* do nothing... */ /*option 2: output from uart1,uart1 output will not wait , just for output debug info */ /*os_printf output uart data via uart1(GPIO2)*/ - //os_install_putc1((void *)uart1_write_char); //use this one to output debug information via uart1 // + /* os_install_putc1((void *)uart1_write_char); */ /* use this one to output debug information via uart1 */ /*option 3: output from uart0 will skip current byte if fifo is full now... */ /*see uart0_write_char_no_wait:you can output via a buffer or output directly */ /*os_printf output uart data via uart0 or uart buffer*/ - //os_install_putc1((void *)uart0_write_char_no_wait); //use this to print via uart0 + /* os_install_putc1((void *)uart0_write_char_no_wait); */ /* use this to print via uart0 */ #if UART_SELFTEST&UART_BUFF_EN os_timer_disarm(&buff_timer_t); - os_timer_setfn(&buff_timer_t, uart_test_rx, NULL); //a demo to process the data in uart rx buffer + os_timer_setfn(&buff_timer_t, uart_test_rx, NULL); /* a demo to process the data in uart rx buffer */ os_timer_arm(&buff_timer_t, 10, 1); #endif } -void ICACHE_FLASH_ATTR -uart_reattach() -{ +void ICACHE_FLASH_ATTR uart_reattach(void) { uart_init(BIT_RATE_115200, BIT_RATE_115200); } /****************************************************************************** - * FunctionName : uart_tx_one_char_no_wait - * Description : uart tx a single char without waiting for fifo - * Parameters : uint8_t uart - uart port - * uint8_t TxChar - char to tx - * Returns : STATUS + * FunctionName : uart_tx_one_char + * Description : Internal used function + * Use uart1 interface to transfer one char + * Parameters : uint8_t TxChar - character to tx + * Returns : OK *******************************************************************************/ -STATUS uart_tx_one_char_no_wait(uint8_t uart, uint8_t TxChar) -{ - uint8_t fifo_cnt = ((READ_PERI_REG(UART_STATUS(uart)) >> UART_TXFIFO_CNT_S)& UART_TXFIFO_CNT); +STATUS uart_tx_one_char(UARTNum uart, uint8_t tx_har) { + while (true) { + uint32_t fifo_cnt = READ_PERI_REG(UART_STATUS(uart)) & (UART_TXFIFO_CNT << UART_TXFIFO_CNT_S); - if (fifo_cnt < 126) { - WRITE_PERI_REG(UART_FIFO(uart), TxChar); + if ((fifo_cnt >> UART_TXFIFO_CNT_S & UART_TXFIFO_CNT) < 126) { + break; + } } + WRITE_PERI_REG(UART_FIFO(uart), tx_har); return OK; } -STATUS uart0_tx_one_char_no_wait(uint8_t TxChar) -{ - uint8_t fifo_cnt = ((READ_PERI_REG(UART_STATUS(UART0)) >> UART_TXFIFO_CNT_S)& UART_TXFIFO_CNT); +/****************************************************************************** + * FunctionName : uart_tx_one_char_no_wait + * Description : uart tx a single char without waiting for fifo + * Parameters : uint8_t uart - uart port + * uint8_t TxChar - char to tx + * Returns : STATUS +*******************************************************************************/ +STATUS uart_tx_one_char_no_wait(UARTNum uart, uint8_t tx_char) { + uint8_t fifo_cnt = ((READ_PERI_REG(UART_STATUS(uart)) >> UART_TXFIFO_CNT_S)& UART_TXFIFO_CNT); if (fifo_cnt < 126) { - WRITE_PERI_REG(UART_FIFO(UART0), TxChar); + WRITE_PERI_REG(UART_FIFO(uart), tx_char); } return OK; } - /****************************************************************************** - * FunctionName : uart1_sendStr_no_wait + * FunctionName : uart_send_str_no_wait * Description : uart tx a string without waiting for every char, used for print debug info which can be lost * Parameters : const char *str - string to be sent * Returns : NONE *******************************************************************************/ -void uart1_sendStr_no_wait(const char *str) +void uart_send_str_no_wait(UARTNum uart, const char *str) { while (*str) { - uart_tx_one_char_no_wait(UART1, *str++); - } -} - - -#if UART_BUFF_EN -/****************************************************************************** - * FunctionName : Uart_Buf_Init - * Description : tx buffer enqueue: fill a first linked buffer - * Parameters : char *pdata - data point to be enqueue - * Returns : NONE -*******************************************************************************/ -struct UartBuffer *ICACHE_FLASH_ATTR -Uart_Buf_Init(uint32_t buf_size) -{ - uint32_t heap_size = system_get_free_heap_size(); - - if (heap_size <= buf_size) { - DBG1("no buf for uart\n\r"); - return NULL; - } else { - DBG("test heap size: %d\n\r", heap_size); - struct UartBuffer *pBuff = (struct UartBuffer *)os_malloc(sizeof(struct UartBuffer)); - pBuff->UartBuffSize = buf_size; - pBuff->pUartBuff = (uint8_t *)os_malloc(pBuff->UartBuffSize); - pBuff->pInPos = pBuff->pUartBuff; - pBuff->pOutPos = pBuff->pUartBuff; - pBuff->Space = pBuff->UartBuffSize; - pBuff->BuffState = OK; - pBuff->nextBuff = NULL; - pBuff->TcpControl = RUN; - return pBuff; - } -} - - -//copy uart buffer -LOCAL void Uart_Buf_Cpy(struct UartBuffer *pCur, char *pdata, uint16_t data_len) -{ - if (data_len == 0) { - return ; - } - - uint16_t tail_len = pCur->pUartBuff + pCur->UartBuffSize - pCur->pInPos ; - - if (tail_len >= data_len) { //do not need to loop back the queue - os_memcpy(pCur->pInPos, pdata, data_len); - pCur->pInPos += (data_len); - pCur->pInPos = (pCur->pUartBuff + (pCur->pInPos - pCur->pUartBuff) % pCur->UartBuffSize); - pCur->Space -= data_len; - } else { - os_memcpy(pCur->pInPos, pdata, tail_len); - pCur->pInPos += (tail_len); - pCur->pInPos = (pCur->pUartBuff + (pCur->pInPos - pCur->pUartBuff) % pCur->UartBuffSize); - pCur->Space -= tail_len; - os_memcpy(pCur->pInPos, pdata + tail_len, data_len - tail_len); - pCur->pInPos += (data_len - tail_len); - pCur->pInPos = (pCur->pUartBuff + (pCur->pInPos - pCur->pUartBuff) % pCur->UartBuffSize); - pCur->Space -= (data_len - tail_len); - } - -} - -/****************************************************************************** - * FunctionName : uart_buf_free - * Description : deinit of the tx buffer - * Parameters : struct UartBuffer* pTxBuff - tx buffer struct pointer - * Returns : NONE -*******************************************************************************/ -void ICACHE_FLASH_ATTR -uart_buf_free(struct UartBuffer *pBuff) -{ - os_free(pBuff->pUartBuff); - os_free(pBuff); -} - - -//rx buffer dequeue -uint16_t ICACHE_FLASH_ATTR -rx_buff_deq(char *pdata, uint16_t data_len) -{ - uint16_t buf_len = (pRxBuffer->UartBuffSize - pRxBuffer->Space); - uint16_t tail_len = pRxBuffer->pUartBuff + pRxBuffer->UartBuffSize - pRxBuffer->pOutPos ; - uint16_t len_tmp = 0; - len_tmp = ((data_len > buf_len) ? buf_len : data_len); - - if (pRxBuffer->pOutPos <= pRxBuffer->pInPos) { - os_memcpy(pdata, pRxBuffer->pOutPos, len_tmp); - pRxBuffer->pOutPos += len_tmp; - pRxBuffer->Space += len_tmp; - } else { - if (len_tmp > tail_len) { - os_memcpy(pdata, pRxBuffer->pOutPos, tail_len); - pRxBuffer->pOutPos += tail_len; - pRxBuffer->pOutPos = (pRxBuffer->pUartBuff + (pRxBuffer->pOutPos - pRxBuffer->pUartBuff) % pRxBuffer->UartBuffSize); - pRxBuffer->Space += tail_len; - - os_memcpy(pdata + tail_len, pRxBuffer->pOutPos, len_tmp - tail_len); - pRxBuffer->pOutPos += (len_tmp - tail_len); - pRxBuffer->pOutPos = (pRxBuffer->pUartBuff + (pRxBuffer->pOutPos - pRxBuffer->pUartBuff) % pRxBuffer->UartBuffSize); - pRxBuffer->Space += (len_tmp - tail_len); - } else { - //os_printf("case 3 in rx deq\n\r"); - os_memcpy(pdata, pRxBuffer->pOutPos, len_tmp); - pRxBuffer->pOutPos += len_tmp; - pRxBuffer->pOutPos = (pRxBuffer->pUartBuff + (pRxBuffer->pOutPos - pRxBuffer->pUartBuff) % pRxBuffer->UartBuffSize); - pRxBuffer->Space += len_tmp; - } - } - - if (pRxBuffer->Space >= UART_FIFO_LEN) { - uart_rx_intr_enable(UART0); + uart_tx_one_char_no_wait(uart, *str++); } - - return len_tmp; } +void ICACHE_FLASH_ATTR uart_tx_send_buffer(UARTNum uart, uint8_t *buf, uint16_t len) { + uint16_t i; -//move data from uart fifo to rx buffer -void Uart_rx_buff_enq() -{ - uint8_t fifo_len, buf_idx; - uint8_t fifo_data; -#if 1 - fifo_len = (READ_PERI_REG(UART_STATUS(UART0)) >> UART_RXFIFO_CNT_S)&UART_RXFIFO_CNT; - - if (fifo_len >= pRxBuffer->Space) { - os_printf("buf full!!!\n\r"); - } else { - buf_idx = 0; - - while (buf_idx < fifo_len) { - buf_idx++; - fifo_data = READ_PERI_REG(UART_FIFO(UART0)) & 0xFF; - *(pRxBuffer->pInPos++) = fifo_data; - - if (pRxBuffer->pInPos == (pRxBuffer->pUartBuff + pRxBuffer->UartBuffSize)) { - pRxBuffer->pInPos = pRxBuffer->pUartBuff; - } - } - - pRxBuffer->Space -= fifo_len ; - - if (pRxBuffer->Space >= UART_FIFO_LEN) { - //os_printf("after rx enq buf enough\n\r"); - uart_rx_intr_enable(UART0); - } - } - -#endif -} - - -//fill the uart tx buffer -void ICACHE_FLASH_ATTR -tx_buff_enq(char *pdata, uint16_t data_len) -{ - CLEAR_PERI_REG_MASK(UART_INT_ENA(UART0), UART_TXFIFO_EMPTY_INT_ENA); - - if (pTxBuffer == NULL) { - DBG1("\n\rnull, create buffer struct\n\r"); - pTxBuffer = Uart_Buf_Init(UART_TX_BUFFER_SIZE); - - if (pTxBuffer != NULL) { - Uart_Buf_Cpy(pTxBuffer, pdata, data_len); - } else { - DBG1("uart tx MALLOC no buf \n\r"); - } - } else { - if (data_len <= pTxBuffer->Space) { - Uart_Buf_Cpy(pTxBuffer, pdata, data_len); - } else { - DBG1("UART TX BUF FULL!!!!\n\r"); - } - } - -#if 0 - - if (pTxBuffer->Space <= URAT_TX_LOWER_SIZE) { - set_tcp_block(); - } - -#endif - SET_PERI_REG_MASK(UART_CONF1(UART0), (UART_TX_EMPTY_THRESH_VAL & UART_TXFIFO_EMPTY_THRHD) << UART_TXFIFO_EMPTY_THRHD_S); - SET_PERI_REG_MASK(UART_INT_ENA(UART0), UART_TXFIFO_EMPTY_INT_ENA); -} - - - -//-------------------------------- -LOCAL void tx_fifo_insert(struct UartBuffer *pTxBuff, uint8_t data_len, uint8_t uart_no) -{ - uint8_t i; - - for (i = 0; i < data_len; i++) { - WRITE_PERI_REG(UART_FIFO(uart_no), *(pTxBuff->pOutPos++)); - - if (pTxBuff->pOutPos == (pTxBuff->pUartBuff + pTxBuff->UartBuffSize)) { - pTxBuff->pOutPos = pTxBuff->pUartBuff; - } - } - - pTxBuff->pOutPos = (pTxBuff->pUartBuff + (pTxBuff->pOutPos - pTxBuff->pUartBuff) % pTxBuff->UartBuffSize); - pTxBuff->Space += data_len; -} - - -/****************************************************************************** - * FunctionName : tx_start_uart_buffer - * Description : get data from the tx buffer and fill the uart tx fifo, co-work with the uart fifo empty interrupt - * Parameters : uint8_t uart_no - uart port num - * Returns : NONE -*******************************************************************************/ -void tx_start_uart_buffer(uint8_t uart_no) -{ - uint8_t tx_fifo_len = (READ_PERI_REG(UART_STATUS(uart_no)) >> UART_TXFIFO_CNT_S)&UART_TXFIFO_CNT; - uint8_t fifo_remain = UART_FIFO_LEN - tx_fifo_len ; - uint8_t len_tmp; - uint16_t tail_ptx_len, head_ptx_len, data_len; - //struct UartBuffer* pTxBuff = *get_buff_prt(); - - if (pTxBuffer) { - data_len = (pTxBuffer->UartBuffSize - pTxBuffer->Space); - - if (data_len > fifo_remain) { - len_tmp = fifo_remain; - tx_fifo_insert(pTxBuffer, len_tmp, uart_no); - SET_PERI_REG_MASK(UART_INT_ENA(UART0), UART_TXFIFO_EMPTY_INT_ENA); - } else { - len_tmp = data_len; - tx_fifo_insert(pTxBuffer, len_tmp, uart_no); - } - } else { - DBG1("pTxBuff null \n\r"); + for (i = 0; i < len; i++) { + uart_tx_one_char(uart, buf[i]); } } -#endif - - -void uart_rx_intr_disable(uint8_t uart_no) +void uart_rx_intr_disable(UARTNum uart) { #if 1 - CLEAR_PERI_REG_MASK(UART_INT_ENA(uart_no), UART_RXFIFO_FULL_INT_ENA | UART_RXFIFO_TOUT_INT_ENA); + CLEAR_PERI_REG_MASK(UART_INT_ENA(uart), UART_RXFIFO_FULL_INT_ENA | UART_RXFIFO_TOUT_INT_ENA); #else ETS_UART_INTR_DISABLE(); #endif } -void uart_rx_intr_enable(uint8_t uart_no) -{ +void uart_rx_intr_enable(UARTNum uart) { #if 1 - SET_PERI_REG_MASK(UART_INT_ENA(uart_no), UART_RXFIFO_FULL_INT_ENA | UART_RXFIFO_TOUT_INT_ENA); + SET_PERI_REG_MASK(UART_INT_ENA(uart), UART_RXFIFO_FULL_INT_ENA | UART_RXFIFO_TOUT_INT_ENA); #else ETS_UART_INTR_ENABLE(); #endif } - -//======================================================== -LOCAL void -uart0_write_char(char c) -{ - if (c == '\n') { - uart_tx_one_char(UART0, '\r'); - uart_tx_one_char(UART0, '\n'); - } else if (c == '\r') { - } else { - uart_tx_one_char(UART0, c); - } +void ICACHE_FLASH_ATTR uart_set_num_bits(UARTNum uart, UARTNumBits len) { + SET_PERI_REG_BITS(UART_CONF0(uart), UART_BIT_NUM, len, UART_BIT_NUM_S); } -void ICACHE_FLASH_ATTR -UART_SetWordLength(uint8_t uart_no, UartBitsNum4Char len) -{ - SET_PERI_REG_BITS(UART_CONF0(uart_no), UART_BIT_NUM, len, UART_BIT_NUM_S); +void ICACHE_FLASH_ATTR uart_set_stop_bits(UARTNum uart, UARTStopBits bits) { + SET_PERI_REG_BITS(UART_CONF0(uart), UART_STOP_BIT_NUM, bits, UART_STOP_BIT_NUM_S); } -void ICACHE_FLASH_ATTR -UART_SetStopBits(uint8_t uart_no, UartStopBitsNum bit_num) -{ - SET_PERI_REG_BITS(UART_CONF0(uart_no), UART_STOP_BIT_NUM, bit_num, UART_STOP_BIT_NUM_S); +void ICACHE_FLASH_ATTR uart_set_line_inverse(UARTNum uart, UARTLineLevelInverse inverse_mask) { + CLEAR_PERI_REG_MASK(UART_CONF0(uart), UART_LINE_INV_MASK); + SET_PERI_REG_MASK(UART_CONF0(uart), inverse_mask); } -void ICACHE_FLASH_ATTR -UART_SetLineInverse(uint8_t uart_no, UART_LineLevelInverse inverse_mask) -{ - CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_LINE_INV_MASK); - SET_PERI_REG_MASK(UART_CONF0(uart_no), inverse_mask); -} - -void ICACHE_FLASH_ATTR -UART_SetParity(uint8_t uart_no, UartParityMode Parity_mode) -{ - CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_PARITY | UART_PARITY_EN); +void ICACHE_FLASH_ATTR uart_set_parity(UARTNum uart, UARTParity parity) { + CLEAR_PERI_REG_MASK(UART_CONF0(uart), UART_PARITY | UART_PARITY_EN); - if (Parity_mode == NONE_BITS) { + if (parity == NONE_BITS) { } else { - SET_PERI_REG_MASK(UART_CONF0(uart_no), Parity_mode | UART_PARITY_EN); + SET_PERI_REG_MASK(UART_CONF0(uart), parity | UART_PARITY_EN); } } -void ICACHE_FLASH_ATTR -UART_SetBaudrate(uint8_t uart_no, uint32_t baud_rate) -{ - uart_div_modify(uart_no, UART_CLK_FREQ / baud_rate); +void ICACHE_FLASH_ATTR uart_set_rate(UARTNum uart, uint32_t rate) { + uart_div_modify(uart, UART_CLK_FREQ / rate); } -void ICACHE_FLASH_ATTR -UART_SetFlowCtrl(uint8_t uart_no, UART_HwFlowCtrl flow_ctrl, uint8_t rx_thresh) +void ICACHE_FLASH_ATTR uart_set_flow_ctrl(UARTNum uart, UARTHwFlowCtrl flow_ctrl, uint8_t rx_thresh) { - if (flow_ctrl & USART_HardwareFlowControl_RTS) { + if (flow_ctrl & UART_HW_FLOWCONTROL_RTS) { PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_U0RTS); - SET_PERI_REG_BITS(UART_CONF1(uart_no), UART_RX_FLOW_THRHD, rx_thresh, UART_RX_FLOW_THRHD_S); - SET_PERI_REG_MASK(UART_CONF1(uart_no), UART_RX_FLOW_EN); + SET_PERI_REG_BITS(UART_CONF1(uart), UART_RX_FLOW_THRHD, rx_thresh, UART_RX_FLOW_THRHD_S); + SET_PERI_REG_MASK(UART_CONF1(uart), UART_RX_FLOW_EN); } else { - CLEAR_PERI_REG_MASK(UART_CONF1(uart_no), UART_RX_FLOW_EN); + CLEAR_PERI_REG_MASK(UART_CONF1(uart), UART_RX_FLOW_EN); } - if (flow_ctrl & USART_HardwareFlowControl_CTS) { + if (flow_ctrl & UART_HW_FLOWCONTROL_CTS) { PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, FUNC_UART0_CTS); - SET_PERI_REG_MASK(UART_CONF0(uart_no), UART_TX_FLOW_EN); + SET_PERI_REG_MASK(UART_CONF0(uart), UART_TX_FLOW_EN); } else { - CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_TX_FLOW_EN); + CLEAR_PERI_REG_MASK(UART_CONF0(uart), UART_TX_FLOW_EN); } } -void ICACHE_FLASH_ATTR -UART_WaitTxFifoEmpty(uint8_t uart_no, uint32_t time_out_us) //do not use if tx flow control enabled -{ +/* do not use if tx flow control enabled */ +void ICACHE_FLASH_ATTR uart_wait_tx_fifo_empty(UARTNum uart, uint32_t time_out_us) { uint32_t t_s = system_get_time(); - while (READ_PERI_REG(UART_STATUS(uart_no)) & (UART_TXFIFO_CNT << UART_TXFIFO_CNT_S)) { + while (READ_PERI_REG(UART_STATUS(uart)) & (UART_TXFIFO_CNT << UART_TXFIFO_CNT_S)) { if ((system_get_time() - t_s) > time_out_us) { break; } - - WRITE_PERI_REG(0X60000914, 0X73);//WTD - + WRITE_PERI_REG(0X60000914, 0X73); /* WTD */ } } - -bool ICACHE_FLASH_ATTR -UART_CheckOutputFinished(uint8_t uart_no, uint32_t time_out_us) -{ +bool ICACHE_FLASH_ATTR uart_check_output_finished(UARTNum uart, uint32_t time_out_us) { uint32_t t_start = system_get_time(); uint8_t tx_fifo_len; - uint32_t tx_buff_len; + uint32_t tx_buff_len = 0; while (1) { - tx_fifo_len = ((READ_PERI_REG(UART_STATUS(uart_no)) >> UART_TXFIFO_CNT_S)&UART_TXFIFO_CNT); + tx_fifo_len = ((READ_PERI_REG(UART_STATUS(uart)) >> UART_TXFIFO_CNT_S)&UART_TXFIFO_CNT); - if (pTxBuffer) { - tx_buff_len = ((pTxBuffer->UartBuffSize) - (pTxBuffer->Space)); - } else { - tx_buff_len = 0; +#if UART_BUFF_EN + if (p_tx_buffer) { + tx_buff_len = ((p_tx_buffer->buf_size) - (p_tx_buffer->space)); } - +#endif if (tx_fifo_len == 0 && tx_buff_len == 0) { - return TRUE; + return true; } if (system_get_time() - t_start > time_out_us) { - return FALSE; + return false; } - - WRITE_PERI_REG(0X60000914, 0X73);//WTD + WRITE_PERI_REG(0X60000914, 0X73); /* WTD */ } } +void ICACHE_FLASH_ATTR uart_reset_fifo(UARTNum uart) { + SET_PERI_REG_MASK(UART_CONF0(uart), UART_RXFIFO_RST | UART_TXFIFO_RST); + CLEAR_PERI_REG_MASK(UART_CONF0(uart), UART_RXFIFO_RST | UART_TXFIFO_RST); +} -void ICACHE_FLASH_ATTR -UART_ResetFifo(uint8_t uart_no) -{ - SET_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST); - CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_RXFIFO_RST | UART_TXFIFO_RST); +void ICACHE_FLASH_ATTR uart_clear_intr_status(UARTNum uart, uint32_t clr_mask) { + WRITE_PERI_REG(UART_INT_CLR(uart), clr_mask); } -void ICACHE_FLASH_ATTR -UART_ClearIntrStatus(uint8_t uart_no, uint32_t clr_mask) -{ - WRITE_PERI_REG(UART_INT_CLR(uart_no), clr_mask); +void ICACHE_FLASH_ATTR uart_set_intr_enable(UARTNum uart, uint32_t ena_mask) { + SET_PERI_REG_MASK(UART_INT_ENA(uart), ena_mask); } -void ICACHE_FLASH_ATTR -UART_SetIntrEna(uint8_t uart_no, uint32_t ena_mask) +static void ICACHE_FLASH_ATTR uart0_write_char_no_wait(char c) { - SET_PERI_REG_MASK(UART_INT_ENA(uart_no), ena_mask); +#if UART_BUFF_EN + uint8_t chr; + + if (c == '\n') { + chr = '\r'; + tx_buf_enq(&chr, 1); + chr = '\n'; + tx_buf_enq(&chr, 1); + } else if (c == '\r') { + + } else { + tx_buf_enq(&c, 1); + } + +#else + if (c == '\n') { + uart_tx_one_char_no_wait(UART0, '\r'); + uart_tx_one_char_no_wait(UART0, '\n'); + } else if (c == '\r') { + + } else { + uart_tx_one_char_no_wait(UART0, c); + } +#endif +} + +static void uart_write_char(UARTNum uart, char c) { + if (c == '\n') { + uart_tx_one_char(UART0, '\r'); + uart_tx_one_char(UART0, '\n'); + } else if (c == '\r') { + } else { + uart_tx_one_char(UART0, c); + } } +static void ICACHE_FLASH_ATTR uart0_write_char(char c) { uart_write_char(UART1, c); } +static void ICACHE_FLASH_ATTR uart1_write_char(char c) { uart_write_char(UART0, c); } -void ICACHE_FLASH_ATTR -UART_SetPrintPort(uint8_t uart_no) +void ICACHE_FLASH_ATTR uart_set_print_port(UARTNum uart) { - if (uart_no == 1) { + if (uart == UART1) { os_install_putc1(uart1_write_char); } else { - /*option 1: do not wait if uart fifo is full,drop current character*/ + /* option 1: do not wait if uart fifo is full, drop current character */ os_install_putc1(uart0_write_char_no_wait); - /*option 2: wait for a while if uart fifo is full*/ + /* option 2: wait for a while if uart fifo is full */ os_install_putc1(uart0_write_char); } } +#if UART_SELFTEST -//======================================================== - +#if UART_BUFF_EN +os_timer_t buff_timer_t; -/*test code*/ -void ICACHE_FLASH_ATTR -uart_init_2(UartBautRate uart0_br, UartBautRate uart1_br) +void ICACHE_FLASH_ATTR uart_test_rx() { - // rom use 74880 baut_rate, here reinitialize - UartDev.baut_rate = uart0_br; + uint8_t uart_buf[128] = {0}; + uint16_t len = 0; + len = rx_buff_deq(uart_buf, 128); + tx_buff_enq(uart_buf, len); +} +#endif + +void ICACHE_FLASH_ATTR uart_init_2(UARTBaudRate uart0_br, UARTBaudRate uart1_br) { + /* rom use 74880 baut_rate, here reinitialize */ + UartDev.baud_rate = uart0_br; UartDev.exist_parity = STICK_PARITY_EN; UartDev.parity = EVEN_BITS; UartDev.stop_bits = ONE_STOP_BIT; UartDev.data_bits = EIGHT_BITS; uart_config(UART0); - UartDev.baut_rate = uart1_br; + UartDev.baud_rate = uart1_br; uart_config(UART1); ETS_UART_INTR_ENABLE(); - // install uart1 putc callback - os_install_putc1((void *)uart1_write_char);//print output at UART1 + /* install uart1 putc callback */ + os_install_putc1((void *)uart1_write_char); /* print output at UART1 */ } +#endif diff --git a/driver_lib/include/driver/gpio16.h b/driver_lib/include/driver/gpio16.h index 34d05864..f8749967 100644 --- a/driver_lib/include/driver/gpio16.h +++ b/driver_lib/include/driver/gpio16.h @@ -24,10 +24,11 @@ #ifndef __GPIO16_H__ #define __GPIO16_H__ + #include "ets_sys.h" void gpio16_output_conf(void); void gpio16_output_set(uint8_t value); void gpio16_input_conf(void); uint8_t gpio16_input_get(void); -#endif +#endif /* __GPIO16_H__ */ diff --git a/driver_lib/include/driver/hw_timer.h b/driver_lib/include/driver/hw_timer.h index 71af7233..5da736f0 100644 --- a/driver_lib/include/driver/hw_timer.h +++ b/driver_lib/include/driver/hw_timer.h @@ -22,19 +22,20 @@ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ + +#ifndef __HW_TIMER_H__ +#define __HW_TIMER_H__ #include "ets_sys.h" -#ifndef __hw_timer_H__ -#define __hw_timer_H__ -//TIMER PREDIVED MODE + typedef enum { - DIVDED_BY_1 = 0, //timer clock - DIVDED_BY_16 = 4, //divided by 16 - DIVDED_BY_256 = 8, //divided by 256 + DIVDED_BY_1 = 0, + DIVDED_BY_16 = 4, + DIVDED_BY_256 = 8, } time_predived_mode; -typedef enum { //timer interrupt mode - TM_LEVEL_INT = 1, // level interrupt - TM_EDGE_INT = 0, //edge interrupt +typedef enum { + TM_LEVEL_INT = 1, + TM_EDGE_INT = 0, } time_int_mode; typedef enum { @@ -48,4 +49,4 @@ void hw_timer_init(frc1_timer_source_type source_type, uint8_t req); void hw_timer_set_func(void (* user_hw_timer_cb_set)(void)) ; void hw_timer_arm(uint32_t val) ; -#endif +#endif /* __HW_TIMER_H__ */ diff --git a/driver_lib/include/driver/i2c_master.h b/driver_lib/include/driver/i2c_master.h index 856971f9..32b169f5 100644 --- a/driver_lib/include/driver/i2c_master.h +++ b/driver_lib/include/driver/i2c_master.h @@ -33,12 +33,14 @@ #define I2C_MASTER_SDA_FUNC FUNC_GPIO2 #define I2C_MASTER_SCL_FUNC FUNC_GPIO14 -//#define I2C_MASTER_SDA_MUX PERIPHS_IO_MUX_GPIO2_U -//#define I2C_MASTER_SCL_MUX PERIPHS_IO_MUX_GPIO0_U -//#define I2C_MASTER_SDA_GPIO 2 -//#define I2C_MASTER_SCL_GPIO 0 -//#define I2C_MASTER_SDA_FUNC FUNC_GPIO2 -//#define I2C_MASTER_SCL_FUNC FUNC_GPIO0 +/* +#define I2C_MASTER_SDA_MUX PERIPHS_IO_MUX_GPIO2_U +#define I2C_MASTER_SCL_MUX PERIPHS_IO_MUX_GPIO0_U +#define I2C_MASTER_SDA_GPIO 2 +#define I2C_MASTER_SCL_GPIO 0 +#define I2C_MASTER_SDA_FUNC FUNC_GPIO2 +#define I2C_MASTER_SCL_FUNC FUNC_GPIO0 +*/ #if 0 #define I2C_MASTER_GPIO_SET(pin) \ diff --git a/driver_lib/include/driver/key.h b/driver_lib/include/driver/key.h index 79d5a744..e0b5dfff 100644 --- a/driver_lib/include/driver/key.h +++ b/driver_lib/include/driver/key.h @@ -27,6 +27,7 @@ #include "ets_sys.h" #include "gpio.h" #include "os_type.h" + typedef void (* key_function)(void); struct single_key_param { @@ -48,4 +49,4 @@ struct keys_param { struct single_key_param *key_init_single(uint8_t gpio_id, uint32_t gpio_name, uint8_t gpio_func, key_function long_press, key_function short_press); void key_init(struct keys_param *key); -#endif +#endif /* __KEY_H__ */ diff --git a/driver_lib/include/driver/sdio_slv.h b/driver_lib/include/driver/sdio_slv.h index 15183602..abddebd0 100644 --- a/driver_lib/include/driver/sdio_slv.h +++ b/driver_lib/include/driver/sdio_slv.h @@ -24,11 +24,8 @@ #ifndef __SDIO_SLAVE_H__ #define __SDIO_SLAVE_H__ -#include "ets_sys.h" #include "c_types.h" -#include "user_interface.h" - #define RX_AVAILIBLE 2 #define TX_AVAILIBLE 1 #define INIT_STAGE 0 diff --git a/driver_lib/include/driver/slc_register.h b/driver_lib/include/driver/slc_register.h index 7f292d6d..32aeb807 100644 --- a/driver_lib/include/driver/slc_register.h +++ b/driver_lib/include/driver/slc_register.h @@ -1,4 +1,3 @@ -//Generated at 2012-10-23 19:55:03 /* * ESPRESSIF MIT License * @@ -28,7 +27,7 @@ #define SLC_REGISTER_H_ #define REG_SLC_BASE 0x60000B00 -//version value:32'h091700 +/* version value:32'h091700 */ #define SLC_CONF0 (REG_SLC_BASE + 0x0) #ifndef ESP_MAC_5 @@ -246,7 +245,7 @@ #define SLC_RX_EOF_MODE (BIT(19)) #define SLC_RX_FILL_MODE (BIT(18)) #define SLC_INFOR_NO_REPLACE (BIT(17)) -#define SLC_TOKEN_NO_REPLACE (BIT(16)) // +#define SLC_TOKEN_NO_REPLACE (BIT(16)) #define SLC_POP_IDLE_CNT 0x0000FFFF #endif #define SLC_POP_IDLE_CNT_S 0 @@ -276,9 +275,10 @@ #define SLC_HOST_CONF_W5 (REG_SLC_BASE + 0x80 + 0x3C) #define SLC_HOST_INTR_RAW (REG_SLC_BASE + 0x80 + 0x8) #define SLC_HOST_INTR_ENA_BIT (BIT(23)) -//[15:12]: 0x3ff9xxxx -- 0b01 from_host -// 0x3ffaxxxx -- 0b10 general -// 0x3ffbxxxx -- 0b11 to_host + +/* [15:12]: 0x3ff9xxxx -- 0b01 from_host + 0x3ffaxxxx -- 0b10 general + 0x3ffbxxxx -- 0b11 to_host */ #define SLC_DATA_ADDR_CLEAR_MASK (~(0xf<<12)) #define SLC_FROM_HOST_ADDR_MASK (0x1<<12) #define SLC_TO_HOST_ADDR_MASK (0x3<<12) @@ -294,7 +294,7 @@ } while(0); -#define SLC_TX_DESC_DEBUG_REG 0x3ff0002c //[15:0] set to 0xcccc +#define SLC_TX_DESC_DEBUG_REG 0x3ff0002c /* [15:0] set to 0xcccc */ -#endif // SLC_REGISTER_H_INCLUDED +#endif /* SLC_REGISTER_H_ */ diff --git a/driver_lib/include/driver/spi.h b/driver_lib/include/driver/spi.h index 3e538ec9..5a63db08 100644 --- a/driver_lib/include/driver/spi.h +++ b/driver_lib/include/driver/spi.h @@ -22,8 +22,8 @@ * */ -#ifndef SPI_APP_H -#define SPI_APP_H +#ifndef _SPI_H_ +#define _SPI_H_ #include "spi_register.h" #include "ets_sys.h" @@ -41,34 +41,21 @@ #define HSPI 1 void cache_flush(void); -//spi master init funtion void spi_master_init(uint8_t spi_no); - -//lcd drive function void spi_lcd_9bit_write(uint8_t spi_no, uint8_t high_bit, uint8_t low_8bit); -//use spi send 8bit data void spi_mast_byte_write(uint8_t spi_no, uint8_t data); -//transmit data to esp8266 slave buffer,which needs 16bit transmission , -//first byte is master command 0x04, second byte is master data +/* read and write data to esp8266 slave buffer,which needs 16bit transmission , + first byte is master command 0x04, second byte is master data */ void spi_byte_write_espslave(uint8_t spi_no, uint8_t data); -//read data from esp8266 slave buffer,which needs 16bit transmission , -//first byte is master command 0x06, second byte is to read slave data void spi_byte_read_espslave(uint8_t spi_no, uint8_t *data); -//esp8266 slave mode initial void spi_slave_init(uint8_t spi_no, uint8_t data_len); -//esp8266 slave isr handle funtion,tiggered when any transmission is finished. -//the function is registered in spi_slave_init. void spi_slave_isr_handler(void *para); - -//hspi test function, used to test esp8266 spi slave +/* hspi test function, used to test esp8266 spi slave */ void hspi_master_readwrite_repeat(void); - - void spi_test_init(void); - -#endif +#endif /* _SPI_H_ */ diff --git a/driver_lib/include/driver/spi_interface.h b/driver_lib/include/driver/spi_interface.h index 04005e5d..4b5d14e7 100644 --- a/driver_lib/include/driver/spi_interface.h +++ b/driver_lib/include/driver/spi_interface.h @@ -22,21 +22,15 @@ * */ -/** - * @file spi_interface.h - * @brief Defines and Macros for the SPI. - */ #ifndef __SPI_INTERFACE_H__ #define __SPI_INTERFACE_H__ #include "driver/spi_register.h" #include "c_types.h" -//***************************************************************************** -// -// Make sure all of the definitions in this header have a C binding. -// -//***************************************************************************** +/***************************************************************************** + Make sure all of the definitions in this header have a C binding. +*****************************************************************************/ #ifdef __cplusplus extern "C" @@ -88,12 +82,7 @@ typedef enum { SpiSubMode_3 = 3, } SpiSubMode; -/** - * @brief The SPI module working speed. - * - * @attention Max speed 80MHz - * - */ +/* SPI mode working speed */ typedef enum { SpiSpeed_0_5MHz = 160, SpiSpeed_1MHz = 80, @@ -104,16 +93,12 @@ typedef enum { } SpiSpeed; -/** - * @brief The SPI mode working speed. - * - */ typedef enum { SpiBitOrder_MSBFirst = 0, SpiBitOrder_LSBFirst = 1, } SpiBitOrder; -// @brief SPI interrupt soource defined. +/* SPI interrupt soource defined */ typedef enum { SpiIntSrc_TransDone = SPI_TRANS_DONE, SpiIntSrc_WrStaDone = SPI_SLV_WR_STA_DONE, @@ -122,7 +107,7 @@ typedef enum { SpiIntSrc_RdBufDone = SPI_SLV_RD_BUF_DONE, } SpiIntSrc; -// @brief SPI CS pin. +/* SPI CS pin */ typedef enum { SpiPinCS_0 = 1, SpiPinCS_1 = 2, @@ -135,22 +120,22 @@ typedef enum { * @brief SPI attribute */ typedef struct { - SpiMode mode; ///< Master or slave mode - SpiSubMode subMode; ///< SPI SPI_CPOL SPI_CPHA mode - SpiSpeed speed; ///< SPI Clock - SpiBitOrder bitOrder; ///< SPI bit order + SpiMode mode; + SpiSubMode subMode; + SpiSpeed speed; + SpiBitOrder bitOrder; } SpiAttr; /** * @brief SPI data package */ typedef struct { - uint16_t cmd; ///< Command value - uint8_t cmdLen; ///< Command byte length - uint32_t *addr; ///< Point to address value - uint8_t addrLen; ///< Address byte length - uint32_t *data; ///< Point to data buffer - uint8_t dataLen; ///< Data byte length. + uint16_t cmd; + uint8_t cmdLen; + uint32_t *addr; + uint8_t addrLen; + uint32_t *data; + uint8_t dataLen; } SpiData; @@ -158,9 +143,8 @@ typedef struct { * @brief SPI interrupt information */ typedef struct { - SpiIntSrc src; ///< Interrupt source - void *isrFunc; ///< SPI interrupt callback function. - + SpiIntSrc src; + void *isrFunc; } SpiIntInfo; #pragma upack (1) @@ -175,7 +159,7 @@ typedef struct { * * @return void. */ -void SPIInit(SpiNum spiNum, SpiAttr *pAttr); +void spi_init(SpiNum spiNum, SpiAttr *pAttr); /** * @brief Set slave address value by master. @@ -187,7 +171,7 @@ void SPIInit(SpiNum spiNum, SpiAttr *pAttr); * * @return void. */ -void SPIMasterCfgAddr(SpiNum spiNum, uint32_t addr); +void spi_master_config_addr(SpiNum spiNum, uint32_t addr); /** * @brief Set command value by master. @@ -199,7 +183,7 @@ void SPIMasterCfgAddr(SpiNum spiNum, uint32_t addr); * * @return void. */ -void SPIMasterCfgCmd(SpiNum spiNum, uint32_t cmd); +void spi_master_config_cmd(SpiNum spiNum, uint32_t cmd); /** * @brief Send data to slave from master. @@ -211,7 +195,7 @@ void SPIMasterCfgCmd(SpiNum spiNum, uint32_t cmd); * * @return int32_t, -1:indicates failure,others indicates success. */ -int32_t SPIMasterSendData(SpiNum spiNum, SpiData *pInData); +int32_t spi_master_send_data(SpiNum spiNum, SpiData *pInData); /** * @brief Receive data from slave by master. @@ -224,7 +208,7 @@ int32_t SPIMasterSendData(SpiNum spiNum, SpiData *pInData); * @return int32_t, -1:indicates failure,others indicates success. * */ -int32_t SPIMasterRecvData(SpiNum spiNum, SpiData *pOutData); +int32_t spi_master_recv_data(SpiNum spiNum, SpiData *pOutData); /** * @brief Load data to slave send buffer. @@ -238,7 +222,7 @@ int32_t SPIMasterRecvData(SpiNum spiNum, SpiData *pOutData); * * @return int32_t, -1:indicates failure,others indicates success. */ -int32_t SPISlaveSendData(SpiNum spiNum, uint32_t *pInData, uint8_t inLen); +int32_t spi_slave_send_data(SpiNum spiNum, uint32_t *pInData, uint8_t inLen); /** * @brief Receive data by slave. @@ -250,7 +234,7 @@ int32_t SPISlaveSendData(SpiNum spiNum, uint32_t *pInData, uint8_t inLen); * * @return int32_t, -1:indicates failure,others indicates success. */ -int32_t SPISlaveRecvData(SpiNum spiNum); +int32_t spi_slave_recv_data(SpiNum spiNum); /** * @brief Set slave status by master. @@ -264,7 +248,7 @@ int32_t SPISlaveRecvData(SpiNum spiNum); * * @attention Just for ESP8266(slave) register of RD_STATUS or WR_STATUS. */ -void SPIMasterSendStatus(SpiNum spiNum, uint8_t data); +void spi_master_send_status(SpiNum spiNum, uint8_t data); /** * @brief Get salve status by master. @@ -276,7 +260,7 @@ void SPIMasterSendStatus(SpiNum spiNum, uint8_t data); * * @attention Just for ESP8266(slave) register of RD_STATUS or WR_STATUS. */ -int32_t SPIMasterRecvStatus(SpiNum spiNum); +int32_t spi_master_recv_status(SpiNum spiNum); /** * @brief Select SPI CS pin. @@ -288,7 +272,7 @@ int32_t SPIMasterRecvStatus(SpiNum spiNum); * * @return void. */ -void SPICsPinSelect(SpiNum spiNum, SpiPinCS pinCs); +void spi_cs_pin_select(SpiNum spiNum, SpiPinCS pinCs); /** * @brief Set SPI module interrupt source and callback function. @@ -300,7 +284,7 @@ void SPICsPinSelect(SpiNum spiNum, SpiPinCS pinCs); * * @return void. */ -void SPIIntCfg(SpiNum spiNum, SpiIntInfo *pIntInfo); +void spi_int_cfg(SpiNum spiNum, SpiIntInfo *pIntInfo); /** * @brief Enable SPI module interrupt source. @@ -312,7 +296,7 @@ void SPIIntCfg(SpiNum spiNum, SpiIntInfo *pIntInfo); * * @return void. */ -void SPIIntEnable(SpiNum spiNum, SpiIntSrc intSrc); +void spi_int_enable(SpiNum spiNum, SpiIntSrc intSrc); /** * @brief Disable SPI module interrupt source. @@ -324,7 +308,7 @@ void SPIIntEnable(SpiNum spiNum, SpiIntSrc intSrc); * * @return void. */ -void SPIIntDisable(SpiNum spiNum, SpiIntSrc intSrc); +void spi_int_disable(SpiNum spiNum, SpiIntSrc intSrc); /** * @brief Clear all of spi interrupt. @@ -334,10 +318,10 @@ void SPIIntDisable(SpiNum spiNum, SpiIntSrc intSrc); * * @return void. */ -void SPIIntClear(SpiNum spiNum); +void spi_int_clear(SpiNum spiNum); #ifdef __cplusplus } #endif -#endif // __SPI_INTERFACE_H__ +#endif /* __SPI_INTERFACE_H__ */ diff --git a/driver_lib/include/driver/spi_overlap.h b/driver_lib/include/driver/spi_overlap.h index 705a040f..46f33815 100644 --- a/driver_lib/include/driver/spi_overlap.h +++ b/driver_lib/include/driver/spi_overlap.h @@ -22,13 +22,13 @@ * */ -#ifndef SPI_OVERLAP_APP_H -#define SPI_OVERLAP_APP_H +#ifndef SPI_OVERLAP_H_ +#define SPI_OVERLAP_H_ #include "ets_sys.h" #include "spi_flash.h" #define HSPI_OVERLAP -//#define NO_HSPI_DEVICE +/* #define NO_HSPI_DEVICE */ #define HOST_INF_SEL 0x3ff00028 #define FUNC_SPI_CS2 1 #define FUNC_SPI_CS1 1 @@ -82,4 +82,4 @@ void hspi_dev_sel(uint8_t dev_no); void hspi_overlap_flash_init(void); SpiFlashOpResult hspi_overlap_read_flash_data(SpiFlashChip *spi, uint32_t flash_addr, uint32_t *addr_dest, uint32_t byte_length); -#endif +#endif /* SPI_OVERLAP_H_ */ diff --git a/driver_lib/include/driver/spi_register.h b/driver_lib/include/driver/spi_register.h index 4f905824..98d0f603 100644 --- a/driver_lib/include/driver/spi_register.h +++ b/driver_lib/include/driver/spi_register.h @@ -22,8 +22,8 @@ * */ -#ifndef SPI_REGISTER_H_INCLUDED -#define SPI_REGISTER_H_INCLUDED +#ifndef SPI_REGISTER_H_ +#define SPI_REGISTER_H_ #define REG_SPI_BASE(i) (0x60000200-i*0x100) #define SPI_CMD(i) (REG_SPI_BASE(i) + 0x0) @@ -219,4 +219,4 @@ #define SPI_EXT3(i) (REG_SPI_BASE(i) + 0xFC) #define SPI_INT_HOLD_ENA 0x00000003 #define SPI_INT_HOLD_ENA_S 0 -#endif // SPI_REGISTER_H_INCLUDED +#endif /* SPI_REGISTER_H_ */ diff --git a/driver_lib/include/driver/uart.h b/driver_lib/include/driver/uart.h index 6dd2b6fc..baf51201 100644 --- a/driver_lib/include/driver/uart.h +++ b/driver_lib/include/driver/uart.h @@ -25,24 +25,23 @@ #ifndef UART_APP_H #define UART_APP_H -#include "uart_register.h" #include "eagle_soc.h" #include "c_types.h" +#include "driver/uart_register.h" -#define UART_TX_BUFFER_SIZE 256 //Ring buffer length of tx buffer -#define UART_RX_BUFFER_SIZE 256 //Ring buffer length of rx buffer +#define UART_TX_BUFFER_SIZE 256 /* Ring buffer length of tx buffer */ +#define UART_RX_BUFFER_SIZE 256 /* Ring buffer length of rx buffer */ -#define UART_BUFF_EN 0 //use uart buffer , FOR UART0 -#define UART_SELFTEST 0 //set 1:enable the loop test demo for uart buffer, FOR UART0 +#define UART_BUFF_EN 0 /* set 1: use uart buffer, FOR UART0 */ +#define UART_SELFTEST 0 /* set 1: enable the loop test demo for uart buffer, FOR UART0 */ -#define UART_HW_RTS 0 //set 1: enable uart hw flow control RTS, PIN MTDO, FOR UART0 -#define UART_HW_CTS 0 //set1: enable uart hw flow contrl CTS , PIN MTCK, FOR UART0 +#define UART_HW_RTS 0 /* set 1: enable uart hw flow control RTS, PIN MTDO, FOR UART0 */ +#define UART_HW_CTS 0 /* set 1: enable uart hw flow control CTS, PIN MTCK, FOR UART0 */ - - - -#define UART0 0 -#define UART1 1 +typedef enum { + UART0=0x0, + UART1=0x1 +} UARTNum; typedef enum { @@ -50,32 +49,32 @@ typedef enum { SIX_BITS = 0x1, SEVEN_BITS = 0x2, EIGHT_BITS = 0x3 -} UartBitsNum4Char; +} UARTNumBits; typedef enum { ONE_STOP_BIT = 0x1, ONE_HALF_STOP_BIT = 0x2, TWO_STOP_BIT = 0x3 -} UartStopBitsNum; +} UARTStopBits; typedef enum { - NONE_BITS = 0x2, - ODD_BITS = 1, - EVEN_BITS = 0 -} UartParityMode; + EVEN_BITS = 0x0, + ODD_BITS = 0x1, + NONE_BITS = 0x2 +} UARTParity; typedef enum { STICK_PARITY_DIS = 0, STICK_PARITY_EN = 1 -} UartExistParity; +} UARTExistParity; typedef enum { - UART_None_Inverse = 0x0, - UART_Rxd_Inverse = UART_RXD_INV, - UART_CTS_Inverse = UART_CTS_INV, - UART_Txd_Inverse = UART_TXD_INV, - UART_RTS_Inverse = UART_RTS_INV, -} UART_LineLevelInverse; + UART_NONE_INVERSE = 0x0, + UART_RXD_INVERSE = UART_RXD_INV, + UART_CTS_INVERSE = UART_CTS_INV, + UART_TXD_INVERSE = UART_TXD_INV, + UART_RTS_INVERSE = UART_RTS_INV +} UARTLineLevelInverse; typedef enum { @@ -94,136 +93,115 @@ typedef enum { BIT_RATE_460800 = 460800, BIT_RATE_921600 = 921600, BIT_RATE_1843200 = 1843200, - BIT_RATE_3686400 = 3686400, -} UartBautRate; + BIT_RATE_3686400 = 3686400 +} UARTBaudRate; typedef enum { NONE_CTRL, HARDWARE_CTRL, XON_XOFF_CTRL -} UartFlowCtrl; +} UARTFlowCtrl; typedef enum { - USART_HardwareFlowControl_None = 0x0, - USART_HardwareFlowControl_RTS = 0x1, - USART_HardwareFlowControl_CTS = 0x2, - USART_HardwareFlowControl_CTS_RTS = 0x3 -} UART_HwFlowCtrl; + UART_HW_FLOWCONTROL_NONE = 0x0, + UART_HW_FLOWCONTROL_RTS = 0x1, + UART_HW_FLOWCONTROL_CTS = 0x2, + UART_HW_FLOWCONTROL_CTS_RTS = 0x3 +} UARTHwFlowCtrl; typedef enum { EMPTY, UNDER_WRITE, WRITE_OVER -} RcvMsgBuffState; - -typedef struct { - uint32_t RcvBuffSize; - uint8_t *pRcvMsgBuff; - uint8_t *pWritePos; - uint8_t *pReadPos; - uint8_t TrigLvl; //JLU: may need to pad - RcvMsgBuffState BuffState; -} RcvMsgBuff; - -typedef struct { - uint32_t TrxBuffSize; - uint8_t *pTrxBuff; -} TrxMsgBuff; +} UARTRxMsgBuffState; typedef enum { BAUD_RATE_DET, WAIT_SYNC_FRM, SRCH_MSG_HEAD, RCV_MSG_BODY, - RCV_ESC_CHAR, -} RcvMsgState; + RCV_ESC_CHAR +} UARTRxMsgState; -typedef struct { - UartBautRate baut_rate; - UartBitsNum4Char data_bits; - UartExistParity exist_parity; - UartParityMode parity; - UartStopBitsNum stop_bits; - UartFlowCtrl flow_ctrl; - RcvMsgBuff rcv_buff; - TrxMsgBuff trx_buff; - RcvMsgState rcv_state; - int32_t received; - int32_t buff_uart_no; //indicate which uart use tx/rx buffer -} UartDevice; - -void uart_init(UartBautRate uart0_br, UartBautRate uart1_br); -void uart0_sendStr(const char *str); - - -/////////////////////////////////////// -#define UART_FIFO_LEN 128 //define the tx fifo length -#define UART_TX_EMPTY_THRESH_VAL 0x10 +typedef enum { + RUN = 0, + BLOCK = 1 +} TCPState; +typedef struct { + uint32_t rx_buff_size; + uint8_t *p_rx_buff; + uint8_t *p_write_pos; + uint8_t *p_read_pos; + uint8_t trig_lvl; + UARTRxMsgBuffState buff_state; +} UARTRxMsgBuff_t; -struct UartBuffer { - uint32_t UartBuffSize; - uint8_t *pUartBuff; - uint8_t *pInPos; - uint8_t *pOutPos; - STATUS BuffState; - uint16_t Space; //remanent space of the buffer - uint8_t TcpControl; - struct UartBuffer *nextBuff; -}; - -struct UartRxBuff { - uint32_t UartRxBuffSize; - uint8_t *pUartRxBuff; - uint8_t *pWritePos; - uint8_t *pReadPos; - STATUS RxBuffState; - uint32_t Space; //remanent space of the buffer -} ; +typedef struct { + uint32_t tx_buff_size; + uint8_t *p_tx_buff; +} UARTTxMsgBuff_t; -typedef enum { - RUN = 0, - BLOCK = 1, -} TCPState; +typedef struct { + UARTBaudRate baud_rate; + UARTNumBits data_bits; + UARTExistParity exist_parity; + UARTParity parity; + UARTStopBits stop_bits; + UARTFlowCtrl flow_ctrl; + UARTRxMsgBuff_t rx_buff; + UARTTxMsgBuff_t tx_buff; + UARTRxMsgState rx_state; + int32_t received; + int32_t buff_uart_no; /* indicate which uart use tx/rx buffer */ +} UARTDevice_t; + +#define UART_FIFO_LEN 128 /* define the tx fifo length */ +#define UART_TX_EMPTY_THRESH_VAL 0x10 -//void ICACHE_FLASH_ATTR uart_test_rx(); -STATUS uart_tx_one_char(uint8_t uart, uint8_t TxChar); -STATUS uart_tx_one_char_no_wait(uint8_t uart, uint8_t TxChar); -void uart1_sendStr_no_wait(const char *str); -struct UartBuffer *Uart_Buf_Init(); - - -#if UART_BUFF_EN -LOCAL void Uart_Buf_Cpy(struct UartBuffer *pCur, char *pdata, uint16_t data_len); -void uart_buf_free(struct UartBuffer *pBuff); -void tx_buff_enq(char *pdata, uint16_t data_len); -LOCAL void tx_fifo_insert(struct UartBuffer *pTxBuff, uint8_t data_len, uint8_t uart_no); -void tx_start_uart_buffer(uint8_t uart_no); -uint16_t rx_buff_deq(char *pdata, uint16_t data_len); -void Uart_rx_buff_enq(); -#endif -void uart_rx_intr_enable(uint8_t uart_no); -void uart_rx_intr_disable(uint8_t uart_no); -void uart0_tx_buffer(uint8_t *buf, uint16_t len); - -//============================================== -#define FUNC_UART0_CTS 4 -#define FUNC_U0CTS 4 -#define FUNC_U1TXD_BK 2 -#define UART_LINE_INV_MASK (0x3f<<19) -void UART_SetWordLength(uint8_t uart_no, UartBitsNum4Char len); -void UART_SetStopBits(uint8_t uart_no, UartStopBitsNum bit_num); -void UART_SetLineInverse(uint8_t uart_no, UART_LineLevelInverse inverse_mask); -void UART_SetParity(uint8_t uart_no, UartParityMode Parity_mode); -void UART_SetBaudrate(uint8_t uart_no, uint32_t baud_rate); -void UART_SetFlowCtrl(uint8_t uart_no, UART_HwFlowCtrl flow_ctrl, uint8_t rx_thresh); -void UART_WaitTxFifoEmpty(uint8_t uart_no, uint32_t time_out_us); //do not use if tx flow control enabled -void UART_ResetFifo(uint8_t uart_no); -void UART_ClearIntrStatus(uint8_t uart_no, uint32_t clr_mask); -void UART_SetIntrEna(uint8_t uart_no, uint32_t ena_mask); -void UART_SetPrintPort(uint8_t uart_no); -bool UART_CheckOutputFinished(uint8_t uart_no, uint32_t time_out_us); -//============================================== +typedef struct UARTBuffer { + uint32_t buf_size; + uint8_t *p_buf; + uint8_t *p_in_pos; + uint8_t *p_out_pos; + STATUS buf_state; + uint16_t space; /* remaining buffer space */ + uint8_t tcp_control; + struct UARTBuffer *next; +}UARTBuffer_t; + +typedef struct{ + uint32_t buf_size; + uint8_t *p_buf; + uint8_t *p_in_pos; + uint8_t *p_out_pos; + STATUS buf_state; + uint16_t space; /* remaining buffer space */ +} UARTRxBuff_t; + +void uart_rx_intr_enable(UARTNum uart); +void uart_rx_intr_disable(UARTNum uart); + +STATUS uart_tx_one_char(UARTNum uart, uint8_t tx_char); +STATUS uart_tx_one_char_no_wait(UARTNum uart, uint8_t tx_char); +void uart_send_str(UARTNum uart, const char *str); +void uart_send_str_no_wait(UARTNum uart, const char *str); +void uart_tx_send_buffer(UARTNum uart, uint8_t *buf, uint16_t len); + +void uart_init(UARTBaudRate uart0_br, UARTBaudRate uart1_br); +void uart_reattach(void); +void uart_set_num_bits(UARTNum uart, UARTNumBits len); +void uart_set_stop_bits(UARTNum uart, UARTStopBits bits); +void uart_set_line_inverse(UARTNum uart, UARTLineLevelInverse inverse_mask); +void uart_set_parity(UARTNum uart, UARTParity parity); +void uart_set_rate(UARTNum uart, uint32_t baud_rate); +void uart_set_flow_ctrl(UARTNum uart, UARTHwFlowCtrl flow_ctrl, uint8_t rx_thresh); +void uart_wait_tx_fifo_empty(UARTNum uart, uint32_t time_out_us); /* do not use if tx flow control enabled */ +void uart_reset_fifo(UARTNum uart); +void uart_clear_intr_status(UARTNum uart, uint32_t clr_mask); +void uart_set_intr_enable(UARTNum uart, uint32_t ena_mask); +void uart_set_print_port(UARTNum uart); +bool uart_check_output_finished(UARTNum uart, uint32_t time_out_us); #endif diff --git a/driver_lib/include/driver/uart_register.h b/driver_lib/include/driver/uart_register.h index fe4e15e9..66e73a23 100644 --- a/driver_lib/include/driver/uart_register.h +++ b/driver_lib/include/driver/uart_register.h @@ -26,7 +26,7 @@ #define UART_REGISTER_H_ #define REG_UART_BASE(i) (0x60000000 + (i)*0xf00) -//version value:32'h062000 +/* version value:32'h062000 */ #define UART_FIFO(i) (REG_UART_BASE(i) + 0x0) #define UART_RXFIFO_RD_BYTE 0x000000FF @@ -155,5 +155,5 @@ #define UART_DATE(i) (REG_UART_BASE(i) + 0x78) #define UART_ID(i) (REG_UART_BASE(i) + 0x7C) -#endif // UART_REGISTER_H_INCLUDED +#endif /* UART_REGISTER_H_ */ diff --git a/include/at_custom.h b/include/at_custom.h index 0cc6b7f3..8dce9f12 100755 --- a/include/at_custom.h +++ b/include/at_custom.h @@ -28,7 +28,7 @@ #include "c_types.h" #define at_port_print_irom_str(str) do { \ - static const uint8 irom_str[] ICACHE_RODATA_ATTR = str; \ + static const uint8_t irom_str[] ICACHE_RODATA_ATTR = str; \ at_port_print(irom_str); \ } while(0) @@ -42,13 +42,13 @@ typedef struct void (*at_exeCmd)(uint8_t id); }at_funcationType; -typedef void (*at_custom_uart_rx_intr)(uint8* data,int32 len); +typedef void (*at_custom_uart_rx_intr)(uint8_t* data,int32_t len); typedef void (*at_custom_response_func_type)(const char *str); -typedef void (*at_fake_uart_tx_func_type)(const uint8*data,uint32 length); +typedef void (*at_fake_uart_tx_func_type)(const uint8_t*data,uint32_t length); -extern uint8 at_customLinkMax; +extern uint8_t at_customLinkMax; /** * @brief Response "OK" to uart. @@ -82,7 +82,7 @@ void at_register_response_func(at_custom_response_func_type response_func); * cmd_num : the num of at cmd that custom defined * @retval None */ -void at_cmd_array_regist(at_funcationType *custom_at_cmd_array,uint32 cmd_num); +void at_cmd_array_regist(at_funcationType *custom_at_cmd_array,uint32_t cmd_num); /** * @brief get digit form at cmd line.the maybe alter pSrc * @param p_src: at cmd line string @@ -99,7 +99,7 @@ bool at_get_next_int_dec(char **p_src,int*result,int* err); * max_len :max len of string excepted to get * @retval None */ -int32 at_data_str_copy(char *p_dest, char **p_src, int32 max_len); +int32_t at_data_str_copy(char *p_dest, char **p_src, int32_t max_len); /** * @brief initialize at module @@ -141,7 +141,7 @@ void at_leave_special_state(void); * bit15~8 : at test version * bit7~0 : customized version */ -uint32 at_get_version(void); +uint32_t at_get_version(void); /** * @brief register custom uart rx interrupt function @@ -157,7 +157,7 @@ void at_register_uart_rx_intr(at_custom_uart_rx_intr rx_func); * @param length: data length * @retval data len,if ok len == length */ -uint32 at_fake_uart_rx(uint8* data,uint32 length); +uint32_t at_fake_uart_rx(uint8_t* data,uint32_t length); /** * @brief enable fake uart,and register fake uart tx @@ -172,7 +172,7 @@ bool at_fake_uart_enable(bool enable,at_fake_uart_tx_func_type at_fake_uart_tx_f * @param ch: escape character. * @retval TRUE,if set ok,otherwize FALSE. */ -bool at_set_escape_character(uint8 ch); +bool at_set_escape_character(uint8_t ch); /** * @brief Enable wpa2 enterprise command diff --git a/include/c_types.h b/include/c_types.h index aeab8dee..98558611 100755 --- a/include/c_types.h +++ b/include/c_types.h @@ -25,6 +25,8 @@ #ifndef _C_TYPES_H_ #define _C_TYPES_H_ +#ifdef USE_NON_STANDARD_TYPES + typedef unsigned char uint8_t; typedef signed char sint8_t; typedef signed char int8_t; @@ -65,15 +67,29 @@ typedef double real64; typedef unsigned int size_t; -#ifndef __packed -#define __packed __attribute__((packed)) -#endif - #define LOCAL static #ifndef NULL #define NULL (void *)0 -#endif /* NULL */ +#endif + +#ifndef __cplusplus +typedef unsigned char bool; +#define BOOL bool +#define true (1) +#define false (0) +#define TRUE true +#define FALSE false +#endif /* !__cplusplus */ + +#else +#include +#include +#endif + +#ifndef __packed +#define __packed __attribute__((packed)) +#endif /* probably should not put STATUS here */ typedef enum { @@ -102,15 +118,4 @@ typedef enum { #define STORE_ATTR __attribute__((aligned(4))) -#ifndef __cplusplus -typedef unsigned char bool; -#define BOOL bool -#define true (1) -#define false (0) -#define TRUE true -#define FALSE false - - -#endif /* !__cplusplus */ - #endif /* _C_TYPES_H_ */ diff --git a/include/eagle_soc.h b/include/eagle_soc.h index d7015dc7..819eaef9 100644 --- a/include/eagle_soc.h +++ b/include/eagle_soc.h @@ -25,7 +25,7 @@ #ifndef _EAGLE_SOC_H_ #define _EAGLE_SOC_H_ -//Register Bits{{ +/* Register Bits */ #define BIT31 0x80000000 #define BIT30 0x40000000 #define BIT29 0x20000000 @@ -58,9 +58,8 @@ #define BIT2 0x00000004 #define BIT1 0x00000002 #define BIT0 0x00000001 -//}} -//Registers Operation {{ +/* Registers Operation */ #define ETS_UNCACHED_ADDR(addr) (addr) #define ETS_CACHED_ADDR(addr) (addr) @@ -71,62 +70,62 @@ #define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))) #define GET_PERI_REG_BITS(reg, hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)) #define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|((value)<<(shift)) )) -//}} -//Periheral Clock {{ -#define APB_CLK_FREQ 80*1000000 //unit: Hz + +/* Peripheral Clock */ +#define APB_CLK_FREQ 80*1000000 /* unit: Hz */ #define UART_CLK_FREQ APB_CLK_FREQ -#define TIMER_CLK_FREQ (APB_CLK_FREQ>>8) //divided by 256 -//}} +#define TIMER_CLK_FREQ (APB_CLK_FREQ>>8) /* divided by 256*/ + -//Peripheral device base address define{{ +/* Peripheral device base address define */ #define PERIPHS_DPORT_BASEADDR 0x3ff00000 #define PERIPHS_GPIO_BASEADDR 0x60000300 #define PERIPHS_TIMER_BASEDDR 0x60000600 #define PERIPHS_RTC_BASEADDR 0x60000700 #define PERIPHS_IO_MUX 0x60000800 -//}} -//Interrupt remap control registers define{{ + +/* Interrupt remap control registers define*/ #define EDGE_INT_ENABLE_REG (PERIPHS_DPORT_BASEADDR+0x04) #define TM1_EDGE_INT_ENABLE() SET_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT1) #define TM1_EDGE_INT_DISABLE() CLEAR_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT1) -//}} -//GPIO reg {{ + +/* GPIO reg */ #define GPIO_REG_READ(reg) READ_PERI_REG(PERIPHS_GPIO_BASEADDR + reg) #define GPIO_REG_WRITE(reg, val) WRITE_PERI_REG(PERIPHS_GPIO_BASEADDR + reg, val) #define GPIO_OUT_ADDRESS 0x00 #define GPIO_OUT_W1TS_ADDRESS 0x04 #define GPIO_OUT_W1TC_ADDRESS 0x08 -#define GPIO_ENABLE_ADDRESS 0x0c +#define GPIO_ENABLE_ADDRESS 0x0c #define GPIO_ENABLE_W1TS_ADDRESS 0x10 #define GPIO_ENABLE_W1TC_ADDRESS 0x14 -#define GPIO_OUT_W1TC_DATA_MASK 0x0000ffff +#define GPIO_OUT_W1TC_DATA_MASK 0x0000ffff -#define GPIO_IN_ADDRESS 0x18 +#define GPIO_IN_ADDRESS 0x18 -#define GPIO_STATUS_ADDRESS 0x1c -#define GPIO_STATUS_W1TS_ADDRESS 0x20 +#define GPIO_STATUS_ADDRESS 0x1c +#define GPIO_STATUS_W1TS_ADDRESS 0x20 #define GPIO_STATUS_W1TC_ADDRESS 0x24 -#define GPIO_STATUS_INTERRUPT_MASK 0x0000ffff +#define GPIO_STATUS_INTERRUPT_MASK 0x0000ffff -#define GPIO_RTC_CALIB_SYNC PERIPHS_GPIO_BASEADDR+0x6c -#define RTC_CALIB_START BIT31 //first write to zero, then to one to start -#define RTC_PERIOD_NUM_MASK 0x3ff //max 8ms -#define GPIO_RTC_CALIB_VALUE PERIPHS_GPIO_BASEADDR+0x70 -#define RTC_CALIB_RDY_S 31 //after measure, flag to one, when start from zero to one, turn to zero -#define RTC_CALIB_VALUE_MASK 0xfffff +#define GPIO_RTC_CALIB_SYNC PERIPHS_GPIO_BASEADDR+0x6c +#define RTC_CALIB_START BIT31 /* first write to zero, then to one to start */ +#define RTC_PERIOD_NUM_MASK 0x3ff /* max 8ms */ +#define GPIO_RTC_CALIB_VALUE PERIPHS_GPIO_BASEADDR+0x70 +#define RTC_CALIB_RDY_S 31 /* after measure, flag to one, when start from zero to one, turn to zero */ +#define RTC_CALIB_VALUE_MASK 0xfffff -#define GPIO_PIN0_ADDRESS 0x28 +#define GPIO_PIN0_ADDRESS 0x28 -#define GPIO_ID_PIN0 0 -#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n)) -#define GPIO_LAST_REGISTER_ID GPIO_ID_PIN(15) -#define GPIO_ID_NONE 0xffffffff +#define GPIO_ID_PIN0 0 +#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n)) +#define GPIO_LAST_REGISTER_ID GPIO_ID_PIN(15) +#define GPIO_ID_NONE 0xffffffff -#define GPIO_PIN_COUNT 16 +#define GPIO_PIN_COUNT 16 #define GPIO_PIN_CONFIG_MSB 12 #define GPIO_PIN_CONFIG_LSB 11 @@ -163,32 +162,32 @@ #define GPIO_PIN_SOURCE_MASK 0x00000001 #define GPIO_PIN_SOURCE_GET(x) (((x) & GPIO_PIN_SOURCE_MASK) >> GPIO_PIN_SOURCE_LSB) #define GPIO_PIN_SOURCE_SET(x) (((x) << GPIO_PIN_SOURCE_LSB) & GPIO_PIN_SOURCE_MASK) -// }} -// TIMER reg {{ + +/* TIMER reg */ #define RTC_REG_READ(addr) READ_PERI_REG(PERIPHS_TIMER_BASEDDR + addr) #define RTC_REG_WRITE(addr, val) WRITE_PERI_REG(PERIPHS_TIMER_BASEDDR + addr, val) #define RTC_CLR_REG_MASK(reg, mask) CLEAR_PERI_REG_MASK(PERIPHS_TIMER_BASEDDR +reg, mask) /* Returns the current time according to the timer timer. */ #define NOW() RTC_REG_READ(FRC2_COUNT_ADDRESS) -//load initial_value to timer1 +/* load initial_value to timer1 */ #define FRC1_LOAD_ADDRESS 0x00 -//timer1's counter value(count from initial_value to 0) +/* timer1's counter value(count from initial_value to 0) */ #define FRC1_COUNT_ADDRESS 0x04 #define FRC1_CTRL_ADDRESS 0x08 -//clear timer1's interrupt when write this address +/* clear timer1's interrupt when write this address */ #define FRC1_INT_ADDRESS 0x0c #define FRC1_INT_CLR_MASK 0x00000001 -//timer2's counter value(count from initial_value to 0) +/* timer2's counter value(count from initial_value to 0) */ #define FRC2_COUNT_ADDRESS 0x24 -// }} -//RTC reg {{ + +/* RTC reg */ #define REG_RTC_BASE PERIPHS_RTC_BASEADDR #define RTC_STORE0 (REG_RTC_BASE + 0x030) @@ -201,9 +200,9 @@ #define RTC_GPIO_IN_DATA (REG_RTC_BASE + 0x08C) #define RTC_GPIO_CONF (REG_RTC_BASE + 0x090) #define PAD_XPD_DCDC_CONF (REG_RTC_BASE + 0x0A0) -//}} -//PIN Mux reg {{ + +/* PIN Mux reg */ #define PERIPHS_IO_MUX_FUNC 0x13 #define PERIPHS_IO_MUX_FUNC_S 4 #define PERIPHS_IO_MUX_PULLUP BIT7 @@ -274,6 +273,6 @@ |( (((FUNC&BIT2)<<2)|(FUNC&0x3))<>gpio_no)&BIT0) /* GPIO interrupt handler, registered through gpio_intr_handler_register */ -typedef void (* gpio_intr_handler_fn_t)(uint32 intr_mask, void *arg); +typedef void (* gpio_intr_handler_fn_t)(uint32_t intr_mask, void *arg); /* @@ -67,15 +68,15 @@ void gpio_init(void); * writes is significant, calling code should divide a single call * into multiple calls. */ -void gpio_output_set(uint32 set_mask, - uint32 clear_mask, - uint32 enable_mask, - uint32 disable_mask); +void gpio_output_set(uint32_t set_mask, + uint32_t clear_mask, + uint32_t enable_mask, + uint32_t disable_mask); /* * Sample the value of GPIO input pins and returns a bitmask. */ -uint32 gpio_input_get(void); +uint32_t gpio_input_get(void); /* * Set the specified GPIO register to the specified value. @@ -83,10 +84,10 @@ uint32 gpio_input_get(void); * expected to be used during normal operation. It is intended * mainly for debug, or for unusual requirements. */ -void gpio_register_set(uint32 reg_id, uint32 value); +void gpio_register_set(uint32_t reg_id, uint32_t value); /* Get the current value of the specified GPIO register. */ -uint32 gpio_register_get(uint32 reg_id); +uint32_t gpio_register_get(uint32_t reg_id); /* * Register an application-specific interrupt handler for GPIO pin @@ -102,18 +103,18 @@ uint32 gpio_register_get(uint32 reg_id); void gpio_intr_handler_register(gpio_intr_handler_fn_t fn, void *arg); /* Determine which GPIO interrupts are pending. */ -uint32 gpio_intr_pending(void); +uint32_t gpio_intr_pending(void); /* * Acknowledge GPIO interrupts. * Intended to be called from the gpio_intr_handler_fn. */ -void gpio_intr_ack(uint32 ack_mask); +void gpio_intr_ack(uint32_t ack_mask); -void gpio_pin_wakeup_enable(uint32 i, GPIO_INT_TYPE intr_state); +void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state); -void gpio_pin_wakeup_disable(); +void gpio_pin_wakeup_disable(void); -void gpio_pin_intr_state_set(uint32 i, GPIO_INT_TYPE intr_state); +void gpio_pin_intr_state_set(uint32_t i, GPIO_INT_TYPE intr_state); -#endif // _GPIO_H_ +#endif /* _GPIO_H_ */ diff --git a/include/ip_addr.h b/include/ip_addr.h index 2f2767e7..61e58538 100644 --- a/include/ip_addr.h +++ b/include/ip_addr.h @@ -28,7 +28,7 @@ #include "c_types.h" struct ip_addr { - uint32 addr; + uint32_t addr; }; typedef struct ip_addr ip_addr_t; @@ -55,27 +55,27 @@ struct ip_info { /** Set an IP address given by the four byte-parts. Little-endian version that prevents the use of htonl. */ #define IP4_ADDR(ipaddr, a,b,c,d) \ - (ipaddr)->addr = ((uint32)((d) & 0xff) << 24) | \ - ((uint32)((c) & 0xff) << 16) | \ - ((uint32)((b) & 0xff) << 8) | \ - (uint32)((a) & 0xff) + (ipaddr)->addr = ((uint32_t)((d) & 0xff) << 24) | \ + ((uint32_t)((c) & 0xff) << 16) | \ + ((uint32_t)((b) & 0xff) << 8) | \ + (uint32_t)((a) & 0xff) -#define ip4_addr1(ipaddr) (((uint8*)(ipaddr))[0]) -#define ip4_addr2(ipaddr) (((uint8*)(ipaddr))[1]) -#define ip4_addr3(ipaddr) (((uint8*)(ipaddr))[2]) -#define ip4_addr4(ipaddr) (((uint8*)(ipaddr))[3]) +#define ip4_addr1(ipaddr) (((uint8_t*)(ipaddr))[0]) +#define ip4_addr2(ipaddr) (((uint8_t*)(ipaddr))[1]) +#define ip4_addr3(ipaddr) (((uint8_t*)(ipaddr))[2]) +#define ip4_addr4(ipaddr) (((uint8_t*)(ipaddr))[3]) -#define ip4_addr1_16(ipaddr) ((uint16)ip4_addr1(ipaddr)) -#define ip4_addr2_16(ipaddr) ((uint16)ip4_addr2(ipaddr)) -#define ip4_addr3_16(ipaddr) ((uint16)ip4_addr3(ipaddr)) -#define ip4_addr4_16(ipaddr) ((uint16)ip4_addr4(ipaddr)) +#define ip4_addr1_16(ipaddr) ((uint16_t)ip4_addr1(ipaddr)) +#define ip4_addr2_16(ipaddr) ((uint16_t)ip4_addr2(ipaddr)) +#define ip4_addr3_16(ipaddr) ((uint16_t)ip4_addr3(ipaddr)) +#define ip4_addr4_16(ipaddr) ((uint16_t)ip4_addr4(ipaddr)) /** 255.255.255.255 */ -#define IPADDR_NONE ((uint32)0xffffffffUL) +#define IPADDR_NONE ((uint32_t)0xffffffffUL) /** 0.0.0.0 */ -#define IPADDR_ANY ((uint32)0x00000000UL) -uint32 ipaddr_addr(const char *cp); +#define IPADDR_ANY ((uint32_t)0x00000000UL) +uint32_t ipaddr_addr(const char *cp); #define IP2STR(ipaddr) ip4_addr1_16(ipaddr), \ ip4_addr2_16(ipaddr), \ diff --git a/include/json/jsontree.h b/include/json/jsontree.h index 0ffe9d15..d6e92ea8 100644 --- a/include/json/jsontree.h +++ b/include/json/jsontree.h @@ -132,7 +132,7 @@ const char *jsontree_path_name(const struct jsontree_context *js_ctx, int depth); void jsontree_write_int(const struct jsontree_context *js_ctx, int value); -void jsontree_write_int_array(const struct jsontree_context *js_ctx, const int *text, uint32 length); +void jsontree_write_int_array(const struct jsontree_context *js_ctx, const int *text, uint32_t length); void jsontree_write_atom(const struct jsontree_context *js_ctx, const char *text); diff --git a/include/osapi.h b/include/osapi.h index 317e907c..43b70541 100755 --- a/include/osapi.h +++ b/include/osapi.h @@ -26,6 +26,7 @@ #define _OSAPI_H_ #include +#include #include "os_type.h" #include "user_config.h" @@ -76,6 +77,7 @@ void ets_timer_setfn(os_timer_t *ptimer, os_timer_func_t *pfunction, void *parg) int ets_sprintf(char *str, const char *format, ...) __attribute__ ((format (printf, 2, 3))); int os_printf_plus(const char *format, ...) __attribute__ ((format (printf, 1, 2))); int ets_snprintf(char *str, unsigned int size, const char *format, ...) __attribute__ ((format (printf, 3, 4))); +int ets_vsnprintf(char *str, unsigned int size, const char *format, va_list argptr); #define os_sprintf_plus ets_sprintf #define os_sprintf(buf, fmt, ...) os_sprintf_plus(buf, fmt, ##__VA_ARGS__) diff --git a/include/ping.h b/include/ping.h index 6537a7a4..815b2c65 100644 --- a/include/ping.h +++ b/include/ping.h @@ -25,28 +25,27 @@ #ifndef __PING_H__ #define __PING_H__ - typedef void (* ping_recv_function)(void* arg, void *pdata); typedef void (* ping_sent_function)(void* arg, void *pdata); struct ping_option{ - uint32 count; - uint32 ip; - uint32 coarse_time; + uint32_t count; + uint32_t ip; + uint32_t coarse_time; ping_recv_function recv_function; ping_sent_function sent_function; void* reverse; }; struct ping_resp{ - uint32 total_count; - uint32 resp_time; - uint32 seqno; - uint32 timeout_count; - uint32 bytes; - uint32 total_bytes; - uint32 total_time; - sint8 ping_err; + uint32_t total_count; + uint32_t resp_time; + uint32_t seqno; + uint32_t timeout_count; + uint32_t bytes; + uint32_t total_bytes; + uint32_t total_time; + int8_t ping_err; }; bool ping_start(struct ping_option *ping_opt); diff --git a/include/pwm.h b/include/pwm.h index eae782f8..a8a0f78c 100644 --- a/include/pwm.h +++ b/include/pwm.h @@ -36,23 +36,23 @@ #define PWM_CHANNEL_NUM_MAX 8 struct pwm_param { - uint32 period; - uint32 freq; - uint32 duty[PWM_CHANNEL_NUM_MAX]; //PWM_CHANNEL<=8 + uint32_t period; + uint32_t freq; + uint32_t duty[PWM_CHANNEL_NUM_MAX]; /* PWM_CHANNEL<=8 */ }; /* pwm_init should be called only once, for now */ -void pwm_init(uint32 period, uint32 *duty,uint32 pwm_channel_num,uint32 (*pin_info_list)[3]); +void pwm_init(uint32_t period, uint32_t *duty,uint32_t pwm_channel_num,uint32_t (*pin_info_list)[3]); void pwm_start(void); -void pwm_set_duty(uint32 duty, uint8 channel); -uint32 pwm_get_duty(uint8 channel); -void pwm_set_period(uint32 period); -uint32 pwm_get_period(void); +void pwm_set_duty(uint32_t duty, uint8_t channel); +uint32_t pwm_get_duty(uint8_t channel); +void pwm_set_period(uint32_t period); +uint32_t pwm_get_period(void); -uint32 get_pwm_version(void); -void set_pwm_debug_en(uint8 print_en); +uint32_t get_pwm_version(void); +void set_pwm_debug_en(uint8_t print_en); #endif diff --git a/include/simple_pair.h b/include/simple_pair.h index 80148094..71fb3846 100644 --- a/include/simple_pair.h +++ b/include/simple_pair.h @@ -34,14 +34,14 @@ typedef enum { SP_ST_WAIT_TIMEOUT, SP_ST_SEND_ERROR, SP_ST_KEY_INSTALL_ERR, - SP_ST_KEY_OVERLAP_ERR, //means the same macaddr has two different keys + SP_ST_KEY_OVERLAP_ERR, /* means the same macaddr has two different keys */ SP_ST_OP_ERROR, SP_ST_UNKNOWN_ERROR, SP_ST_MAX, } SP_ST_t; -typedef void (*simple_pair_status_cb_t)(u8 *sa, u8 status); +typedef void (*simple_pair_status_cb_t)(uint8_t *sa, uint8_t status); int register_simple_pair_status_cb(simple_pair_status_cb_t cb); void unregister_simple_pair_status_cb(void); @@ -57,8 +57,8 @@ int simple_pair_sta_start_negotiate(void); int simple_pair_ap_start_negotiate(void); int simple_pair_ap_refuse_negotiate(void); -int simple_pair_set_peer_ref(u8 *peer_mac, u8 *tmp_key, u8 *ex_key); -int simple_pair_get_peer_ref(u8 *peer_mac, u8 *tmp_key, u8 *ex_key); +int simple_pair_set_peer_ref(uint8_t *peer_mac, uint8_t *tmp_key, uint8_t *ex_key); +int simple_pair_get_peer_ref(uint8_t *peer_mac, uint8_t *tmp_key, uint8_t *ex_key); #endif /* __SIMPLE_PAIR_H__ */ diff --git a/include/smartconfig.h b/include/smartconfig.h index 6f3802ad..6b3574f3 100644 --- a/include/smartconfig.h +++ b/include/smartconfig.h @@ -44,7 +44,7 @@ typedef void (*sc_callback_t)(sc_status status, void *pdata); const char *smartconfig_get_version(void); bool smartconfig_start(sc_callback_t cb, ...); bool smartconfig_stop(void); -bool esptouch_set_timeout(uint8 time_s); //15s~255s, offset:45s +bool esptouch_set_timeout(uint8_t time_s); /* 15s~255s, offset:45s */ bool smartconfig_set_type(sc_type type); #endif diff --git a/include/sntp.h b/include/sntp.h index db027489..30f4177f 100644 --- a/include/sntp.h +++ b/include/sntp.h @@ -10,19 +10,19 @@ /** * get the seconds since Jan 01, 1970, 00:00 (GMT + 8) */ -uint32 sntp_get_current_timestamp(); +uint32_t sntp_get_current_timestamp(void); /** * get real time (GTM + 8 time zone) */ -char* sntp_get_real_time(long t); +char* sntp_get_real_time(uint32_t t); /** * SNTP get time_zone default GMT + 8 */ -sint8 sntp_get_timezone(void); +int8_t sntp_get_timezone(void); /** * SNTP set time_zone (default GMT + 8) */ -bool sntp_set_timezone(sint8 timezone); +bool sntp_set_timezone(int8_t timezone); /** * Initialize this module. * Send out request instantly or after SNTP_STARTUP_DELAY(_FUNC). @@ -38,7 +38,7 @@ void sntp_stop(void); * @param numdns the index of the NTP server to set must be < SNTP_MAX_SERVERS * @param dnsserver IP address of the NTP server to set */ -void sntp_setserver(unsigned char idx, ip_addr_t *addr); +void sntp_setserver(uint8_t idx, ip_addr_t *addr); /** * Obtain one of the currently configured by IP address (or DHCP) NTP servers * @@ -46,14 +46,14 @@ void sntp_setserver(unsigned char idx, ip_addr_t *addr); * @return IP address of the indexed NTP server or "ip_addr_any" if the NTP * server has not been configured by address (or at all). */ -ip_addr_t sntp_getserver(unsigned char idx); +ip_addr_t sntp_getserver(uint8_t idx); /** * Initialize one of the NTP servers by name * * @param numdns the index of the NTP server to set must be < SNTP_MAX_SERVERS,now sdk support SNTP_MAX_SERVERS = 3 * @param dnsserver DNS name of the NTP server to set, to be resolved at contact time */ -void sntp_setservername(unsigned char idx, char *server); +void sntp_setservername(uint8_t idx, const char *server); /** * Obtain one of the currently configured by name NTP servers. * @@ -61,7 +61,7 @@ void sntp_setservername(unsigned char idx, char *server); * @return IP address of the indexed NTP server or NULL if the NTP * server has not been configured by name (or at all) */ -char *sntp_getservername(unsigned char idx); +char *sntp_getservername(uint8_t idx); #define sntp_servermode_dhcp(x) diff --git a/include/spi_flash.h b/include/spi_flash.h index 2ff47865..cefab134 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -24,6 +24,7 @@ #ifndef SPI_FLASH_H #define SPI_FLASH_H +#include typedef enum { SPI_FLASH_RESULT_OK, @@ -32,26 +33,26 @@ typedef enum { } SpiFlashOpResult; typedef struct{ - uint32 deviceId; - uint32 chip_size; // chip size in byte - uint32 block_size; - uint32 sector_size; - uint32 page_size; - uint32 status_mask; + uint32_t deviceId; + uint32_t chip_size; /* chip size in byte */ + uint32_t block_size; + uint32_t sector_size; + uint32_t page_size; + uint32_t status_mask; } SpiFlashChip; #define SPI_FLASH_SEC_SIZE 4096 -uint32 spi_flash_get_id(void); -SpiFlashOpResult spi_flash_erase_sector(uint16 sec); -SpiFlashOpResult spi_flash_write(uint32 des_addr, uint32 *src_addr, uint32 size); -SpiFlashOpResult spi_flash_read(uint32 src_addr, uint32 *des_addr, uint32 size); +uint32_t spi_flash_get_id(void); +SpiFlashOpResult spi_flash_erase_sector(uint16_t sec); +SpiFlashOpResult spi_flash_write(uint32_t des_addr, uint32_t *src_addr, uint32_t size); +SpiFlashOpResult spi_flash_read(uint32_t src_addr, uint32_t *des_addr, uint32_t size); typedef SpiFlashOpResult (* user_spi_flash_read)( SpiFlashChip *spi, - uint32 src_addr, - uint32 *des_addr, - uint32 size); + uint32_t src_addr, + uint32_t *des_addr, + uint32_t size); void spi_flash_set_read_func(user_spi_flash_read read); diff --git a/include/upgrade.h b/include/upgrade.h index e7e69681..29d4de4b 100644 --- a/include/upgrade.h +++ b/include/upgrade.h @@ -40,19 +40,19 @@ typedef void (*upgrade_states_check_callback)(void * arg); -//#define UPGRADE_SSL_ENABLE +/* #define UPGRADE_SSL_ENABLE */ struct upgrade_server_info { - uint8 ip[4]; - uint16 port; + uint8_t ip[4]; + uint16_t port; - uint8 upgrade_flag; + uint8_t upgrade_flag; - uint8 pre_version[16]; - uint8 upgrade_version[16]; + uint8_t pre_version[16]; + uint8_t upgrade_version[16]; - uint32 check_times; - uint8 *url; + uint32_t check_times; + uint8_t *url; upgrade_states_check_callback check_cb; struct espconn *pespconn; @@ -62,12 +62,12 @@ struct upgrade_server_info { #define UPGRADE_FLAG_START 0x01 #define UPGRADE_FLAG_FINISH 0x02 -void system_upgrade_init(); -void system_upgrade_deinit(); -bool system_upgrade(uint8 *data, uint16 len); +void system_upgrade_init(void); +void system_upgrade_deinit(void); +bool system_upgrade(uint8_t *data, uint16_t len); #ifdef UPGRADE_SSL_ENABLE -bool system_upgrade_start_ssl(struct upgrade_server_info *server); // not supported now +bool system_upgrade_start_ssl(struct upgrade_server_info *server); /* not supported now */ #else bool system_upgrade_start(struct upgrade_server_info *server); #endif diff --git a/include/user_interface.h b/include/user_interface.h index aab9affa..43e16ba9 100755 --- a/include/user_interface.h +++ b/include/user_interface.h @@ -25,6 +25,7 @@ #ifndef __USER_INTERFACE_H__ #define __USER_INTERFACE_H__ +#include "c_types.h" #include "os_type.h" #ifdef LWIP_OPEN_SRC #include "lwip/ip_addr.h" @@ -53,13 +54,13 @@ enum rst_reason { }; struct rst_info{ - uint32 reason; - uint32 exccause; - uint32 epc1; - uint32 epc2; - uint32 epc3; - uint32 excvaddr; - uint32 depc; + uint32_t reason; + uint32_t exccause; + uint32_t epc1; + uint32_t epc2; + uint32_t epc3; + uint32_t excvaddr; + uint32_t depc; }; struct rst_info* system_get_rst_info(void); @@ -70,17 +71,17 @@ struct rst_info* system_get_rst_info(void); void system_restore(void); void system_restart(void); -bool system_deep_sleep_set_option(uint8 option); -bool system_deep_sleep(uint64 time_in_us); -bool system_deep_sleep_instant(uint64 time_in_us); +bool system_deep_sleep_set_option(uint8_t option); +bool system_deep_sleep(uint64_t time_in_us); +bool system_deep_sleep_instant(uint64_t time_in_us); -uint8 system_upgrade_userbin_check(void); +uint8_t system_upgrade_userbin_check(void); void system_upgrade_reboot(void); -uint8 system_upgrade_flag_check(); -void system_upgrade_flag_set(uint8 flag); +uint8_t system_upgrade_flag_check(void); +void system_upgrade_flag_set(uint8_t flag); void system_timer_reinit(void); -uint32 system_get_time(void); +uint32_t system_get_time(void); /* user task's prio must be 0/1/2 !!!*/ enum { @@ -90,35 +91,35 @@ enum { USER_TASK_PRIO_MAX }; -bool system_os_task(os_task_t task, uint8 prio, os_event_t *queue, uint8 qlen); -bool system_os_post(uint8 prio, os_signal_t sig, os_param_t par); +bool system_os_task(os_task_t task, uint8_t prio, os_event_t *queue, uint8_t qlen); +bool system_os_post(uint8_t prio, os_signal_t sig, os_param_t par); void system_print_meminfo(void); -uint32 system_get_free_heap_size(void); +uint32_t system_get_free_heap_size(void); -void system_set_os_print(uint8 onoff); -uint8 system_get_os_print(); +void system_set_os_print(uint8_t onoff); +uint8_t system_get_os_print(void); -uint64 system_mktime(uint32 year, uint32 mon, uint32 day, uint32 hour, uint32 min, uint32 sec); +uint64_t system_mktime(uint32_t year, uint32_t mon, uint32_t day, uint32_t hour, uint32_t min, uint32_t sec); -uint32 system_get_chip_id(void); +uint32_t system_get_chip_id(void); typedef void (* init_done_cb_t)(void); void system_init_done_cb(init_done_cb_t cb); -uint32 system_rtc_clock_cali_proc(void); -uint32 system_get_rtc_time(void); +uint32_t system_rtc_clock_cali_proc(void); +uint32_t system_get_rtc_time(void); -bool system_rtc_mem_read(uint8 src_addr, void *des_addr, uint16 load_size); -bool system_rtc_mem_write(uint8 des_addr, const void *src_addr, uint16 save_size); +bool system_rtc_mem_read(uint8_t src_addr, void *des_addr, uint16_t load_size); +bool system_rtc_mem_write(uint8_t des_addr, const void *src_addr, uint16_t save_size); void system_uart_swap(void); void system_uart_de_swap(void); -uint16 system_adc_read(void); -void system_adc_read_fast(uint16 *adc_addr, uint16 adc_num, uint8 adc_clk_div); -uint16 system_get_vdd33(void); +uint16_t system_adc_read(void); +void system_adc_read_fast(uint16_t *adc_addr, uint16_t adc_num, uint8_t adc_clk_div); +uint16_t system_get_vdd33(void); const char *system_get_sdk_version(void); @@ -128,16 +129,16 @@ const char *system_get_sdk_version(void); #define SYS_BOOT_NORMAL_BIN 0 #define SYS_BOOT_TEST_BIN 1 -uint8 system_get_boot_version(void); -uint32 system_get_userbin_addr(void); -uint8 system_get_boot_mode(void); -bool system_restart_enhance(uint8 bin_type, uint32 bin_addr); +uint8_t system_get_boot_version(void); +uint32_t system_get_userbin_addr(void); +uint8_t system_get_boot_mode(void); +bool system_restart_enhance(uint8_t bin_type, uint32_t bin_addr); #define SYS_CPU_80MHZ 80 #define SYS_CPU_160MHZ 160 -bool system_update_cpu_freq(uint8 freq); -uint8 system_get_cpu_freq(void); +bool system_update_cpu_freq(uint8_t freq); +uint8_t system_get_cpu_freq(void); enum flash_size_map { FLASH_SIZE_4M_MAP_256_256 = 0, /**< Flash size : 4Mbits. Map : 256KBytes + 256KBytes */ @@ -155,13 +156,14 @@ enum flash_size_map { enum flash_size_map system_get_flash_size_map(void); -void system_phy_set_max_tpw(uint8 max_tpw); -void system_phy_set_tpw_via_vdd33(uint16 vdd33); -void system_phy_set_rfoption(uint8 option); -void system_phy_set_powerup_option(uint8 option); +void system_phy_set_max_tpw(uint8_t max_tpw); +void system_phy_set_tpw_via_vdd33(uint16_t vdd33); +void system_phy_set_rfoption(uint8_t option); +void system_phy_set_powerup_option(uint8_t option); +void system_phy_freq_trace_enable(bool enable); -bool system_param_save_with_protect(uint16 start_sec, void *param, uint16 len); -bool system_param_load(uint16 start_sec, uint16 offset, void *param, uint16 len); +bool system_param_save_with_protect(uint16_t start_sec, void *param, uint16_t len); +bool system_param_load(uint16_t start_sec, uint16_t offset, void *param, uint16_t len); void system_soft_wdt_stop(void); void system_soft_wdt_restart(void); @@ -193,27 +195,27 @@ typedef enum _cipher_type { CIPHER_UNKNOWN, } CIPHER_TYPE; -uint8 wifi_get_opmode(void); -uint8 wifi_get_opmode_default(void); -bool wifi_set_opmode(uint8 opmode); -bool wifi_set_opmode_current(uint8 opmode); -uint8 wifi_get_broadcast_if(void); -bool wifi_set_broadcast_if(uint8 interface); +uint8_t wifi_get_opmode(void); +uint8_t wifi_get_opmode_default(void); +bool wifi_set_opmode(uint8_t opmode); +bool wifi_set_opmode_current(uint8_t opmode); +uint8_t wifi_get_broadcast_if(void); +bool wifi_set_broadcast_if(uint8_t interface); struct bss_info { STAILQ_ENTRY(bss_info) next; - uint8 bssid[6]; - uint8 ssid[32]; - uint8 ssid_len; - uint8 channel; - sint8 rssi; + uint8_t bssid[6]; + uint8_t ssid[32]; + uint8_t ssid_len; + uint8_t channel; + int8_t rssi; AUTH_MODE authmode; - uint8 is_hidden; - sint16 freq_offset; - sint16 freqcal_val; - uint8 *esp_mesh_ie; - uint8 simple_pair; + uint8_t is_hidden; + int16_t freq_offset; + int16_t freqcal_val; + uint8_t *esp_mesh_ie; + uint8_t simple_pair; CIPHER_TYPE pairwise_cipher; CIPHER_TYPE group_cipher; uint32_t phy_11b:1; @@ -226,28 +228,28 @@ struct bss_info { typedef struct _scaninfo { STAILQ_HEAD(, bss_info) *pbss; struct espconn *pespconn; - uint8 totalpage; - uint8 pagenum; - uint8 page_sn; - uint8 data_cnt; + uint8_t totalpage; + uint8_t pagenum; + uint8_t page_sn; + uint8_t data_cnt; } scaninfo; typedef void (* scan_done_cb_t)(void *arg, STATUS status); typedef struct { - int8 rssi; + int8_t rssi; AUTH_MODE authmode; } wifi_fast_scan_threshold_t; struct station_config { - uint8 ssid[32]; - uint8 password[64]; - uint8 channel; - uint8 bssid_set; // Note: If bssid_set is 1, station will just connect to the router - // with both ssid[] and bssid[] matched. Please check about this. - uint8 bssid[6]; + uint8_t ssid[32]; + uint8_t password[64]; + uint8_t channel; + uint8_t bssid_set; /* Note: If bssid_set is 1, station will just connect to the router */ + /* with both ssid[] and bssid[] matched. Please check about this. */ + uint8_t bssid[6]; wifi_fast_scan_threshold_t threshold; - bool open_and_wep_mode_disable; // Can connect to open/wep router by default. + bool open_and_wep_mode_disable; /* Can connect to open/wep router by default.*/ bool all_channel_scan; }; @@ -262,7 +264,7 @@ bool wifi_station_disconnect(void); void wifi_enable_signaling_measurement(void); void wifi_disable_signaling_measurement(void); -sint8 wifi_station_get_rssi(void); +int8_t wifi_station_get_rssi(void); typedef enum { WIFI_SCAN_TYPE_ACTIVE = 0, /**< active scan */ @@ -284,18 +286,18 @@ typedef union { } wifi_scan_time_t; struct scan_config { - uint8 *ssid; // Note: ssid == NULL, don't filter ssid. - uint8 *bssid; // Note: bssid == NULL, don't filter bssid. - uint8 channel; // Note: channel == 0, scan all channels, otherwise scan set channel. - uint8 show_hidden; // Note: show_hidden == 1, can get hidden ssid routers' info. - wifi_scan_type_t scan_type; // scan type, active or passive - wifi_scan_time_t scan_time; // scan time per channel + uint8_t *ssid; /* Note: ssid == NULL, don't filter ssid. */ + uint8_t *bssid; /* Note: bssid == NULL, don't filter bssid. */ + uint8_t channel; /* Note: channel == 0, scan all channels, otherwise scan set channel. */ + uint8_t show_hidden; /* Note: show_hidden == 1, can get hidden ssid routers' info. */ + wifi_scan_type_t scan_type; /* scan type, active or passive */ + wifi_scan_time_t scan_time; /* scan time per channel */ }; bool wifi_station_scan(struct scan_config *config, scan_done_cb_t cb); -uint8 wifi_station_get_auto_connect(void); -bool wifi_station_set_auto_connect(uint8 set); +uint8_t wifi_station_get_auto_connect(void); +bool wifi_station_set_auto_connect(uint8_t set); bool wifi_station_set_reconnect_policy(bool set); @@ -313,37 +315,37 @@ enum dhcp_status { DHCP_STARTED }; -uint8 wifi_station_get_connect_status(void); +uint8_t wifi_station_get_connect_status(void); -uint8 wifi_station_get_current_ap_id(void); -bool wifi_station_ap_change(uint8 current_ap_id); -bool wifi_station_ap_number_set(uint8 ap_number); -uint8 wifi_station_get_ap_info(struct station_config config[]); +uint8_t wifi_station_get_current_ap_id(void); +bool wifi_station_ap_change(uint8_t current_ap_id); +bool wifi_station_ap_number_set(uint8_t ap_number); +uint8_t wifi_station_get_ap_info(struct station_config config[]); bool wifi_station_dhcpc_start(void); bool wifi_station_dhcpc_stop(void); enum dhcp_status wifi_station_dhcpc_status(void); -bool wifi_station_dhcpc_set_maxtry(uint8 num); +bool wifi_station_dhcpc_set_maxtry(uint8_t num); char* wifi_station_get_hostname(void); bool wifi_station_set_hostname(char *name); -int wifi_station_set_cert_key(uint8 *client_cert, int client_cert_len, - uint8 *private_key, int private_key_len, - uint8 *private_key_passwd, int private_key_passwd_len); +int wifi_station_set_cert_key(uint8_t *client_cert, int client_cert_len, + uint8_t *private_key, int private_key_len, + uint8_t *private_key_passwd, int private_key_passwd_len); void wifi_station_clear_cert_key(void); -int wifi_station_set_username(uint8 *username, int len); +int wifi_station_set_username(uint8_t *username, int len); void wifi_station_clear_username(void); struct softap_config { - uint8 ssid[32]; - uint8 password[64]; - uint8 ssid_len; // Note: Recommend to set it according to your ssid - uint8 channel; // Note: support 1 ~ 13 - AUTH_MODE authmode; // Note: Don't support AUTH_WEP in softAP mode. - uint8 ssid_hidden; // Note: default 0 - uint8 max_connection; // Note: default 4, max 4 - uint16 beacon_interval; // Note: support 100 ~ 60000 ms, default 100 + uint8_t ssid[32]; + uint8_t password[64]; + uint8_t ssid_len; /* Note: Recommend to set it according to your ssid */ + uint8_t channel; /* Note: support 1 ~ 13 */ + AUTH_MODE authmode; /* Note: Don't support AUTH_WEP in softAP mode. */ + uint8_t ssid_hidden; /* Note: default 0 */ + uint8_t max_connection; /* Note: default 4, max 4 */ + uint16_t beacon_interval; /* Note: support 100 ~ 60000 ms, default 100 */ }; bool wifi_softap_get_config(struct softap_config *config); @@ -354,7 +356,7 @@ bool wifi_softap_set_config_current(struct softap_config *config); struct station_info { STAILQ_ENTRY(station_info) next; - uint8 bssid[6]; + uint8_t bssid[6]; struct ip_addr ip; }; @@ -370,7 +372,7 @@ enum dhcps_offer_option{ OFFER_END }; -uint8 wifi_softap_get_station_num(void); +uint8_t wifi_softap_get_station_num(void); struct station_info * wifi_softap_get_station_info(void); void wifi_softap_free_station_info(void); @@ -379,34 +381,34 @@ bool wifi_softap_dhcps_stop(void); bool wifi_softap_set_dhcps_lease(struct dhcps_lease *please); bool wifi_softap_get_dhcps_lease(struct dhcps_lease *please); -uint32 wifi_softap_get_dhcps_lease_time(void); -bool wifi_softap_set_dhcps_lease_time(uint32 minute); +uint32_t wifi_softap_get_dhcps_lease_time(void); +bool wifi_softap_set_dhcps_lease_time(uint32_t minute); bool wifi_softap_reset_dhcps_lease_time(void); enum dhcp_status wifi_softap_dhcps_status(void); -bool wifi_softap_set_dhcps_offer_option(uint8 level, void* optarg); +bool wifi_softap_set_dhcps_offer_option(uint8_t level, void* optarg); #define STATION_IF 0x00 #define SOFTAP_IF 0x01 -bool wifi_get_ip_info(uint8 if_index, struct ip_info *info); -bool wifi_set_ip_info(uint8 if_index, struct ip_info *info); -bool wifi_get_macaddr(uint8 if_index, uint8 *macaddr); -bool wifi_set_macaddr(uint8 if_index, uint8 *macaddr); +bool wifi_get_ip_info(uint8_t if_index, struct ip_info *info); +bool wifi_set_ip_info(uint8_t if_index, struct ip_info *info); +bool wifi_get_macaddr(uint8_t if_index, uint8_t *macaddr); +bool wifi_set_macaddr(uint8_t if_index, uint8_t *macaddr); -uint8 wifi_get_channel(void); -bool wifi_set_channel(uint8 channel); +uint8_t wifi_get_channel(void); +bool wifi_set_channel(uint8_t channel); -void wifi_status_led_install(uint8 gpio_id, uint32 gpio_name, uint8 gpio_func); -void wifi_status_led_uninstall(); +void wifi_status_led_install(uint8_t gpio_id, uint32_t gpio_name, uint8_t gpio_func); +void wifi_status_led_uninstall(void); /** Get the absolute difference between 2 u32_t values (correcting overflows) * 'a' is expected to be 'higher' (without overflow) than 'b'. */ #define ESP_U32_DIFF(a, b) (((a) >= (b)) ? ((a) - (b)) : (((a) + ((b) ^ 0xFFFFFFFF) + 1))) -void wifi_promiscuous_enable(uint8 promiscuous); +void wifi_promiscuous_enable(uint8_t promiscuous); -typedef void (* wifi_promiscuous_cb_t)(uint8 *buf, uint16 len); +typedef void (* wifi_promiscuous_cb_t)(uint8_t *buf, uint16_t len); void wifi_set_promiscuous_rx_cb(wifi_promiscuous_cb_t cb); @@ -436,20 +438,20 @@ bool wifi_set_sleep_type(enum sleep_type type); enum sleep_type wifi_get_sleep_type(void); bool wifi_set_sleep_level(enum sleep_level level); enum sleep_level wifi_get_sleep_level(void); -bool wifi_set_listen_interval(uint8 interval); -uint8 wifi_get_listen_interval(void); +bool wifi_set_listen_interval(uint8_t interval); +uint8_t wifi_get_listen_interval(void); void wifi_fpm_open(void); void wifi_fpm_close(void); void wifi_fpm_do_wakeup(void); -sint8 wifi_fpm_do_sleep(uint32 sleep_time_in_us); +int8_t wifi_fpm_do_sleep(uint32_t sleep_time_in_us); void wifi_fpm_set_sleep_type(enum sleep_type type); enum sleep_type wifi_fpm_get_sleep_type(void); typedef void (*fpm_wakeup_cb)(void); void wifi_fpm_set_wakeup_cb(fpm_wakeup_cb cb); -void wifi_fpm_auto_sleep_set_in_null_mode(uint8 req); +void wifi_fpm_auto_sleep_set_in_null_mode(uint8_t req); enum { EVENT_STAMODE_CONNECTED = 0, @@ -498,22 +500,22 @@ enum { }; typedef struct { - uint8 ssid[32]; - uint8 ssid_len; - uint8 bssid[6]; - uint8 channel; + uint8_t ssid[32]; + uint8_t ssid_len; + uint8_t bssid[6]; + uint8_t channel; } Event_StaMode_Connected_t; typedef struct { - uint8 ssid[32]; - uint8 ssid_len; - uint8 bssid[6]; - uint8 reason; + uint8_t ssid[32]; + uint8_t ssid_len; + uint8_t bssid[6]; + uint8_t reason; } Event_StaMode_Disconnected_t; typedef struct { - uint8 old_mode; - uint8 new_mode; + uint8_t old_mode; + uint8_t new_mode; } Event_StaMode_AuthMode_Change_t; typedef struct { @@ -523,29 +525,29 @@ typedef struct { } Event_StaMode_Got_IP_t; typedef struct { - uint8 mac[6]; - uint8 aid; + uint8_t mac[6]; + uint8_t aid; } Event_SoftAPMode_StaConnected_t; typedef struct { - uint8 mac[6]; + uint8_t mac[6]; struct ip_addr ip; - uint8 aid; + uint8_t aid; } Event_SoftAPMode_Distribute_Sta_IP_t; typedef struct { - uint8 mac[6]; - uint8 aid; + uint8_t mac[6]; + uint8_t aid; } Event_SoftAPMode_StaDisconnected_t; typedef struct { int rssi; - uint8 mac[6]; + uint8_t mac[6]; } Event_SoftAPMode_ProbeReqRecved_t; typedef struct { - uint8 old_opmode; - uint8 new_opmode; + uint8_t old_opmode; + uint8_t new_opmode; } Event_OpMode_Change_t; typedef union { @@ -561,7 +563,7 @@ typedef union { } Event_Info_u; typedef struct _esp_event { - uint32 event; + uint32_t event; Event_Info_u event_info; } System_Event_t; @@ -591,15 +593,15 @@ bool wifi_wps_start(void); typedef void (*wps_st_cb_t)(int status); bool wifi_set_wps_cb(wps_st_cb_t cb); -typedef void (*freedom_outside_cb_t)(uint8 status); +typedef void (*freedom_outside_cb_t)(uint8_t status); int wifi_register_send_pkt_freedom_cb(freedom_outside_cb_t cb); void wifi_unregister_send_pkt_freedom_cb(void); -int wifi_send_pkt_freedom(uint8 *buf, int len, bool sys_seq); +int wifi_send_pkt_freedom(uint8_t *buf, int len, bool sys_seq); int wifi_rfid_locp_recv_open(void); void wifi_rfid_locp_recv_close(void); -typedef void (*rfid_locp_cb_t)(uint8 *frm, int len, int rssi); +typedef void (*rfid_locp_cb_t)(uint8_t *frm, int len, int rssi); int wifi_register_rfid_locp_recv_cb(rfid_locp_cb_t cb); void wifi_unregister_rfid_locp_recv_cb(void); @@ -619,8 +621,8 @@ enum FIXED_RATE { #define FIXED_RATE_MASK_AP 0x02 #define FIXED_RATE_MASK_ALL 0x03 -int wifi_set_user_fixed_rate(uint8 enable_mask, uint8 rate); -int wifi_get_user_fixed_rate(uint8 *enable_mask, uint8 *rate); +int wifi_set_user_fixed_rate(uint8_t enable_mask, uint8_t rate); +int wifi_get_user_fixed_rate(uint8_t *enable_mask, uint8_t *rate); enum support_rate { RATE_11B5M = 0, @@ -637,7 +639,7 @@ enum support_rate { RATE_11G36M = 11, }; -int wifi_set_user_sup_rate(uint8 min, uint8 max); +int wifi_set_user_sup_rate(uint8_t min, uint8_t max); enum RATE_11B_ID { RATE_11B_B11M = 0, @@ -687,9 +689,9 @@ enum RATE_11N_ID { #define LIMIT_RATE_MASK_AP 0x02 #define LIMIT_RATE_MASK_ALL 0x03 -bool wifi_set_user_rate_limit(uint8 mode, uint8 ifidx, uint8 max, uint8 min); -uint8 wifi_get_user_limit_rate_mask(void); -bool wifi_set_user_limit_rate_mask(uint8 enable_mask); +bool wifi_set_user_rate_limit(uint8_t mode, uint8_t ifidx, uint8_t max, uint8_t min); +uint8_t wifi_get_user_limit_rate_mask(void); +bool wifi_set_user_limit_rate_mask(uint8_t enable_mask); enum { USER_IE_BEACON = 0, @@ -700,16 +702,16 @@ enum { USER_IE_MAX }; -typedef void (*user_ie_manufacturer_recv_cb_t)(uint8 type, const uint8 sa[6], const uint8 m_oui[3], uint8 *ie, uint8 ie_len, int rssi); +typedef void (*user_ie_manufacturer_recv_cb_t)(uint8_t type, const uint8_t sa[6], const uint8_t m_oui[3], uint8_t *ie, uint8_t ie_len, int rssi); -bool wifi_set_user_ie(bool enable, uint8 *m_oui, uint8 type, uint8 *user_ie, uint8 len); +bool wifi_set_user_ie(bool enable, uint8_t *m_oui, uint8_t type, uint8_t *user_ie, uint8_t len); int wifi_register_user_ie_manufacturer_recv_cb(user_ie_manufacturer_recv_cb_t cb); void wifi_unregister_user_ie_manufacturer_recv_cb(void); -void wifi_enable_gpio_wakeup(uint32 i, GPIO_INT_TYPE intr_status); +void wifi_enable_gpio_wakeup(uint32_t i, GPIO_INT_TYPE intr_status); void wifi_disable_gpio_wakeup(void); -void uart_div_modify(uint8 uart_no, uint32 DivLatchValue); +void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue); typedef enum { WIFI_COUNTRY_POLICY_AUTO, /**< Country policy is auto, use the country info of AP to which the station is connected */ diff --git a/include/wpa2_enterprise.h b/include/wpa2_enterprise.h index 9bd0ba51..8c600d5f 100644 --- a/include/wpa2_enterprise.h +++ b/include/wpa2_enterprise.h @@ -36,24 +36,24 @@ typedef int (* get_time_func_t)(struct os_time *t); int wifi_station_set_wpa2_enterprise_auth(int enable); -int wifi_station_set_enterprise_cert_key(u8 *client_cert, int client_cert_len, - u8 *private_key, int private_key_len, - u8 *private_key_passwd, int private_key_passwd_len); +int wifi_station_set_enterprise_cert_key(uint8_t *client_cert, int client_cert_len, + uint8_t *private_key, int private_key_len, + uint8_t *private_key_passwd, int private_key_passwd_len); void wifi_station_clear_enterprise_cert_key(void); -int wifi_station_set_enterprise_ca_cert(u8 *ca_cert, int ca_cert_len); +int wifi_station_set_enterprise_ca_cert(uint8_t *ca_cert, int ca_cert_len); void wifi_station_clear_enterprise_ca_cert(void); -int wifi_station_set_enterprise_identity(u8 *identity, int len); +int wifi_station_set_enterprise_identity(uint8_t *identity, int len); void wifi_station_clear_enterprise_identity(void); -int wifi_station_set_enterprise_username(u8 *username, int len); +int wifi_station_set_enterprise_username(uint8_t *username, int len); void wifi_station_clear_enterprise_username(void); -int wifi_station_set_enterprise_password(u8 *password, int len); +int wifi_station_set_enterprise_password(uint8_t *password, int len); void wifi_station_clear_enterprise_password(void); -int wifi_station_set_enterprise_new_password(u8 *new_password, int len); +int wifi_station_set_enterprise_new_password(uint8_t *new_password, int len); void wifi_station_clear_enterprise_new_password(void); void wifi_station_set_enterprise_disable_time_check(bool disable);