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esp32c6: esp_app_desc_t
not located at the beginning of the app fw image (causes OTA upgrade failures; refusal to boot with newer bootloaders)
#365
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I believe my panic maybe well be related, it seems that since the If remove the If I rebuild my app for esp32s3, then I get the correct EDIT: I should point out that for the esp32c6, if I comment out the part where I grab the |
You are simply using a newer To cut the long story short, these warnings are harmless (albeit annoying). Until we fix these by properly declaring our
This has nothing to do with the warnings from above, and if indeed that happens, it must be chip specific, as I'm pretty sure on the s3 and on the stock esp32 it works just fine. I would hypothesize is that the reason for the error is that this link section has an incorrect name for the c6 (and maybe other riscvs?) and there, it must be something else. Essentially, it must match whatever link section is used in the ESP-IDF code for the same definition (the one in ESP-IDF is with a "weak" linkage attr definition, so we override it essentially). The weird thing is, in ESP-IDF I see the same link section name regardless of the chip type, so really, are you sure it breaks for you (a) only with the c6 (b) only when you use the macro? |
What I would also suggest is - as a test - to try using An easy way to install and use |
Thank you for the explanation of the warnings for I used
The above is
FWIW, a quick attempt to
|
@smithwinston Sorry for the delay. Will try to look at both issues ( |
@smithwinston Still not at the root cause of the problem, but what I have confirmed so far, is that the The reason for this is that the order of the segments' file in the resulting
I'll keep digging as to exactly why that happens, and whether this is something specific to the ESP-IDF Rust tooling, or happens with the C ESP-IDF tooling as well (though the latter would be very strange, as that would indicate nobody is using the c6 in production yet, which I can't believe). |
More info. Looking at the ELF files of an esp32s3 build, and then esp32c6 build, the ELF sections have a weird ordering, if we "order" them by looking at their addresses: S3: ivan@m800:~/dev/esp-idf-matter$ llvm-readelf-14 --sections target/xtensa-esp32s3-espidf/debug/examples/light
There are 40 section headers, starting at offset 0x27eb2f8:
Section Headers:
[Nr] Name Type Address Off Size ES Flg Lk Inf Al
[ 0] NULL 00000000 000000 000000 00 0 0 0
[ 1] .rtc.text NOBITS 600fe000 262000 000100 00 WA 0 0 1
[ 2] .rtc.force_fast PROGBITS 600fe100 261a7a 000000 00 W 0 0 1
[ 3] .rtc_noinit PROGBITS 50000000 261a7a 000000 00 W 0 0 1
[ 4] .rtc.force_slow PROGBITS 50000000 261a7a 000000 00 W 0 0 1
[ 5] .rtc_reserved NOBITS 600fffe8 261fe8 000018 00 WA 0 0 8
[ 6] .iram0.vectors PROGBITS 40374000 094000 000403 00 AX 0 0 4
[ 7] .iram0.text PROGBITS 40374404 094404 017edf 00 AX 0 0 4
[ 8] .dram0.dummy NOBITS 3fc88000 07a000 014300 00 WA 0 0 1
[ 9] .dram0.data PROGBITS 3fc9c300 08e300 005b7c 00 WA 0 0 16
[10] .noinit NOBITS 3fca1e7c 000000 000000 00 WA 0 0 1
[11] .dram0.bss NOBITS 3fca1e80 093e7c 00f428 00 WA 0 0 8
[12] .flash.text PROGBITS 42000020 0ad020 1b4a5a 00 AX 0 0 4
[13] .flash_rodata_dummy NOBITS 3c000020 001020 1c0000 00 WA 0 0 1
[14] .flash.appdesc PROGBITS 3c1c0020 001020 000100 00 A 0 0 16
[15] .flash.rodata PROGBITS 3c1c0120 001120 077fec 00 WA 0 0 16
[16] .flash.rodata_noload NOBITS 3c23810c 07910c 002e4f 00 A 0 0 1
[17] .ext_ram.dummy NOBITS 3c000020 001020 23ffe0 00 WA 0 0 1
[18] .iram0.text_end NOBITS 4038c2e3 0ac2e3 00001d 00 WA 0 0 1
[19] .iram0.data PROGBITS 4038c300 261a7a 000000 00 W 0 0 1
[20] .iram0.bss PROGBITS 4038c300 261a7a 000000 00 W 0 0 1
[21] .dram0.heap_start PROGBITS 3fcb12a8 261a7a 000000 00 W 0 0 1
[22] .debug_aranges PROGBITS 00000000 261a80 033f40 00 0 0 8
[23] .debug_info PROGBITS 00000000 2959c0 df8f4c 00 0 0 1
[24] .debug_abbrev PROGBITS 00000000 108e90c 0c54cc 00 0 0 1
[25] .debug_line PROGBITS 00000000 1153dd8 4cfa01 00 0 0 1
[26] .debug_frame PROGBITS 00000000 16237dc 02d098 00 0 0 4
[27] .debug_str PROGBITS 00000000 1650874 a9a0ee 01 MS 0 0 1
[28] .debug_loc PROGBITS 00000000 20ea962 4475cf 00 0 0 1
[29] .debug_ranges PROGBITS 00000000 2531f38 10c1e8 00 0 0 8
[30] .debug_line_str PROGBITS 00000000 263e120 002902 01 MS 0 0 1
[31] .debug_loclists PROGBITS 00000000 2640a22 0141fd 00 0 0 1
[32] .debug_rnglists PROGBITS 00000000 2654c1f 00085d 00 0 0 1
[33] .comment PROGBITS 00000000 265547c 0000ce 01 MS 0 0 1
[34] .xtensa.info NOTE 00000000 265554a 000038 00 0 0 1
[35] .xt.prop PROGBITS 00000000 2655582 000510 00 0 0 1
[36] .xt.lit PROGBITS 00000000 2655a92 000008 00 0 0 1
[37] .symtab SYMTAB 00000000 2655a9c 057ce0 10 38 5611 4
[38] .strtab STRTAB 00000000 26ad77c 13d97e 00 0 0 1
[39] .shstrtab STRTAB 00000000 27eb0fa 0001fd 00 0 0 1
Key to Flags:
W (write), A (alloc), X (execute), M (merge), S (strings), I (info),
L (link order), O (extra OS processing required), G (group), T (TLS),
C (compressed), x (unknown), o (OS specific), E (exclude),
R (retain), p (processor specific) Notice how the Also an s3 image converted to Segments information
====================
Segment Length Load addr File offs Memory types
------- ------- ---------- ---------- ------------
0 0x780ec 0x3c1c0020 0x00000018 DROM
1 0x05b7c 0x3fc9c300 0x0007810c BYTE_ACCESSIBLE, MEM_INTERNAL, DRAM
2 0x02380 0x40374000 0x0007dc90 MEM_INTERNAL, IRAM
3 0x1b4a5c 0x42000020 0x00080018 IROM
4 0x15f64 0x40376380 0x00234a7c MEM_INTERNAL, IRAM Notice how all flash non-executable sections from the ELF are merged in a single "DROM" segment which starts first (what we want). In contrast, the ELF dump of an esp32c6 image gives: ivan@m800:~/dev/esp-idf-matter$ llvm-readelf-14 --sections target/riscv32imac-esp-espidf/debug/examples/light
There are 38 section headers, starting at offset 0x33b4660:
Section Headers:
[Nr] Name Type Address Off Size ES Flg Lk Inf Al
[ 0] NULL 00000000 000000 000000 00 0 0 0
[ 1] .rtc.text PROGBITS 50000000 46bc24 000000 00 W 0 0 1
[ 2] .rtc.force_fast PROGBITS 50000000 46bc24 000000 00 W 0 0 1
[ 3] .rtc_noinit PROGBITS 50000000 46bc24 000000 00 W 0 0 1
[ 4] .rtc.force_slow PROGBITS 50000000 46bc24 000000 00 W 0 0 1
[ 5] .rtc_reserved NOBITS 50003fe8 46bfe8 000018 00 WA 0 0 8
[ 6] .iram0.text PROGBITS 40800000 001000 01ccee 00 AX 0 0 256
[ 7] .iram0.text_end NOBITS 4081ccee 01dcee 000002 00 WA 0 0 1
[ 8] .iram0.data NOBITS 4081ccf0 01dcee 000000 00 WA 0 0 1
[ 9] .iram0.bss PROGBITS 4081ccf0 46bc24 000000 00 W 0 0 1
[10] .dram0.data PROGBITS 4081ccf0 01dcf0 004735 00 WA 0 0 16
[11] .noinit NOBITS 40821425 022425 000003 00 WA 0 0 1
[12] .dram0.bss NOBITS 40821430 022425 010ba0 00 WA 0 0 16
[13] .flash.text PROGBITS 42000020 023020 1e5b00 00 AX 0 0 2
[14] .flash_rodata_dummy NOBITS 42000020 209020 1e8000 00 WA 0 0 1
[15] .flash.appdesc PROGBITS 421e8020 3f1020 000100 00 A 0 0 16
[16] .flash.rodata PROGBITS 421e8120 3f1120 07ab04 00 WA 0 0 16
[17] .eh_frame_hdr PROGBITS 42262c24 46bc24 000000 00 W 0 0 1
[18] .eh_frame PROGBITS 42262c24 46bc24 000000 00 W 0 0 1
[19] .flash.tdata PROGBITS 42262c24 46bc24 000000 00 W 0 0 1
[20] .flash.rodata_noload NOBITS 42262c24 46bc24 003207 00 A 0 0 4
[21] .dram0.heap_start PROGBITS 40831fd0 46bc24 000000 00 W 0 0 1
[22] .debug_aranges PROGBITS 00000000 46bc28 038830 00 0 0 8
[23] .debug_info PROGBITS 00000000 4a4458 da4f93 00 0 0 1
[24] .debug_abbrev PROGBITS 00000000 12493eb 0bf173 00 0 0 1
[25] .debug_line PROGBITS 00000000 130855e 4eb2e8 00 0 0 1
[26] .debug_frame PROGBITS 00000000 17f3848 0a3778 00 0 0 4
[27] .debug_str PROGBITS 00000000 1896fc0 a8c027 01 MS 0 0 1
[28] .debug_loc PROGBITS 00000000 2322fe7 4e3c9e 00 0 0 1
[29] .debug_ranges PROGBITS 00000000 2806c85 0f3878 00 0 0 1
[30] .debug_line_str PROGBITS 00000000 28fa4fd 001ce2 01 MS 0 0 1
[31] .debug_loclists PROGBITS 00000000 28fc1df 003235 00 0 0 1
[32] .debug_rnglists PROGBITS 00000000 28ff414 00049a 00 0 0 1
[33] .comment PROGBITS 00000000 28ff8ae 0000cc 01 MS 0 0 1
[34] .riscv.attributes RISCV_ATTRIBUTES 00000000 28ff97a 000057 00 0 0 1
[35] .symtab SYMTAB 00000000 28ff9d4 96c450 10 36 600417 4
[36] .strtab STRTAB 00000000 326be24 14864f 00 0 0 1
[37] .shstrtab STRTAB 00000000 33b4473 0001eb 00 0 0 1
Key to Flags:
W (write), A (alloc), X (execute), M (merge), S (strings), I (info),
L (link order), O (extra OS processing required), G (group), T (TLS),
C (compressed), x (unknown), o (OS specific), E (exclude),
R (retain), p (processor specific) Notice how the ... and the Segments information
====================
Segment Length Load addr File offs Memory types
------- ------- ---------- ---------- ------------
0 0x17ff8 0x40800000 0x00000018 DRAM, BYTE_ACCESSIBLE, IRAM
1 0x7ac04 0x421e8020 0x00018018 IROM <-- THIS SHOULD BE FIRST
2 0x04cf8 0x40817ff8 0x00092c24 DRAM, BYTE_ACCESSIBLE, IRAM
3 0x04738 0x4081ccf0 0x00097924 DRAM, BYTE_ACCESSIBLE, IRAM
4 0x03fac 0x00000000 0x0009c064 PADDING
5 0x1e5b00 0x42000020 0x000a0018 IROM First of all, the 0x421e8020 should be the first segment, not the second, and then - why is it marked as "IROM"?! It is DROM actually? |
@ivmarkov Intereresting stuff, thank you for looking into it. Yes I'd be surprised if no-one is using the C6 (although I'm leaning to the S3 simply due to the large flash size on the modules I have as I need dual images for OTA updates). |
I can't believe it either, but so far this seems actually the most likely outcome.
FYI there are c6 modules with 8 or even 16 MB flash too. Mine are with 8MB. The big difference IMO is in |
I'm closing this because the bug is actually in
For |
cfg
condition name: esp_idf_app_compile_time_date
etc.esp_app_desc_t
not located at the beginning of the app fw image (causes OTA upgrade failures; refusal to boot with newer bootloaders)
Bug description
I had an existing project that had
esp_app_desc!()
in it'smain.rs
. After updating the esp-idf-* crates, I find I get a series of warnings for a number of cfg conditions related to esp_app_desc!:... and so on.
This is somewhat beyond my burgeoning Rust skills!
To Reproduce
cargo generate esp-rs/esp-idf-template cargo
1.1. Enter a test project name
1.2. Chose
esp32c6
as the MCU1.3. Chose
Configure advanced template options
1.4. Picked
v5.3
1.5. Picked
false
for the restcargo add esp-idf-sys
main.rs
add:esp_idf_sys::esp_app_desc!();
Then try to build with
cargo build
.I'm actually working on OTA updates and I'm seeing a runtime panic (a UTF8 error it seems) inside esp-idf-svc's
ota.rs:196
where it's trying to get the version string:I'm not entirely sure if this related, but it surely seems coincidental.
Expected behavior
No warnings. This compiled ok in prior versions.
Environment
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