$size evaluates to the wrong value
#1094
Comments
|
@Rodrigodd, please checkout Surelog, apply your patch in the UHDM submodule, Check the diffs, you can run: Let me know the results. |
|
I tried running I run I then run ResultsI then try git diffdiff --git a/tests/DashYTest/DashYTest.log b/tests/DashYTest/DashYTest.log
index 8fbb10c4..26e09b5b 100644
--- a/tests/DashYTest/DashYTest.log
+++ b/tests/DashYTest/DashYTest.log
@@ -43,22 +43,6 @@ n<> u<11> t<Top_level_rule> c<1> l<1:1> el<3:1>
AST_DEBUG_END
AST_DEBUG_BEGIN
LIB: work
-FILE: ${SURELOG_DIR}/tests/DashYTest/lib/OR.v
-n<> u<0> t<_INVALID_> f<0> l<0:0>
-n<> u<1> t<Null_rule> p<11> s<10> l<1:1> el<1:0>
-n<module> u<2> t<Module_keyword> p<6> s<3> l<1:1> el<1:7>
-n<OR> u<3> t<StringConst> p<6> s<5> l<1:8> el<1:10>
-n<> u<4> t<Port> p<5> l<1:11> el<1:11>
-n<> u<5> t<List_of_ports> p<6> c<4> l<1:10> el<1:12>
-n<> u<6> t<Module_nonansi_header> p<8> c<2> s<7> l<1:1> el<1:13>
-n<> u<7> t<ENDMODULE> p<8> l<2:1> el<2:10>
-n<> u<8> t<Module_declaration> p<9> c<6> l<1:1> el<2:10>
-n<> u<9> t<Description> p<10> c<8> l<1:1> el<2:10>
-n<> u<10> t<Source_text> p<11> c<9> l<1:1> el<2:10>
-n<> u<11> t<Top_level_rule> c<1> l<1:1> el<3:1>
-AST_DEBUG_END
-AST_DEBUG_BEGIN
-LIB: work
FILE: ${SURELOG_DIR}/tests/DashYTest/lib/SIM.v
n<> u<0> t<_INVALID_> f<0> l<0:0>
n<> u<1> t<Null_rule> p<29> s<28> l<1:1> el<1:0>
@@ -91,6 +75,22 @@ n<> u<27> t<Description> p<28> c<26> l<1:1> el<6:10>
n<> u<28> t<Source_text> p<29> c<27> l<1:1> el<6:10>
n<> u<29> t<Top_level_rule> c<1> l<1:1> el<7:1>
AST_DEBUG_END
+AST_DEBUG_BEGIN
+LIB: work
+FILE: ${SURELOG_DIR}/tests/DashYTest/lib/OR.v
+n<> u<0> t<_INVALID_> f<0> l<0:0>
+n<> u<1> t<Null_rule> p<11> s<10> l<1:1> el<1:0>
+n<module> u<2> t<Module_keyword> p<6> s<3> l<1:1> el<1:7>
+n<OR> u<3> t<StringConst> p<6> s<5> l<1:8> el<1:10>
+n<> u<4> t<Port> p<5> l<1:11> el<1:11>
+n<> u<5> t<List_of_ports> p<6> c<4> l<1:10> el<1:12>
+n<> u<6> t<Module_nonansi_header> p<8> c<2> s<7> l<1:1> el<1:13>
+n<> u<7> t<ENDMODULE> p<8> l<2:1> el<2:10>
+n<> u<8> t<Module_declaration> p<9> c<6> l<1:1> el<2:10>
+n<> u<9> t<Description> p<10> c<8> l<1:1> el<2:10>
+n<> u<10> t<Source_text> p<11> c<9> l<1:1> el<2:10>
+n<> u<11> t<Top_level_rule> c<1> l<1:1> el<3:1>
+AST_DEBUG_END
[INF:CP0300] Compilation...
[INF:CP0303] ${SURELOG_DIR}/tests/DashYTest/lib/AND.v:1:1: Compile module "work@AND".
[INF:CP0303] ${SURELOG_DIR}/tests/DashYTest/lib/OR.v:1:1: Compile module "work@OR".
diff --git a/tests/LibraryIntercon/LibraryIntercon.log b/tests/LibraryIntercon/LibraryIntercon.log
index 696ff212..beb44dd8 100644
--- a/tests/LibraryIntercon/LibraryIntercon.log
+++ b/tests/LibraryIntercon/LibraryIntercon.log
@@ -11,8 +11,8 @@ LIB: realLib
LIB: logicLib
${SURELOG_DIR}/tests/LibraryIntercon/driver.sv
- ${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv
${SURELOG_DIR}/tests/LibraryIntercon/top.sv
+ ${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/nets.pkg".
@@ -20,17 +20,17 @@ LIB: logicLib
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.svr".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.svr".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/top.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/nets.pkg".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.svr".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.svr".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/driver.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/top.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv".
[WRN:PA0205] ${SURELOG_DIR}/tests/LibraryIntercon/nets.pkg:1:1: No timescale set for "NetsPkg".
-[WRN:PA0205] ${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv:2:1: No timescale set for "cmp".
[WRN:PA0205] ${SURELOG_DIR}/tests/LibraryIntercon/top.sv:1:1: No timescale set for "top".
+[WRN:PA0205] ${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv:2:1: No timescale set for "cmp".
[INF:CP0300] Compilation...
[INF:CP0301] ${SURELOG_DIR}/tests/LibraryIntercon/nets.pkg:1:1: Compile package "NetsPkg".
[INF:CP0303] ${SURELOG_DIR}/tests/LibraryIntercon/cmp.sv:2:1: Compile module "logicLib@cmp".
diff --git a/tests/NonSynthUnusedMod/NonSynthUnusedMod.log b/tests/NonSynthUnusedMod/NonSynthUnusedMod.log
index 39a27646..bae83811 100644
--- a/tests/NonSynthUnusedMod/NonSynthUnusedMod.log
+++ b/tests/NonSynthUnusedMod/NonSynthUnusedMod.log
@@ -27,22 +27,6 @@ n<> u<21> t<Top_level_rule> c<1> l<1:1> el<8:1>
AST_DEBUG_END
AST_DEBUG_BEGIN
LIB: work
-FILE: ${SURELOG_DIR}/tests/NonSynthUnusedMod/top.v
-n<> u<0> t<_INVALID_> f<0> l<0:0>
-n<> u<1> t<Null_rule> p<11> s<10> l<1:1> el<1:0>
-n<module> u<2> t<Module_keyword> p<6> s<3> l<1:1> el<1:7>
-n<top> u<3> t<StringConst> p<6> s<5> l<1:8> el<1:11>
-n<> u<4> t<Port> p<5> l<1:12> el<1:12>
-n<> u<5> t<List_of_ports> p<6> c<4> l<1:11> el<1:13>
-n<> u<6> t<Module_nonansi_header> p<8> c<2> s<7> l<1:1> el<1:14>
-n<> u<7> t<ENDMODULE> p<8> l<3:1> el<3:10>
-n<> u<8> t<Module_declaration> p<9> c<6> l<1:1> el<3:10>
-n<> u<9> t<Description> p<10> c<8> l<1:1> el<3:10>
-n<> u<10> t<Source_text> p<11> c<9> l<1:1> el<3:10>
-n<> u<11> t<Top_level_rule> c<1> l<1:1> el<4:1>
-AST_DEBUG_END
-AST_DEBUG_BEGIN
-LIB: work
FILE: ${SURELOG_DIR}/tests/NonSynthUnusedMod/nonsynth.v
n<> u<0> t<_INVALID_> f<0> l<0:0>
n<> u<1> t<Null_rule> p<38> s<37> l<1:1> el<1:0>
@@ -84,6 +68,22 @@ n<> u<36> t<Description> p<37> c<35> l<1:1> el<7:10>
n<> u<37> t<Source_text> p<38> c<36> l<1:1> el<7:10>
n<> u<38> t<Top_level_rule> c<1> l<1:1> el<8:1>
AST_DEBUG_END
+AST_DEBUG_BEGIN
+LIB: work
+FILE: ${SURELOG_DIR}/tests/NonSynthUnusedMod/top.v
+n<> u<0> t<_INVALID_> f<0> l<0:0>
+n<> u<1> t<Null_rule> p<11> s<10> l<1:1> el<1:0>
+n<module> u<2> t<Module_keyword> p<6> s<3> l<1:1> el<1:7>
+n<top> u<3> t<StringConst> p<6> s<5> l<1:8> el<1:11>
+n<> u<4> t<Port> p<5> l<1:12> el<1:12>
+n<> u<5> t<List_of_ports> p<6> c<4> l<1:11> el<1:13>
+n<> u<6> t<Module_nonansi_header> p<8> c<2> s<7> l<1:1> el<1:14>
+n<> u<7> t<ENDMODULE> p<8> l<3:1> el<3:10>
+n<> u<8> t<Module_declaration> p<9> c<6> l<1:1> el<3:10>
+n<> u<9> t<Description> p<10> c<8> l<1:1> el<3:10>
+n<> u<10> t<Source_text> p<11> c<9> l<1:1> el<3:10>
+n<> u<11> t<Top_level_rule> c<1> l<1:1> el<4:1>
+AST_DEBUG_END
[INF:CP0300] Compilation...
[INF:CP0303] ${SURELOG_DIR}/tests/NonSynthUnusedMod/dut.sv:1:1: Compile module "work@dut".
[INF:CP0303] ${SURELOG_DIR}/tests/NonSynthUnusedMod/nonsynth.v:1:1: Compile module "work@nonsynth".
diff --git a/tests/OldLibrary/OldLibrary.log b/tests/OldLibrary/OldLibrary.log
index 90fc14dc..85fb4c7e 100644
--- a/tests/OldLibrary/OldLibrary.log
+++ b/tests/OldLibrary/OldLibrary.log
@@ -1,16 +1,16 @@
[INF:CM0023] Creating log file "${SURELOG_DIR}/build/regression/OldLibrary/slpp_all/surelog.log".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/OldLibrary/top.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL2.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL1.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL3.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL1.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL2.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/OldLibrary/top.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL2.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL1.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL3.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL1.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/OldLibrary/lib/CELL2.v".
[WRN:PA0205] ${SURELOG_DIR}/tests/OldLibrary/top.v:1:1: No timescale set for "top".
-[WRN:PA0205] ${SURELOG_DIR}/tests/OldLibrary/lib/CELL2.v:1:1: No timescale set for "CELL2".
-[WRN:PA0205] ${SURELOG_DIR}/tests/OldLibrary/lib/CELL1.v:1:1: No timescale set for "CELL1".
[WRN:PA0205] ${SURELOG_DIR}/tests/OldLibrary/lib/CELL3.v:1:1: No timescale set for "CELL3".
+[WRN:PA0205] ${SURELOG_DIR}/tests/OldLibrary/lib/CELL1.v:1:1: No timescale set for "CELL1".
+[WRN:PA0205] ${SURELOG_DIR}/tests/OldLibrary/lib/CELL2.v:1:1: No timescale set for "CELL2".
[INF:CP0300] Compilation...
[INF:CP0303] ${SURELOG_DIR}/tests/OldLibrary/lib/CELL1.v:1:1: Compile module "work@CELL1".
[INF:CP0305] ${SURELOG_DIR}/tests/OldLibrary/lib/CELL2.v:1:1: Compile udp "work@CELL2".
diff --git a/tests/PreprocLine/PreprocLine.log b/tests/PreprocLine/PreprocLine.log
index 860f4d72..3741bf9d 100644
--- a/tests/PreprocLine/PreprocLine.log
+++ b/tests/PreprocLine/PreprocLine.log
@@ -13,38 +13,38 @@ n<top> u<3> t<StringConst> p<4> l<1:8> el<1:11>
n<> u<4> t<Module_ansi_header> p<66> c<2> s<64> l<1:1> el<1:12>
n<> u<5> t<Dollar_keyword> p<17> s<6> l<3:9> el<3:10>
n<display> u<6> t<StringConst> p<17> s<16> l<3:10> el<3:17>
-n<"${SURELOG_DIR}/tests/PreprocLine/dut.sv"> u<7> t<StringLiteral> p<8> l<3:18> el<3:64>
-n<> u<8> t<Primary_literal> p<9> c<7> l<3:18> el<3:64>
-n<> u<9> t<Primary> p<10> c<8> l<3:18> el<3:64>
-n<> u<10> t<Expression> p<16> c<9> s<15> l<3:18> el<3:64>
-n<3> u<11> t<IntConst> p<12> l<3:66> el<3:67>
-n<> u<12> t<Primary_literal> p<13> c<11> l<3:66> el<3:67>
-n<> u<13> t<Primary> p<14> c<12> l<3:66> el<3:67>
-n<> u<14> t<Expression> p<15> c<13> l<3:66> el<3:67>
-n<> u<15> t<Argument> p<16> c<14> l<3:66> el<3:67>
-n<> u<16> t<List_of_arguments> p<17> c<10> l<3:18> el<3:67>
-n<> u<17> t<Subroutine_call> p<18> c<5> l<3:9> el<3:68>
-n<> u<18> t<Subroutine_call_statement> p<19> c<17> l<3:9> el<3:69>
-n<> u<19> t<Statement_item> p<20> c<18> l<3:9> el<3:69>
-n<> u<20> t<Statement> p<21> c<19> l<3:9> el<3:69>
-n<> u<21> t<Statement_or_null> p<57> c<20> s<38> l<3:9> el<3:69>
+n<"${SURELOG_DIR}/tests/PreprocLine/dut.sv"> u<7> t<StringLiteral> p<8> l<3:18> el<3:74>
+n<> u<8> t<Primary_literal> p<9> c<7> l<3:18> el<3:74>
+n<> u<9> t<Primary> p<10> c<8> l<3:18> el<3:74>
+n<> u<10> t<Expression> p<16> c<9> s<15> l<3:18> el<3:74>
+n<3> u<11> t<IntConst> p<12> l<3:76> el<3:77>
+n<> u<12> t<Primary_literal> p<13> c<11> l<3:76> el<3:77>
+n<> u<13> t<Primary> p<14> c<12> l<3:76> el<3:77>
+n<> u<14> t<Expression> p<15> c<13> l<3:76> el<3:77>
+n<> u<15> t<Argument> p<16> c<14> l<3:76> el<3:77>
+n<> u<16> t<List_of_arguments> p<17> c<10> l<3:18> el<3:77>
+n<> u<17> t<Subroutine_call> p<18> c<5> l<3:9> el<3:78>
+n<> u<18> t<Subroutine_call_statement> p<19> c<17> l<3:9> el<3:79>
+n<> u<19> t<Statement_item> p<20> c<18> l<3:9> el<3:79>
+n<> u<20> t<Statement> p<21> c<19> l<3:9> el<3:79>
+n<> u<21> t<Statement_or_null> p<57> c<20> s<38> l<3:9> el<3:79>
n<> u<22> t<Dollar_keyword> p<34> s<23> l<5:9> el<5:10>
n<display> u<23> t<StringConst> p<34> s<33> l<5:10> el<5:17>
-n<"${SURELOG_DIR}/tests/PreprocLine/fake.v"> u<24> t<StringLiteral> p<25> l<5:18> el<5:64>
-n<> u<25> t<Primary_literal> p<26> c<24> l<5:18> el<5:64>
-n<> u<26> t<Primary> p<27> c<25> l<5:18> el<5:64>
-n<> u<27> t<Expression> p<33> c<26> s<32> l<5:18> el<5:64>
-n<102> u<28> t<IntConst> p<29> l<5:66> el<5:69>
-n<> u<29> t<Primary_literal> p<30> c<28> l<5:66> el<5:69>
-n<> u<30> t<Primary> p<31> c<29> l<5:66> el<5:69>
-n<> u<31> t<Expression> p<32> c<30> l<5:66> el<5:69>
-n<> u<32> t<Argument> p<33> c<31> l<5:66> el<5:69>
-n<> u<33> t<List_of_arguments> p<34> c<27> l<5:18> el<5:69>
-n<> u<34> t<Subroutine_call> p<35> c<22> l<5:9> el<5:70>
-n<> u<35> t<Subroutine_call_statement> p<36> c<34> l<5:9> el<5:71>
-n<> u<36> t<Statement_item> p<37> c<35> l<5:9> el<5:71>
-n<> u<37> t<Statement> p<38> c<36> l<5:9> el<5:71>
-n<> u<38> t<Statement_or_null> p<57> c<37> s<55> l<5:9> el<5:71>
+n<"${SURELOG_DIR}/tests/PreprocLine/fake.v"> u<24> t<StringLiteral> p<25> l<5:18> el<5:74>
+n<> u<25> t<Primary_literal> p<26> c<24> l<5:18> el<5:74>
+n<> u<26> t<Primary> p<27> c<25> l<5:18> el<5:74>
+n<> u<27> t<Expression> p<33> c<26> s<32> l<5:18> el<5:74>
+n<102> u<28> t<IntConst> p<29> l<5:76> el<5:79>
+n<> u<29> t<Primary_literal> p<30> c<28> l<5:76> el<5:79>
+n<> u<30> t<Primary> p<31> c<29> l<5:76> el<5:79>
+n<> u<31> t<Expression> p<32> c<30> l<5:76> el<5:79>
+n<> u<32> t<Argument> p<33> c<31> l<5:76> el<5:79>
+n<> u<33> t<List_of_arguments> p<34> c<27> l<5:18> el<5:79>
+n<> u<34> t<Subroutine_call> p<35> c<22> l<5:9> el<5:80>
+n<> u<35> t<Subroutine_call_statement> p<36> c<34> l<5:9> el<5:81>
+n<> u<36> t<Statement_item> p<37> c<35> l<5:9> el<5:81>
+n<> u<37> t<Statement> p<38> c<36> l<5:9> el<5:81>
+n<> u<38> t<Statement_or_null> p<57> c<37> s<55> l<5:9> el<5:81>
n<> u<39> t<Dollar_keyword> p<51> s<40> f<0> l<10:9> el<10:10>
n<display> u<40> t<StringConst> p<51> s<50> f<0> l<10:10> el<10:17>
n<""> u<41> t<StringLiteral> p<42> f<0> l<10:18> el<10:20>
diff --git a/tests/TestSepComp/TestSepComp.log b/tests/TestSepComp/TestSepComp.log
index 54b465dd..93b1ed8a 100644
--- a/tests/TestSepComp/TestSepComp.log
+++ b/tests/TestSepComp/TestSepComp.log
@@ -20,12 +20,12 @@
[WARNING] : 1
[ NOTE] : 0
[INF:CM0023] Creating log file "${SURELOG_DIR}/tests/TestSepComp/slpp_all/surelog.log".
+PARSER CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepComp/top.sv
PARSER CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepComp/pkg1.sv
PARSER CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepComp/pkg2.sv
-PARSER CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepComp/top.sv
+[WRN:PA0205] ${SURELOG_DIR}/tests/TestSepComp/top.sv:1:1: No timescale set for "top".
[WRN:PA0205] ${SURELOG_DIR}/tests/TestSepComp/pkg1.sv:1:1: No timescale set for "pkg1".
[WRN:PA0205] ${SURELOG_DIR}/tests/TestSepComp/pkg2.sv:1:1: No timescale set for "pkg2".
-[WRN:PA0205] ${SURELOG_DIR}/tests/TestSepComp/top.sv:1:1: No timescale set for "top".
[INF:CP0300] Compilation...
[INF:CP0301] ${SURELOG_DIR}/tests/TestSepComp/pkg1.sv:1:1: Compile package "pkg1".
[INF:CP0301] ${SURELOG_DIR}/tests/TestSepComp/pkg2.sv:1:1: Compile package "pkg2".
diff --git a/tests/TestSepComp/badpath/TestSepCompBadPath.log b/tests/TestSepComp/badpath/TestSepCompBadPath.log
index 5b90118b..92298ff6 100644
--- a/tests/TestSepComp/badpath/TestSepCompBadPath.log
+++ b/tests/TestSepComp/badpath/TestSepCompBadPath.log
@@ -22,19 +22,19 @@
[WARNING] : 3
[ NOTE] : 0
[INF:CM0023] Creating log file "${SURELOG_DIR}/tests/TestSepComp/badpath/slpp_all/surelog.log".
-PARSER CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepComp/pkg1.sv
-PARSER CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepComp/pkg2.sv
PARSER CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepComp/badpath/badtop.sv
PARSER CACHE USED FOR: ${SURELOG_DIR}/tests/EvalFunc/dut.sv
-[WRN:PA0205] ${SURELOG_DIR}/tests/TestSepComp/pkg1.sv:1:1: No timescale set for "pkg1".
-[WRN:PA0205] ${SURELOG_DIR}/tests/TestSepComp/pkg2.sv:1:1: No timescale set for "pkg2".
+PARSER CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepComp/pkg1.sv
+PARSER CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepComp/pkg2.sv
[WRN:PA0205] ${SURELOG_DIR}/tests/TestSepComp/badpath/badtop.sv:1:1: No timescale set for "badtop".
[WRN:PA0205] ${SURELOG_DIR}/tests/EvalFunc/dut.sv:1:1: No timescale set for "prim_util_pkg".
[WRN:PA0205] ${SURELOG_DIR}/tests/EvalFunc/dut.sv:22:1: No timescale set for "top".
+[WRN:PA0205] ${SURELOG_DIR}/tests/TestSepComp/pkg1.sv:1:1: No timescale set for "pkg1".
+[WRN:PA0205] ${SURELOG_DIR}/tests/TestSepComp/pkg2.sv:1:1: No timescale set for "pkg2".
[INF:CP0300] Compilation...
+[INF:CP0301] ${SURELOG_DIR}/tests/EvalFunc/dut.sv:1:1: Compile package "prim_util_pkg".
[INF:CP0301] ${SURELOG_DIR}/tests/TestSepComp/pkg1.sv:1:1: Compile package "pkg1".
[INF:CP0301] ${SURELOG_DIR}/tests/TestSepComp/pkg2.sv:1:1: Compile package "pkg2".
-[INF:CP0301] ${SURELOG_DIR}/tests/EvalFunc/dut.sv:1:1: Compile package "prim_util_pkg".
[INF:CP0303] ${SURELOG_DIR}/tests/TestSepComp/badpath/badtop.sv:1:1: Compile module "work@badtop".
[INF:CP0303] ${SURELOG_DIR}/tests/EvalFunc/dut.sv:22:1: Compile module "work@top".
[INF:CP0302] Compile class "work@mailbox".
diff --git a/tests/TestSepCompNoHash/TestSepCompNoHash.log b/tests/TestSepCompNoHash/TestSepCompNoHash.log
index 0361ce30..9f41c247 100644
--- a/tests/TestSepCompNoHash/TestSepCompNoHash.log
+++ b/tests/TestSepCompNoHash/TestSepCompNoHash.log
@@ -20,15 +20,15 @@
[WARNING] : 1
[ NOTE] : 0
[INF:CM0023] Creating log file "${SURELOG_DIR}/tests/TestSepCompNoHash/slpp_all/surelog.log".
-PP CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepCompNoHash/top.sv
PP CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepCompNoHash/pkg1.sv
PP CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepCompNoHash/pkg2.sv
-PARSER CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepCompNoHash/top.sv
+PP CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepCompNoHash/top.sv
PARSER CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepCompNoHash/pkg1.sv
PARSER CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepCompNoHash/pkg2.sv
-[WRN:PA0205] ${SURELOG_DIR}/tests/TestSepCompNoHash/top.sv:1:1: No timescale set for "top".
+PARSER CACHE USED FOR: ${SURELOG_DIR}/tests/TestSepCompNoHash/top.sv
[WRN:PA0205] ${SURELOG_DIR}/tests/TestSepCompNoHash/pkg1.sv:1:1: No timescale set for "pkg1".
[WRN:PA0205] ${SURELOG_DIR}/tests/TestSepCompNoHash/pkg2.sv:1:1: No timescale set for "pkg2".
+[WRN:PA0205] ${SURELOG_DIR}/tests/TestSepCompNoHash/top.sv:1:1: No timescale set for "top".
[INF:CP0300] Compilation...
[INF:CP0301] ${SURELOG_DIR}/tests/TestSepCompNoHash/pkg1.sv:1:1: Compile package "pkg1".
[INF:CP0301] ${SURELOG_DIR}/tests/TestSepCompNoHash/pkg2.sv:1:1: Compile package "pkg2".
diff --git a/tests/UnitLibrary/UnitLibrary.log b/tests/UnitLibrary/UnitLibrary.log
index 3bdfec55..1c59387a 100644
--- a/tests/UnitLibrary/UnitLibrary.log
+++ b/tests/UnitLibrary/UnitLibrary.log
@@ -22,8 +22,8 @@ LIB: lib1
${SURELOG_DIR}/tests/UnitLibrary/lib1/bot.sv
LIB: lib2
- ${SURELOG_DIR}/tests/UnitLibrary/lib2/sub.v
${SURELOG_DIR}/tests/UnitLibrary/lib2/bot.sv
+ ${SURELOG_DIR}/tests/UnitLibrary/lib2/sub.v
LIB: lib3
${SURELOG_DIR}/tests/UnitLibrary/lib3/sub.v
@@ -49,8 +49,8 @@ LIB: libw
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/UnitLibrary/rtl/adder.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/UnitLibrary/gate/adder.vg".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/UnitLibrary/lib1/bot.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/UnitLibrary/lib2/sub.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/UnitLibrary/lib2/bot.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/UnitLibrary/lib2/sub.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/UnitLibrary/lib3/sub.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/UnitLibrary/libwconfig/libw1/wsub.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/tests/UnitLibrary/libwconfig/libw2/wsub.v".
@@ -61,8 +61,8 @@ LIB: libw
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/UnitLibrary/rtl/adder.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/UnitLibrary/gate/adder.vg".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/UnitLibrary/lib1/bot.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/UnitLibrary/lib2/sub.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/UnitLibrary/lib2/bot.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/UnitLibrary/lib2/sub.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/UnitLibrary/lib3/sub.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/UnitLibrary/libwconfig/libw1/wsub.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/UnitLibrary/libwconfig/libw2/wsub.v".
diff --git a/third_party/UHDM b/third_party/UHDM
--- a/third_party/UHDM
+++ b/third_party/UHDM
@@ -1 +1 @@
-Subproject commit 7d90dd0e68759775d0c86885d991925096b5b496
+Subproject commit 7d90dd0e68759775d0c86885d991925096b5b496-dirty
diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log
index b3dabfd7..7a54c4f2 100644
--- a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log
+++ b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log
@@ -1,11 +1,22 @@
[INF:CM0023] Creating log file "${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/surelog.log".
[WRN:CM0010] Command line argument "-Wno-UNOPTFLAT" ignored.
-Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_parser; cmake -G "Unix Makefiles" .; make -j 16
--- Configuring done
--- Generating done
+Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_parser; cmake -G "Unix Makefiles" .; make -j 28
+�[0mCMake Deprecation Warning at CMakeLists.txt:1 (cmake_minimum_required):
+ Compatibility with CMake < 3.10 will be removed from a future version of
+ CMake.
+
+ Update the VERSION argument <min> value. Or, use the <min>...<max> syntax
+ to tell CMake that the project requires at least <min> but has been updated
+ to work with policies introduced by <max> or earlier.
+
+�[0m
+-- Configuring done (0.0s)
+-- Generating done (0.0s)
-- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_parser
-[100%] Generating preprocessing
+make[1]: Entering directory '${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_parser'
+[100%] �[34m�[1mGenerating preprocessing�[0m
[100%] Built target Parse
+make[1]: Leaving directory '${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_parser'
Surelog preproc status: 0
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/src/uvm_pkg.sv".
PP CACHE USED FOR: ${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/src/uvm_pkg.sv
@@ -60,27 +71,50 @@ PP CACHE USED FOR: ${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/src/uvm_pkg.sv
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/CoresSweRVMP/design/lib/mem_lib.sv".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/CoresSweRVMP/design/lib/ahb_to_axi4.sv".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/CoresSweRVMP/design/lib/axi4_to_ahb.sv".
-Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess; cmake -G "Unix Makefiles" .; make -j 16
--- Configuring done
--- Generating done
+Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess; cmake -G "Unix Makefiles" .; make -j 28
+�[0mCMake Deprecation Warning at CMakeLists.txt:1 (cmake_minimum_required):
+ Compatibility with CMake < 3.10 will be removed from a future version of
+ CMake.
+
+ Update the VERSION argument <min> value. Or, use the <min>...<max> syntax
+ to tell CMake that the project requires at least <min> but has been updated
+ to work with policies introduced by <max> or earlier.
+
+�[0m
+-- Configuring done (0.0s)
+-- Generating done (0.0s)
-- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess
-[ 6%] Generating 10_lsu_bus_intf.sv
-[ 12%] Generating 11_ifu_bp_ctl.sv
-[ 18%] Generating 12_beh_lib.sv
-[ 25%] Generating 13_ifu_mem_ctl.sv
-[ 31%] Generating 14_mem_lib.sv
-[ 37%] Generating 15_exu.sv
-[ 43%] Generating 16_dec_decode_ctl.sv
-[ 50%] Generating 1_lsu_stbuf.sv
-[ 56%] Generating 2_ahb_to_axi4.sv
-[ 62%] Generating 3_rvjtag_tap.sv
-[ 68%] Generating 5_lsu_bus_buffer.sv
-[ 75%] Generating 4_dec_tlu_ctl.sv
-[ 81%] Generating 6_dbg.sv
-[ 87%] Generating 7_axi4_to_ahb.sv
-[100%] Generating 8_ifu_aln_ctl.sv
-[100%] Generating 9_tb_top.sv
+make[1]: Entering directory '${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess'
+[ 3%] �[34m�[1mGenerating 15_ahb_sif.sv�[0m
+[ 7%] �[34m�[1mGenerating 12_ifu_ic_mem.sv�[0m
+[ 10%] �[34m�[1mGenerating 18_dec_ib_ctl.sv�[0m
+[ 14%] �[34m�[1mGenerating 16_dec_decode_ctl.sv�[0m
+[ 21%] �[34m�[1mGenerating 11_ifu_bp_ctl.sv�[0m
+[ 21%] �[34m�[1mGenerating 14_lsu_dccm_ctl.sv�[0m
+[ 25%] �[34m�[1mGenerating 17_lsu_bus_buffer.sv�[0m
+[ 28%] �[34m�[1mGenerating 13_ifu_mem_ctl.sv�[0m
+[ 32%] �[34m�[1mGenerating 19_dec_tlu_ctl.sv�[0m
+[ 35%] �[34m�[1mGenerating 1_lsu_lsc_ctl.sv�[0m
+[ 39%] �[34m�[1mGenerating 20_lsu_stbuf.sv�[0m
+[ 42%] �[34m�[1mGenerating 10_rvjtag_tap.sv�[0m
+[ 46%] �[34m�[1mGenerating 21_dec.sv�[0m
+[ 53%] �[34m�[1mGenerating 24_axi4_to_ahb.sv�[0m
+[ 53%] �[34m�[1mGenerating 25_exu.sv�[0m
+[ 57%] �[34m�[1mGenerating 22_lsu_dccm_mem.sv�[0m
+[ 60%] �[34m�[1mGenerating 23_mem_lib.sv�[0m
+[ 64%] �[34m�[1mGenerating 27_beh_lib.sv�[0m
+[ 75%] �[34m�[1mGenerating 2_ahb_to_axi4.sv�[0m
+[ 75%] �[34m�[1mGenerating 4_lsu_bus_intf.sv�[0m
+[ 75%] �[34m�[1mGenerating 28_tb_top.sv�[0m
+[ 78%] �[34m�[1mGenerating 3_swerv_wrapper.sv�[0m
+[ 82%] �[34m�[1mGenerating 26_lsu.sv�[0m
+[ 85%] �[34m�[1mGenerating 7_dma_ctrl.sv�[0m
+[ 89%] �[34m�[1mGenerating 5_pic_ctrl.sv�[0m
+[ 96%] �[34m�[1mGenerating 8_ifu_aln_ctl.sv�[0m
+[ 92%] �[34m�[1mGenerating 6_swerv.sv�[0m
+[100%] �[34m�[1mGenerating 9_dbg.sv�[0m
[100%] Built target Parse
+make[1]: Leaving directory '${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess'
Surelog parsing status: 0
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/src/uvm_pkg.sv".
PARSER CACHE USED FOR: ${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/src/uvm_pkg.sv
diff --git a/third_party/tests/Earlgrey_Verilator_01_05_21/sim-icarus/Earlgrey_Verilator_01_05_21.log b/third_party/tests/Earlgrey_Verilator_01_05_21/sim-icarus/Earlgrey_Verilator_01_05_21.log
index e206b4d4..d945dbc7 100644
--- a/third_party/tests/Earlgrey_Verilator_01_05_21/sim-icarus/Earlgrey_Verilator_01_05_21.log
+++ b/third_party/tests/Earlgrey_Verilator_01_05_21/sim-icarus/Earlgrey_Verilator_01_05_21.log
@@ -14499,7 +14499,7 @@ var_select 16611
[ NOTE] : 111
============================== Begin Linting Results ==============================
-[LINT]: ${SURELOG_DIR}/third_party/tests/Earlgrey_Verilator_01_05_21/src/lowrisc_dv_dv_macros_0/dv_macros.svh:476:248: Non synthesizable construct, name
+[LINT]: ${SURELOG_DIR}/third_party/tests/Earlgrey_Verilator_01_05_21/src/lowrisc_dv_dv_macros_0/dv_macros.svh:476:258: Non synthesizable construct, name
[LINT]: ${SURELOG_DIR}/third_party/tests/Earlgrey_Verilator_01_05_21/src/lowrisc_dv_dpi_dmidpi_0.1/dmidpi.sv:25:12: Non synthesizable construct,
[LINT]: ${SURELOG_DIR}/third_party/tests/Earlgrey_Verilator_01_05_21/src/lowrisc_dv_dpi_dmidpi_0.1/dmidpi.sv:25:12: Non synthesizable construct,
[LINT]: ${SURELOG_DIR}/third_party/tests/Earlgrey_Verilator_01_05_21/src/lowrisc_dv_dpi_dmidpi_0.1/dmidpi.sv:28:35: Non synthesizable construct,
diff --git a/third_party/tests/NyuziProcessor/NyuziProcessor.log b/third_party/tests/NyuziProcessor/NyuziProcessor.log
index e08fe09e..7fcd459c 100644
--- a/third_party/tests/NyuziProcessor/NyuziProcessor.log
+++ b/third_party/tests/NyuziProcessor/NyuziProcessor.log
@@ -9,66 +9,66 @@
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/trace_logger.sv".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/sim_ps2.sv".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/sim_sdram.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/scoreboard.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_axi_bus_interface.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_store_queue.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/nyuzi.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/synchronizer.sv".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/control_registers.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage5.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/thread_select_stage.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/core.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/instruction_decode_stage.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/writeback_stage.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_store_queue.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/reciprocal_rom.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage3.sv".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/jtag_tap_controller.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_pending_miss_cam.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/oh_to_idx.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sync_fifo.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_2r1w.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_arb_stage.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/int_execute_stage.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/performance_counters.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_update_stage.sv".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_l2_interface.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_tag_stage.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/reciprocal_rom.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/tlb.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage2.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/core.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/thread_select_stage.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/rr_arbiter.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_request_queue.sv".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_data_stage.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage2.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_axi_bus_interface.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/nyuzi.sv".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cam.sv".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_read_stage.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/rr_arbiter.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/synchronizer.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage1.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage4.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_tag_stage.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage3.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_2r1w.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_arb_stage.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/operand_fetch_stage.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_load_miss_queue.sv".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_1r1w.sv".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_tag_stage.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/instruction_decode_stage.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_tag_stage.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/scoreboard.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_pending_miss_cam.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage5.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_load_miss_queue.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/oh_to_idx.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage1.sv".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_data_stage.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_request_queue.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/performance_counters.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/on_chip_debugger.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/writeback_stage.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_update_stage.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cache_lru.sv".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_interconnect.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sync_fifo.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage4.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/tlb.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_tag_stage.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/on_chip_debugger.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/operand_fetch_stage.sv".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/idx_to_oh.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cache_lru.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/int_execute_stage.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/async_fifo.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/gpio_controller.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_sram.sv".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/spi_controller.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/logic_analyzer.sv".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_async_bridge.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_sequencer.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_controller.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart_receive.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_interconnect.sv".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_rom.sv".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart.sv".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/timer.sv".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/ps2_controller.sv".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart_transmit.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/logic_analyzer.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart_receive.sv".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/sdram_controller.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_controller.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/async_fifo.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/ps2_controller.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_sequencer.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_interconnect.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_sram.sv".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/gpio_controller.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/axi_protocol_checker.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/sim_jtag.sv".
@@ -76,66 +76,66 @@
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/trace_logger.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/sim_ps2.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/sim_sdram.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/scoreboard.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_axi_bus_interface.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_store_queue.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/nyuzi.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/synchronizer.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/control_registers.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage5.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/thread_select_stage.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/core.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/instruction_decode_stage.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/writeback_stage.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_store_queue.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/reciprocal_rom.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage3.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/jtag_tap_controller.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_pending_miss_cam.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/oh_to_idx.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sync_fifo.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_2r1w.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_arb_stage.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/int_execute_stage.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/performance_counters.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_update_stage.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_l2_interface.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_tag_stage.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/reciprocal_rom.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/tlb.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage2.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/core.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/thread_select_stage.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/rr_arbiter.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_request_queue.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_data_stage.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage2.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_axi_bus_interface.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/nyuzi.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cam.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_read_stage.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/rr_arbiter.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/synchronizer.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage1.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage4.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_tag_stage.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage3.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_2r1w.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_arb_stage.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/operand_fetch_stage.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_load_miss_queue.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_1r1w.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_tag_stage.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/instruction_decode_stage.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_tag_stage.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/scoreboard.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_pending_miss_cam.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage5.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_load_miss_queue.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/oh_to_idx.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage1.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_data_stage.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_request_queue.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/performance_counters.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/on_chip_debugger.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/writeback_stage.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_update_stage.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cache_lru.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_interconnect.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sync_fifo.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage4.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/tlb.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_tag_stage.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/on_chip_debugger.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/operand_fetch_stage.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/idx_to_oh.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cache_lru.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/int_execute_stage.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/async_fifo.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/gpio_controller.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_sram.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/spi_controller.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/logic_analyzer.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_async_bridge.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_sequencer.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_controller.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart_receive.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_interconnect.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_rom.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/timer.sv".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/ps2_controller.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart_transmit.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/logic_analyzer.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/uart_receive.sv".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/sdram_controller.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_controller.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/async_fifo.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/ps2_controller.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_sequencer.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_interconnect.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_sram.sv".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/gpio_controller.sv".
[INF:CM0029] Using global timescale: "10ps/10ps".
[INF:CP0300] Compilation...
[INF:CP0301] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/defines.svh:22:1: Compile package "defines".
@@ -265,97 +265,97 @@
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/trace_logger.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/scoreboard.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/control_registers.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_axi_bus_interface.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/thread_select_stage.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_store_queue.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/core.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/nyuzi.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/instruction_decode_stage.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/control_registers.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/writeback_stage.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage5.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_store_queue.sv:22:1: previous definition.
+[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage3.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/jtag_tap_controller.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_pending_miss_cam.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sync_fifo.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_l2_interface.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_arb_stage.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_tag_stage.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/int_execute_stage.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/tlb.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_update_stage.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage2.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_l2_interface.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/core.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/thread_select_stage.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_request_queue.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_data_stage.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cam.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage2.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_read_stage.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_axi_bus_interface.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage1.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/nyuzi.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage4.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cam.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_read_stage.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_tag_stage.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_1r1w.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage3.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_tag_stage.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_arb_stage.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_tag_stage.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/operand_fetch_stage.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/scoreboard.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_load_miss_queue.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_pending_miss_cam.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sram_1r1w.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage5.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_tag_stage.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l1_load_miss_queue.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/instruction_decode_stage.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage1.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/ifetch_data_stage.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_request_queue.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cache_lru.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/on_chip_debugger.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_interconnect.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/writeback_stage.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/fp_execute_stage4.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/l2_cache_update_stage.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/tlb.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/io_interconnect.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_tag_stage.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/sync_fifo.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/on_chip_debugger.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/cache_lru.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/operand_fetch_stage.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/int_execute_stage.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/spi_controller.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/async_fifo.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_rom.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/gpio_controller.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/sdram_controller.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_sram.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_controller.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/spi_controller.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/async_fifo.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/vga_controller.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/ps2_controller.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_interconnect.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_rom.sv:22:1: previous definition.
-[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/ps2_controller.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/axi_sram.sv:22:1: previous definition.
[WRN:CP0329] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/testbench/soc_tb.sv:22:1: Multiply defined package: "defines",
- ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/sdram_controller.sv:22:1: previous definition.
+ ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/gpio_controller.sv:22:1: previous definition.
[NTE:CP0309] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/async_fifo.sv:37:29: Implicit port type (wire) for "read_data".
[NTE:CP0309] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/core/dcache_tag_stage.sv:77:49: Implicit port type (wire) for "dt_update_itlb_asid".
[NTE:CP0309] ${SURELOG_DIR}/third_party/tests/NyuziProcessor/hardware/fpga/common/gpio_controller.sv:35:31: Implicit port type (wire) for "gpio_value".
diff --git a/third_party/tests/ariane/Ariane.log b/third_party/tests/ariane/Ariane.log
index 155b7e33..67ca0f51 100644
--- a/third_party/tests/ariane/Ariane.log
+++ b/third_party/tests/ariane/Ariane.log
@@ -1,3 +1,4 @@
+make[1]: Entering directory '${SURELOG_DIR}/third_party/tests/ariane'
Makefile:139: XCELIUM_HOME not set which is necessary for compiling DPIs when using XCELIUM
[Verilator] Building Model
${SURELOG_DIR}/build/bin/surelog -DVERILATOR=1 -sverilog -parse -d coveruhdm -verbose -timescale=1ps/1ps ${SURELOG_DIR}/third_party/tests/ariane/include/riscv_pkg.sv ${SURELOG_DIR}/third_party/tests/ariane/src/riscv-dbg/src/dm_pkg.sv ${SURELOG_DIR}/third_party/tests/ariane/include/ariane_pkg.sv ${SURELOG_DIR}/third_party/tests/ariane/include/std_cache_pkg.sv ${SURELOG_DIR}/third_party/tests/ariane/include/wt_cache_pkg.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi/src/axi_pkg.sv ${SURELOG_DIR}/third_party/tests/ariane/src/register_interface/src/reg_intf.sv ${SURELOG_DIR}/third_party/tests/ariane/src/register_interface/src/reg_intf_pkg.sv ${SURELOG_DIR}/third_party/tests/ariane/include/axi_intf.sv ${SURELOG_DIR}/third_party/tests/ariane/tb/ariane_soc_pkg.sv ${SURELOG_DIR}/third_party/tests/ariane/tb/ariane_axi_soc_pkg.sv ${SURELOG_DIR}/third_party/tests/ariane/include/ariane_axi_pkg.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpnew_pkg.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv ${SURELOG_DIR}/third_party/tests/ariane/src/alu.sv ${SURELOG_DIR}/third_party/tests/ariane/src/amo_buffer.sv ${SURELOG_DIR}/third_party/tests/ariane/src/ariane_regfile_ff.sv ${SURELOG_DIR}/third_party/tests/ariane/src/ariane.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_adapter.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_shim.sv ${SURELOG_DIR}/third_party/tests/ariane/src/branch_unit.sv ${SURELOG_DIR}/third_party/tests/ariane/src/commit_stage.sv ${SURELOG_DIR}/third_party/tests/ariane/src/compressed_decoder.sv ${SURELOG_DIR}/third_party/tests/ariane/src/controller.sv ${SURELOG_DIR}/third_party/tests/ariane/src/csr_buffer.sv ${SURELOG_DIR}/third_party/tests/ariane/src/csr_regfile.sv ${SURELOG_DIR}/third_party/tests/ariane/src/decoder.sv ${SURELOG_DIR}/third_party/tests/ariane/src/dromajo_ram.sv ${SURELOG_DIR}/third_party/tests/ariane/src/ex_stage.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu_wrap.sv ${SURELOG_DIR}/third_party/tests/ariane/src/id_stage.sv ${SURELOG_DIR}/third_party/tests/ariane/src/instr_realign.sv ${SURELOG_DIR}/third_party/tests/ariane/src/issue_read_operands.sv ${SURELOG_DIR}/third_party/tests/ariane/src/issue_stage.sv ${SURELOG_DIR}/third_party/tests/ariane/src/load_store_unit.sv ${SURELOG_DIR}/third_party/tests/ariane/src/load_unit.sv ${SURELOG_DIR}/third_party/tests/ariane/src/mmu.sv ${SURELOG_DIR}/third_party/tests/ariane/src/multiplier.sv ${SURELOG_DIR}/third_party/tests/ariane/src/mult.sv ${SURELOG_DIR}/third_party/tests/ariane/src/perf_counters.sv ${SURELOG_DIR}/third_party/tests/ariane/src/ptw.sv ${SURELOG_DIR}/third_party/tests/ariane/src/re_name.sv ${SURELOG_DIR}/third_party/tests/ariane/src/scoreboard.sv ${SURELOG_DIR}/third_party/tests/ariane/src/serdiv.sv ${SURELOG_DIR}/third_party/tests/ariane/src/store_buffer.sv ${SURELOG_DIR}/third_party/tests/ariane/src/store_unit.sv ${SURELOG_DIR}/third_party/tests/ariane/src/tlb.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpnew_cast_multi.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpnew_classifier.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpnew_divsqrt_multi.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpnew_fma_multi.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpnew_fma.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpnew_noncomp.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpnew_opgroup_block.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpnew_opgroup_fmt_slice.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpnew_opgroup_multifmt_slice.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpnew_rounding.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpnew_top.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv ${SURELOG_DIR}/third_party/tests/ariane/src/frontend/bht.sv ${SURELOG_DIR}/third_party/tests/ariane/src/frontend/btb.sv ${SURELOG_DIR}/third_party/tests/ariane/src/frontend/frontend.sv ${SURELOG_DIR}/third_party/tests/ariane/src/frontend/instr_queue.sv ${SURELOG_DIR}/third_party/tests/ariane/src/frontend/instr_scan.sv ${SURELOG_DIR}/third_party/tests/ariane/src/frontend/ras.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/amo_alu.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/cache_ctrl.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/cva6_icache_axi_wrapper.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/cva6_icache.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/miss_handler.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/std_cache_subsystem.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/std_icache.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/std_nbdcache.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/tag_cmp.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/wt_axi_adapter.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/wt_cache_subsystem.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/wt_dcache_ctrl.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/wt_dcache_mem.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/wt_dcache_missunit.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/wt_dcache.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/wt_dcache_wbuffer.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/wt_icache.sv ${SURELOG_DIR}/third_party/tests/ariane/src/cache_subsystem/wt_l15_adapter.sv ${SURELOG_DIR}/third_party/tests/ariane/bootrom/bootrom.sv ${SURELOG_DIR}/third_party/tests/ariane/src/clint/axi_lite_interface.sv ${SURELOG_DIR}/third_party/tests/ariane/src/clint/clint.sv ${SURELOG_DIR}/third_party/tests/ariane/fpga/src/axi2apb/src/axi2apb_64_32.sv ${SURELOG_DIR}/third_party/tests/ariane/fpga/src/axi2apb/src/axi2apb.sv ${SURELOG_DIR}/third_party/tests/ariane/fpga/src/axi2apb/src/axi2apb_wrap.sv ${SURELOG_DIR}/third_party/tests/ariane/fpga/src/apb_timer/apb_timer.sv ${SURELOG_DIR}/third_party/tests/ariane/fpga/src/apb_timer/timer.sv ${SURELOG_DIR}/third_party/tests/ariane/fpga/src/axi_slice/src/axi_ar_buffer.sv ${SURELOG_DIR}/third_party/tests/ariane/fpga/src/axi_slice/src/axi_aw_buffer.sv ${SURELOG_DIR}/third_party/tests/ariane/fpga/src/axi_slice/src/axi_b_buffer.sv ${SURELOG_DIR}/third_party/tests/ariane/fpga/src/axi_slice/src/axi_r_buffer.sv ${SURELOG_DIR}/third_party/tests/ariane/fpga/src/axi_slice/src/axi_single_slice.sv ${SURELOG_DIR}/third_party/tests/ariane/fpga/src/axi_slice/src/axi_slice.sv ${SURELOG_DIR}/third_party/tests/ariane/fpga/src/axi_slice/src/axi_slice_wrap.sv ${SURELOG_DIR}/third_party/tests/ariane/fpga/src/axi_slice/src/axi_w_buffer.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/apb_regs_top.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_address_decoder_AR.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_address_decoder_AW.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_address_decoder_BR.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_address_decoder_BW.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_address_decoder_DW.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_AR_allocator.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_AW_allocator.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_BR_allocator.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_BW_allocator.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_DW_allocator.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_multiplexer.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_node_arbiter.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_node_intf_wrap.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_node.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_node_wrap_with_slices.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_regs_top.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_request_block.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_node/src/axi_response_block.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_riscv_atomics/src/axi_res_tbl.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_riscv_atomics/src/axi_riscv_amos_alu.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_riscv_atomics/src/axi_riscv_amos.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_riscv_atomics/src/axi_riscv_atomics.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_riscv_atomics/src/axi_riscv_atomics_wrap.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_riscv_atomics/src/axi_riscv_lrsc.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_riscv_atomics/src/axi_riscv_lrsc_wrap.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi_mem_if/src/axi2mem.sv ${SURELOG_DIR}/third_party/tests/ariane/src/pmp/src/pmp_entry.sv ${SURELOG_DIR}/third_party/tests/ariane/src/pmp/src/pmp.sv ${SURELOG_DIR}/third_party/tests/ariane/src/rv_plic/rtl/rv_plic_target.sv ${SURELOG_DIR}/third_party/tests/ariane/src/rv_plic/rtl/rv_plic_gateway.sv ${SURELOG_DIR}/third_party/tests/ariane/src/rv_plic/rtl/plic_regmap.sv ${SURELOG_DIR}/third_party/tests/ariane/src/rv_plic/rtl/plic_top.sv ${SURELOG_DIR}/third_party/tests/ariane/src/riscv-dbg/src/dmi_cdc.sv ${SURELOG_DIR}/third_party/tests/ariane/src/riscv-dbg/src/dmi_jtag.sv ${SURELOG_DIR}/third_party/tests/ariane/src/riscv-dbg/src/dmi_jtag_tap.sv ${SURELOG_DIR}/third_party/tests/ariane/src/riscv-dbg/src/dm_csrs.sv ${SURELOG_DIR}/third_party/tests/ariane/src/riscv-dbg/src/dm_mem.sv ${SURELOG_DIR}/third_party/tests/ariane/src/riscv-dbg/src/dm_sba.sv ${SURELOG_DIR}/third_party/tests/ariane/src/riscv-dbg/src/dm_top.sv ${SURELOG_DIR}/third_party/tests/ariane/src/riscv-dbg/debug_rom/debug_rom.sv ${SURELOG_DIR}/third_party/tests/ariane/src/register_interface/src/apb_to_reg.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi/src/axi_multicut.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/deprecated/generic_fifo.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/deprecated/pulp_sync.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/deprecated/find_first_one.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/rstgen_bypass.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/rstgen.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/stream_mux.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/stream_demux.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/exp_backoff.sv ${SURELOG_DIR}/third_party/tests/ariane/src/util/axi_master_connect.sv ${SURELOG_DIR}/third_party/tests/ariane/src/util/axi_slave_connect.sv ${SURELOG_DIR}/third_party/tests/ariane/src/util/axi_master_connect_rev.sv ${SURELOG_DIR}/third_party/tests/ariane/src/util/axi_slave_connect_rev.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi/src/axi_cut.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi/src/axi_join.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi/src/axi_delayer.sv ${SURELOG_DIR}/third_party/tests/ariane/src/axi/src/axi_to_axi_lite.sv ${SURELOG_DIR}/third_party/tests/ariane/src/fpga-support/rtl/SyncSpRamBeNx64.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/unread.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/sync.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/cdc_2phase.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/spill_register.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/sync_wedge.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/edge_detect.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/stream_arbiter.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/stream_arbiter_flushable.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/deprecated/fifo_v1.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/deprecated/fifo_v2.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/fifo_v3.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/lzc.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/popcount.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/rr_arb_tree.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/deprecated/rrarbiter.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/stream_delay.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/lfsr_8bit.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/lfsr_16bit.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/delta_counter.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/counter.sv ${SURELOG_DIR}/third_party/tests/ariane/src/common_cells/src/shift_reg.sv ${SURELOG_DIR}/third_party/tests/ariane/src/tech_cells_generic/src/pulp_clock_gating.sv ${SURELOG_DIR}/third_party/tests/ariane/src/tech_cells_generic/src/cluster_clock_inverter.sv ${SURELOG_DIR}/third_party/tests/ariane/src/tech_cells_generic/src/pulp_clock_mux2.sv ${SURELOG_DIR}/third_party/tests/ariane/tb/ariane_testharness.sv ${SURELOG_DIR}/third_party/tests/ariane/tb/ariane_peripherals.sv ${SURELOG_DIR}/third_party/tests/ariane/tb/common/uart.sv ${SURELOG_DIR}/third_party/tests/ariane/tb/common/SimDTM.sv ${SURELOG_DIR}/third_party/tests/ariane/tb/common/SimJTAG.sv +define+WT_DCACHE src/util/sram.sv tb/common/mock_uart.sv +incdir+src/axi_node --unroll-count 256 -Werror-PINMISSING -Werror-IMPLICIT -Wno-fatal -Wno-PINCONNECTEMPTY -Wno-ASSIGNDLY -Wno-DECLFILENAME -Wno-UNUSED -Wno-UNOPTFLAT -Wno-BLKANDNBLK -Wno-style -LDFLAGS "-Lblah/lib -Lblah/lib -Wl,-rpath,blah/lib -Wl,-rpath,blah/lib -lfesvr -lpthread" -CFLAGS " -DVL_DEBUG" -Wall --cc --vpi +incdir+src/common_cells/include/ --top-module ariane_testharness --Mdir work-ver -O3 --exe tb/ariane_tb.cpp tb/dpi/SimDTM.cc tb/dpi/SimJTAG.cc tb/dpi/remote_bitbang.cc tb/dpi/msim_helper.cc
@@ -12723,8 +12724,9 @@ there are 1 more instances of this message.
[WARNING] : 19
[ NOTE] : 55
cd work-ver && make -j -f Variane_testharness.mk
-make[1]: Entering directory '${SURELOG_DIR}/third_party/tests/ariane/work-ver'
-make[1]: Variane_testharness.mk: No such file or directory
-make[1]: *** No rule to make target 'Variane_testharness.mk'. Stop.
-make[1]: Leaving directory '${SURELOG_DIR}/third_party/tests/ariane/work-ver'
-make: *** [Makefile:634: verilate] Error 2
+make[2]: Entering directory '${SURELOG_DIR}/third_party/tests/ariane/work-ver'
+make[2]: Variane_testharness.mk: No such file or directory
+make[2]: *** No rule to make target 'Variane_testharness.mk'. Stop.
+make[2]: Leaving directory '${SURELOG_DIR}/third_party/tests/ariane/work-ver'
+make[1]: *** [Makefile:634: verilate] Error 2
+make[1]: Leaving directory '${SURELOG_DIR}/third_party/tests/ariane'
diff --git a/third_party/tests/oh/BasicOh.log b/third_party/tests/oh/BasicOh.log
index 3e84f37b..386ac8b3 100644
--- a/third_party/tests/oh/BasicOh.log
+++ b/third_party/tests/oh/BasicOh.log
@@ -1,282 +1,282 @@
[INF:CM0023] Creating log file "${SURELOG_DIR}/build/regression/BasicOh/slpp_all/surelog.log".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bitreverse.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_inv.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bitreverse.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_inv.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buf.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_parity.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v".
[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_parity.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v".
-[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v".
+[INF:PP0122] Preprocessing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_async.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_debouncer.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobufhi.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and3.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi211.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bitreverse.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai311.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oddr.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx2.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai32.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_inv.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_abs.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrqn.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor3.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edgealign.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux5.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffq.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa211.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi4.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi221.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_iddr.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor2.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao33.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand4.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2onehot.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa42.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao22.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_add.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pulse2pulse.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mult.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao32.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx4.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dsync.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa221.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffrq.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockgate.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rise2pulse.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat0.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_dp.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux6.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux12.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bitreverse.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsq.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nand3.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa33.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_memory_sp.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor2.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao31.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa222.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_datagate.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao222.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa62.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_inv.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_rsync.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockor.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai22.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ser2par.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buf.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_cdc.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fall2pulse.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux2.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_reg1.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi32.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux3.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_parity.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux4.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux9.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_shift.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi22.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pll.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux8.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai33.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi33.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_standby.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or3.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_edge2pulse.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrq.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa22.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_pwr_buf.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_gray2bin.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi311.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao21.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai31.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa311.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao221.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor3.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockdiv.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_par2ser.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa21.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mx3.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffnq.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao211.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or2.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa32.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latq.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_isobuflo.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi3.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_header.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_regfile.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_buffer.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_lat1.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi21.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffrqn.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi31.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffq.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_counter.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux7.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_latnq.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_aoi222.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and2.v".
[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai222.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor3.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsqn.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa32.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_parity.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_csa92.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffqn.v".
-[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_dffsqn.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xnor4.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_tristate.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_fifo_sync.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_delay.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mxi2.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffsq.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_stretcher.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai21.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_or4.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_and4.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor4.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_sdffqn.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_bin2gray.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_arbiter.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oai221.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_ao311.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_xor4.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_clockmux2.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_nor2.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_oa31.v".
+[INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_mux4.v".
[INF:CM0029] Using global timescale: "1ns/1ns".
[INF:CP0300] Compilation...
[INF:CP0303] ${SURELOG_DIR}/third_party/tests/oh/stdlib/hdl/oh_7seg_decode.v:8:1: Compile module "work@oh_7seg_decode".In the test folder I only find one usage of |
|
@Rodrigodd , please submit a PR here with the code change. |
|
I was not satisfied with the fix I proposed, so I took a better look to see if I could find a more proper fix for it. From the Verilog spec:
So I tried to look for the code that calculates diff --git a/templates/ExprEval.cpp b/templates/ExprEval.cpp
index 171dc0e..bdc4c03 100644
--- a/templates/ExprEval.cpp
+++ b/templates/ExprEval.cpp
@@ -4015,8 +4015,8 @@ expr *ExprEval::reduceExpr(const any *result, bool &invalidValue,
tps = tp;
}
- if ((name == "$high") || (name == "$low") || (name == "$left") ||
- (name == "$right")) {
+ if ((name == "$size") || (name == "$high") || (name == "$low") ||
+ (name == "$left") || (name == "$right")) {
VectorOfrange *ranges = nullptr;
if (tps) {
switch (tps->UhdmType()) {
@@ -4075,20 +4075,33 @@ expr *ExprEval::reduceExpr(const any *result, bool &invalidValue,
} else {
return lr;
}
+ } else if (name == "$size") {
+ // $size(a) == $high(a) - $low(a) + 1
+ if (lrv > rrv) {
+ bits = lrv - rrv + 1;
+ } else {
+ bits = rrv - lrv + 1;
+ }
+ found = true;
}
}
}
+ if (!found) {
+ if (name == "$right" || name == "$low") {
+ bits = 0;
+ }
- if (tps) {
- bits += size(tps, invalidValue, inst, pexpr, (name != "$size"));
- found = true;
- } else {
- if (object) {
- bits +=
- size(object, invalidValue, inst, pexpr, (name != "$size"));
+ if (tps) {
+ bits = size(tps, invalidValue, inst, pexpr, (name != "$size"));
found = true;
} else {
- invalidValue = true;
+ if (object) {
+ bits =
+ size(object, invalidValue, inst, pexpr, (name != "$size"));
+ found = true;
+ } else {
+ invalidValue = true;
+ }
}
}
} else if (argtype == UHDM_OBJECT_TYPE::uhdmoperation) {But when I tested it, I discovered that Surelog actually doesn't use the code above. Looking a bit more, I found that Surelog also implements it in a very similar way. So I tried the code below: diff --git a/src/DesignCompile/CompileExpression.cpp b/src/DesignCompile/CompileExpression.cpp
index d04b498e..cfb5db56 100644
--- a/src/DesignCompile/CompileExpression.cpp
+++ b/src/DesignCompile/CompileExpression.cpp
@@ -2146,13 +2146,8 @@ UHDM::any *CompileHelper::compileExpression(
result =
compileBits(component, fC, List_of_arguments, compileDesign,
reduce, pexpr, instance, false, muteErrors);
- } else if (name == "$size") {
- NodeId List_of_arguments = fC->Sibling(child);
- result =
- compileBits(component, fC, List_of_arguments, compileDesign,
- reduce, pexpr, instance, true, muteErrors);
} else if (name == "$high" || name == "$low" || name == "$left" ||
- name == "$right") {
+ name == "$right" || name == "$size") {
NodeId List_of_arguments = fC->Sibling(child);
result =
compileBound(component, fC, List_of_arguments, compileDesign,
@@ -4666,6 +4661,15 @@ UHDM::any *CompileHelper::compileBound(
} else {
return lr;
}
+ } else if (name == "size") {
+ // size = high - low + 1
+ UHDM::constant *c = s.MakeConstant();
+ int64_t size = (lrv > rrv) ? lrv - rrv + 1 : rrv - lrv + 1;
+ c->VpiValue("UINT:" + std::to_string(size));
+ c->VpiDecompile(std::to_string(size));
+ c->VpiConstType(vpiUIntConst);
+ c->VpiSize(64);
+ return c;
}
}
}Again, to my surprise, I saw that Surelog doesn't reach the point of successfully evaluating In the And looking now, I notice the above is also missing the Then I tried to just call In the end, I gave up. I will just submit the ad-hoc solution I presented in the OP. |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Description
I was trying to get a existing design loaded into Synlig, but I notice that
$sizeof a unpacked array was returning the size in bits of the full memory, instead of just the number of elements.I am not sure if I should have filled this issue on Synlig, Surelog or here, but, from what I can tell, the code responsible for evaluating
$sizeis mostly here.Reproduction
If I have the file
testsize.svbelow:And in the Surelog repository I run:
I can see from the output that the
vpiSizeofbis 8, where it should be 2.Full Output
Fix?
The patch below makes
$sizereturn the expected value in the case above, but I not sure if it will break others results, or if the function will still be wrong for other types.The text was updated successfully, but these errors were encountered: