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committedJul 24, 2020
Fix boards.txt, travis
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‎.travis.yml

+18-10
Original file line numberDiff line numberDiff line change
@@ -172,31 +172,37 @@ env:
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- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx5micr:LTO=disable,TimerClockSource=default,sketchclock=16pll,bod=4v3,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$MAX_PATH_SAFE_IDE_VERSION_LIST"
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174174
# attinyx8
175-
# LTO=disable, chip=88, clock=16external (external clock), eesave=aenable, bod=1v8
176-
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx8:LTO=disable,chip=88,clock=16external,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
175+
# LTO=disable, chip=88, clock=16external (external clock), eesave=aenable, bod=disable
176+
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx8:LTO=disable,chip=88,clock=16external,eesave=aenable,bod=disable,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
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# clock=4internal, eesave=disable, bod=1v8
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- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx8:LTO=disable,chip=88,clock=1internal,eesave=disable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
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# clock=1internal, eesave=disable, bod=1v8
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- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx8:LTO=disable,chip=88,clock=1internal,eesave=disable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
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# LTO=enable, bod=2v7
182-
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx8:LTO=enable,chip=88,clock=8internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$LTO_IDE_VERSION_LIST"
182+
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx8:LTO=enable,chip=88,clock=8internal,eesave=aenable,bod=2v7,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$LTO_IDE_VERSION_LIST"
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# chip=48, bod=4v3
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# BOD doesn't affect compilation so only a single compilation needs to be done to check the bod=4v3 option
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# Some example sketches are too big to compile for this chip and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
186-
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx8:LTO=disable,chip=48,clock=8internal,eesave=aenable,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
186+
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx8:LTO=disable,chip=48,clock=8internal,eesave=aenable,bod=4v3,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
187187

188188
# attinyx8opti
189189
# Compilation-wise, the opti boards should be copies of non-opti version so only a single compilation is needed to test each board configuration
190-
# LTO=disable, chip=88, clock=8internal, bod=1v8
191-
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx8opti:LTO=disable,chip=88,clock=8internal,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
190+
# LTO=disable, chip=88, clock=8internal, bod=disable
191+
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx8opti:LTO=disable,chip=88,clock=8internal,bod=disable,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
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# chip=48, bod=1v8
193193
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx8opti:LTO=disable,chip=88,clock=8internal,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
194194
# LTO=enable, bod=2v7, clock=16external (external clock)
195-
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx8opti:LTO=enable,chip=88,clock=16external,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$LTO_IDE_VERSION_LIST"
195+
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx8opti:LTO=enable,chip=88,clock=16external,bod=2v7,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$LTO_IDE_VERSION_LIST"
196196
# bod=4v3
197197
# BOD doesn't affect compilation so only a single compilation needs to be done to check the bod=4v3 option
198198
# Some example sketches are too big to compile for this chip and adding additional jobs for each library/example is not possible due to Travis CI's 200 job limit, so I am forced to only do a single test compilation
199-
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx8opti:LTO=disable,chip=48,clock=8internal,bod=1v8,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
199+
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx8opti:LTO=disable,chip=48,clock=8internal,bod=4v3,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
200+
201+
# attinyx8micr
202+
# need to check everything because of prescaler and pin mapping wackiness
203+
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx8micr:LTO=enable,sketchclock=16external,bod=disable,neopixelport=portb,millis=enabled" ALLOW_FAILURE="false" IDE_VERSION_LIST="$LTO_IDE_VERSION_LIST"
204+
205+
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx8micr:LTO=enable,sketchclock=1external16,bod=4v3,neopixelport=portb,millis=enabled,pinmapping=mhtiny" ALLOW_FAILURE="false" IDE_VERSION_LIST="$LTO_IDE_VERSION_LIST"
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201207
# attinyx7
202208
# LTO=disable, chip=167, clock=8internal, eesave=aenable, bod=1v8, pinmapping=new
@@ -252,9 +258,11 @@ env:
252258
- SKETCH_PATH="${APPLICATION_FOLDER}/arduino/examples/01.Basics/BareMinimum/BareMinimum.ino" BOARD_ID="ATTinyCore:avr:attinyx7opti:LTO=disable,chip=167,clock=184external,bod=1v8,neopixelport=portb,millis=enabled,pinmapping=new" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
253259

254260
# attinyx7micr
255-
# No option for clock - always 16external, different pin mapping, no chip selection
261+
# uses sketchclock, different pin mapping, no chip selection
256262
# bod=4v3, pinmapping=digi
257-
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx7micr:LTO=disable,bod=4v3,neopixelport=portb,millis=enabled,pinmapping=digi" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
263+
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx7micr:LTO=disable,bod=4v3,neopixelport=portb,millis=enabled,pinmapping=digi,sketchclock=16external" ALLOW_FAILURE="false" IDE_VERSION_LIST="$FULL_IDE_VERSION_LIST"
264+
# bod=disable, pinmapping=new sketchclock=4external16
265+
- SKETCH_PATH="${SKETCHBOOK_FOLDER}/hardware/ATTinyCore/avr/libraries" BOARD_ID="ATTinyCore:avr:attinyx7micr:LTO=enable,bod=disable,neopixelport=portb,millis=enabled,pinmapping=new,sketchclock=4external16" ALLOW_FAILURE="false" IDE_VERSION_LIST="$LTO_IDE_VERSION_LIST"
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259267
# attinyx61
260268
# LTO=disable, TimerClockSource=default, chip=861, clock=8internal, eesave=aenable, bod=1v8

‎avr/boards.txt

+1-1
Original file line numberDiff line numberDiff line change
@@ -244,7 +244,7 @@ attinyx4opti.build.extra_flags={build.millis} {build.neopixelport}
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attinyx4micr.name=ATtiny84a (Micronucleus / California STEAM)
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attinyx4micr.upload.tool=micronucleus
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attinyx4micr.upload.protocol=usb
247-
attinyx4micr.menu.build.usb=
247+
attinyx4micr.build.usb=
248248
attinyx4micr.build.board=AVR_ATTINYX4
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attinyx4micr.bootloader.tool=avrdude
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attinyx4micr.bootloader.unlock_bits=0xFF

‎avr/extras/UsingMicronucleus.md

+4-4
Original file line numberDiff line numberDiff line change
@@ -58,11 +58,11 @@ In order to make the entry modes work correctly - regardless of sketch behavior
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```
5959
uint8_t resetcause;
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if(!GPIOR0) { //if this isn't 0 at start of setup, bootloader must have set it.
61-
resetcause = MCUSR;
62-
MCUSR=0;
61+
resetcause = MCUSR;
62+
MCUSR=0;
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} else {
64-
resetcause=GPIOR0;
65-
GPIOR0=0; //not needed if you dont use GPIOR0.
64+
resetcause=GPIOR0;
65+
GPIOR0=0; //not needed if you dont use GPIOR0.
6666
}
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```
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