main.stanza

; Generated by JITX 3.26.0
#use-added-syntax(jitx)
defpackage main :
  import core
  import jitx
  import jitx/commands
  import jitx/parts

  import helpers
  import jsl
  import rf-sandbox/board

; Define the shape/size of the board
val board-shape = RoundedRectangle(50.0, 60.0, 3.25)

pcb-module power-management : 
  port P3v3 : power
  inst terminal-block : connectors/components/LSF-SMT/component(num-poles = 3)

  val cxt-3v3 = power-systems/DC-DC/buck/BuckConstraints(
    v-in = min-max(4.9, 5.1)
    v-out = 3.3 +/- (3 %)
    v-in-ripple-max = 0.050
    v-out-ripple-max = 0.030
    i-out = 1.0 +/- (20 %)
    freq = 1.2e6
    K = (40 %)
  )

  inst DCDC-3v3 : TI-vreg/components/TPS6208x/circuit(
    TI-vreg/components/TPS6208x/TPS62082DSG
    cxt-3v3
    snooze-mode = false
    snooze-conn? = create-resistor(
        resistance = 0.0,
        precision = (1 %)
      )
    )
  net (terminal-block.p[1] DCDC-3v3.conv.VIN.V+)
  net (terminal-block.p[2] DCDC-3v3.conv.VIN.V-)
  net (P3v3 DCDC-3v3.conv.VOUT)

; Module to run as a design
pcb-module my-design :
  inst da :  components/CMD291P4/module[4]
  inst adar : components/ADAR3000/component
  inst pwr : power-management

  inst ch3-vias : se-via-cage()[2]
  inst ch4-vias : se-via-cage()[2]

  ; GND nets
  net GND (da[0].power.V- )
  for i in 1 to 4 do :
    net (GND da[i].power.V-)
    net (pwr.P3v3 da[i].power)
  for i in 0 to 2 :
    net (ch3-vias[i].COMMON, ch4-vias[i].COMMON, GND)
  for i in pins(adar.VSS):
    net (i GND)
  symbol(GND) = GND-SYMB

  ; Direct, no via specified
  topo-net(adar.RF-OUT[0] => da[0].rf-in)
  topo-net(adar.RF-OUT[1] => da[1].rf-in)

  ; Specify topology of vias
  topo-net(adar.RF-OUT[2] => ch3-vias[0].sig-in => ch3-vias[1].sig-out => da[2].rf-in)
  topo-net(adar.RF-OUT[3] => ch4-vias[0].sig-in => ch4-vias[1].sig-out => da[3].rf-in)

  ; CH1 timing constraint
  structure(adar.RF-OUT[0] => da[0].rf-in) = se-RF
  timing(adar.RF-OUT[0], da[0].rf-in) = TimingConstraint(100.0e-12 +/- 1.0e-15)
  insertion-loss(adar.RF-OUT[0], da[0].rf-in) = InsertionLossConstraint(min-max(0.0, 8.0))

  ; CH2 CH3, CH4 matching constraints
  for i in 1 to 4 :
    structure(adar.RF-OUT[i] => da[i].rf-in) = se-RF
    timing-difference(adar.RF-OUT[i] => da[i].rf-in, adar.RF-OUT[1] => da[1].rf-in) = TimingDifferenceConstraint(0.0 +/- 1.0e-15)
    insertion-loss(adar.RF-OUT[i], da[i].rf-in) = InsertionLossConstraint(min-max(0.0, 6.0))

  geom(GND) : 
    copper-pour(LayerIndex(0), isolate = 0.125, rank = 1) = board-shape
    copper-pour(LayerIndex(2), isolate = 0.125, rank = 1) = board-shape


setup-design("starting", board-shape, signal-shrink = 0.5)

; Set the top level module (the module to be compile into a schematic and PCB)
set-main-module(my-design)

; View the results
; take a look at the BOM that was generated
view-bom(BOM-STD)
; examine the schematic that was auto-generated
view-schematic()
; view the board that was created
view-board()